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ArmLib/ArmV7: Add ISB to ArmEnableVFP 

ArmEnableVFP could crash on an out-of-order CPU. Adding an instruction barrier after writing to CPACR cures the problem.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13134 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-03-26 11:01:21 +00:00
parent eac42a514b
commit 18029bb911
4 changed files with 4 additions and 0 deletions
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1
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
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@ -347,6 +347,7 @@ ASM_PFX(ArmEnableVFP):
orr r0, r0, #0x00f00000 orr r0, r0, #0x00f00000
# Write back CPACR (Coprocessor Access Control Register) # Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2 mcr p15, 0, r0, c1, c0, 2
isb
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000 mov r0, #0x40000000
mcr p10,#0x7,r0,c8,c0,#0 mcr p10,#0x7,r0,c8,c0,#0

1
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -341,6 +341,7 @@ ArmEnableVFP
orr r0, r0, #0x00f00000 orr r0, r0, #0x00f00000
// Write back CPACR (Coprocessor Access Control Register) // Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2 mcr p15, 0, r0, c1, c0, 2
isb
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000 mov r0, #0x40000000
mcr p10,#0x7,r0,c8,c0,#0 mcr p10,#0x7,r0,c8,c0,#0

1
ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
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@ -88,6 +88,7 @@ ASM_PFX(CPSRRead):
ASM_PFX(ArmWriteCPACR): ASM_PFX(ArmWriteCPACR):
mcr p15, 0, r0, c1, c0, 2 mcr p15, 0, r0, c1, c0, 2
isb
bx lr bx lr
ASM_PFX(ArmWriteAuxCr): ASM_PFX(ArmWriteAuxCr):

1
ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
View File

@ -88,6 +88,7 @@ CPSRRead
ArmWriteCPACR ArmWriteCPACR
mcr p15, 0, r0, c1, c0, 2 mcr p15, 0, r0, c1, c0, 2
isb
bx lr bx lr
ArmWriteAuxCr ArmWriteAuxCr