mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/PL031RealTimeClock: Fixed driver to support UEFI Runtime Services
- Removed PCD base address from the macro definition. The base address needs to be fixup when the driver runs in UEFI Runtime mode - Added the PL031 controller memory region to the Runtime UEFI Memory Mapped IO - Caught the gEfiEventVirtualAddressChangeGuid event to fixup the PL031 Base address Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15435 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
9d34cac819
commit
18ee5b6d78
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -17,22 +17,22 @@
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#define __PL031_REAL_TIME_CLOCK_H__
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// PL031 Registers
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#define PL031_RTC_DR_DATA_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x000)
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#define PL031_RTC_MR_MATCH_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x004)
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#define PL031_RTC_LR_LOAD_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x008)
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#define PL031_RTC_CR_CONTROL_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x00C)
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#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x010)
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#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x014)
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#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x018)
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#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x01C)
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#define PL031_RTC_PERIPH_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE0)
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#define PL031_RTC_PERIPH_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE4)
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#define PL031_RTC_PERIPH_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE8)
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#define PL031_RTC_PERIPH_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFEC)
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#define PL031_RTC_PCELL_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF0)
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#define PL031_RTC_PCELL_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF4)
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#define PL031_RTC_PCELL_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF8)
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#define PL031_RTC_PCELL_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFFC)
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#define PL031_RTC_DR_DATA_REGISTER 0x000
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#define PL031_RTC_MR_MATCH_REGISTER 0x004
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#define PL031_RTC_LR_LOAD_REGISTER 0x008
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#define PL031_RTC_CR_CONTROL_REGISTER 0x00C
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#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010
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#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014
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#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018
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#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C
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#define PL031_RTC_PERIPH_ID0 0xFE0
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#define PL031_RTC_PERIPH_ID1 0xFE4
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#define PL031_RTC_PERIPH_ID2 0xFE8
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#define PL031_RTC_PERIPH_ID3 0xFEC
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#define PL031_RTC_PCELL_ID0 0xFF0
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#define PL031_RTC_PCELL_ID1 0xFF4
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#define PL031_RTC_PCELL_ID2 0xFF8
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#define PL031_RTC_PCELL_ID3 0xFFC
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// PL031 Values
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#define PL031_RTC_ENABLED 0x00000001
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@ -4,7 +4,7 @@
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Currently this driver does not support runtime virtual calling.
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -26,10 +26,16 @@
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/ArmPlatformSysConfigLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiRuntimeServicesTableLib.h>
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#include <Library/UefiRuntimeLib.h>
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#include <Protocol/RealTimeClock.h>
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#include <Guid/GlobalVariable.h>
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#include <Guid/EventGroup.h>
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#include <Drivers/PL031RealTimeClock.h>
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#include <ArmPlatform.h>
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@ -37,6 +43,8 @@
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STATIC CONST CHAR16 mTimeZoneVariableName[] = L"PL031RtcTimeZone";
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STATIC CONST CHAR16 mDaylightVariableName[] = L"PL031RtcDaylight";
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STATIC BOOLEAN mPL031Initialized = FALSE;
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STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
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STATIC UINTN mPL031RtcBase;
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EFI_STATUS
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IdentifyPL031 (
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@ -46,19 +54,19 @@ IdentifyPL031 (
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EFI_STATUS Status;
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// Check if this is a PrimeCell Peripheral
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if ( (MmioRead8 (PL031_RTC_PCELL_ID0) != 0x0D)
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|| (MmioRead8 (PL031_RTC_PCELL_ID1) != 0xF0)
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|| (MmioRead8 (PL031_RTC_PCELL_ID2) != 0x05)
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|| (MmioRead8 (PL031_RTC_PCELL_ID3) != 0xB1)) {
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if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID0) != 0x0D)
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|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID1) != 0xF0)
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|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID2) != 0x05)
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|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID3) != 0xB1)) {
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Status = EFI_NOT_FOUND;
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goto EXIT;
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}
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// Check if this PrimeCell Peripheral is the PL031 Real Time Clock
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if ( (MmioRead8 (PL031_RTC_PERIPH_ID0) != 0x31)
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|| (MmioRead8 (PL031_RTC_PERIPH_ID1) != 0x10)
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|| ((MmioRead8 (PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
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|| (MmioRead8 (PL031_RTC_PERIPH_ID3) != 0x00)) {
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if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID0) != 0x31)
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|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID1) != 0x10)
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|| ((MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
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|| (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID3) != 0x00)) {
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Status = EFI_NOT_FOUND;
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goto EXIT;
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}
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@ -83,18 +91,18 @@ InitializePL031 (
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}
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// Ensure interrupts are masked. We do not want RTC interrupts in UEFI
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if ((MmioRead32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) {
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MmioOr32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
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if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) {
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MmioOr32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
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}
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// Clear any existing interrupts
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if ((MmioRead32 (PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED) {
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MmioOr32 (PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);
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if ((MmioRead32 (mPL031RtcBase + PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED) {
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MmioOr32 (mPL031RtcBase + PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);
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}
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// Start the clock counter
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if ((MmioRead32 (PL031_RTC_CR_CONTROL_REGISTER) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED) {
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MmioOr32 (PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);
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if ((MmioRead32 (mPL031RtcBase + PL031_RTC_CR_CONTROL_REGISTER) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED) {
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MmioOr32 (mPL031RtcBase + PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);
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}
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mPL031Initialized = TRUE;
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@ -267,7 +275,7 @@ LibGetTime (
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Status = ArmPlatformSysConfigGet (SYS_CFG_RTC, &EpochSeconds);
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if (Status == EFI_UNSUPPORTED) {
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// Battery backed up hardware RTC does not exist, revert to PL031
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EpochSeconds = MmioRead32 (PL031_RTC_DR_DATA_REGISTER);
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EpochSeconds = MmioRead32 (mPL031RtcBase + PL031_RTC_DR_DATA_REGISTER);
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Status = EFI_SUCCESS;
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} else if (EFI_ERROR (Status)) {
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// Battery backed up hardware RTC exists but could not be read due to error. Abort.
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@ -275,7 +283,7 @@ LibGetTime (
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} else {
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// Battery backed up hardware RTC exists and we read the time correctly from it.
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// Now sync the PL031 to the new time.
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MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
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MmioWrite32 (mPL031RtcBase + PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
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}
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// Ensure Time is a valid pointer
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@ -484,7 +492,7 @@ LibSetTime (
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// Set the PL031
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MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
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MmioWrite32 (mPL031RtcBase + PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
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// The accesses to Variable Services can be very slow, because we may be writing to Flash.
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// Do this after having set the RTC.
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@ -579,46 +587,6 @@ LibSetWakeupTime (
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return EFI_UNSUPPORTED;
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}
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/**
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This is the declaration of an EFI image entry point. This can be the entry point to an application
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written to this specification, an EFI boot service driver, or an EFI runtime driver.
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@param ImageHandle Handle that identifies the loaded image.
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@param SystemTable System Table for this image.
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@retval EFI_SUCCESS The operation completed successfully.
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**/
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EFI_STATUS
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EFIAPI
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LibRtcInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_HANDLE Handle;
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// Setup the setters and getters
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gRT->GetTime = LibGetTime;
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gRT->SetTime = LibSetTime;
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gRT->GetWakeupTime = LibGetWakeupTime;
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gRT->SetWakeupTime = LibSetWakeupTime;
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// Install the protocol
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Handle = NULL;
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Status = gBS->InstallMultipleProtocolInterfaces (
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&Handle,
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&gEfiRealTimeClockArchProtocolGuid, NULL,
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NULL
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);
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return Status;
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}
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/**
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Fixup internal data so that EFI can be call in virtual mode.
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Call the passed in Child Notify event and convert any pointers in
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@ -640,5 +608,75 @@ LibRtcVirtualNotifyEvent (
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// to virtual address. After the OS transitions to calling in virtual mode, all future
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// runtime calls will be made in virtual mode.
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//
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EfiConvertPointer (0x0, (VOID**)&mPL031RtcBase);
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return;
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}
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/**
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This is the declaration of an EFI image entry point. This can be the entry point to an application
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written to this specification, an EFI boot service driver, or an EFI runtime driver.
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@param ImageHandle Handle that identifies the loaded image.
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@param SystemTable System Table for this image.
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@retval EFI_SUCCESS The operation completed successfully.
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**/
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EFI_STATUS
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EFIAPI
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LibRtcInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_HANDLE Handle;
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// Initialize RTC Base Address
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mPL031RtcBase = PcdGet32 (PcdPL031RtcBase);
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// Declare the controller as EFI_MEMORY_RUNTIME
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Status = gDS->AddMemorySpace (
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EfiGcdMemoryTypeMemoryMappedIo,
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mPL031RtcBase, SIZE_4KB,
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EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = gDS->SetMemorySpaceAttributes (mPL031RtcBase, SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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// Setup the setters and getters
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gRT->GetTime = LibGetTime;
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gRT->SetTime = LibSetTime;
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gRT->GetWakeupTime = LibGetWakeupTime;
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gRT->SetWakeupTime = LibSetWakeupTime;
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// Install the protocol
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Handle = NULL;
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Status = gBS->InstallMultipleProtocolInterfaces (
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&Handle,
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&gEfiRealTimeClockArchProtocolGuid, NULL,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Register for the virtual address change event
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//
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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LibRtcVirtualNotifyEvent,
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NULL,
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&gEfiEventVirtualAddressChangeGuid,
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&mRtcVirtualAddrChangeEvent
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);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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@ -1,7 +1,7 @@
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#/** @file
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#
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# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -35,6 +35,11 @@
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DebugLib
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PcdLib
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ArmPlatformSysConfigLib
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DxeServicesTableLib
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UefiRuntimeLib
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[Guids]
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gEfiEventVirtualAddressChangeGuid
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[Pcd]
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gArmPlatformTokenSpaceGuid.PcdPL031RtcBase
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