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UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo 

Change the variable name from mInternalGr3 to mInternalCr3.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Sheng Wei 2020-10-27 15:59:41 +08:00 committed by mergify[bot]
parent e6a12a0fc8
commit 1a110fcd4e
1 changed files with 5 additions and 5 deletions
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10
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
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@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
}; };
UINTN mInternalGr3; UINTN mInternalCr3;
/** /**
Set the internal page table base address. Set the internal page table base address.
@ -46,7 +46,7 @@ SetPageTableBase (
IN UINTN Cr3 IN UINTN Cr3
) )
{ {
mInternalGr3 = Cr3; mInternalCr3 = Cr3;
} }
/** /**
@ -59,8 +59,8 @@ GetPageTableBase (
VOID VOID
) )
{ {
if (mInternalGr3 != 0) { if (mInternalCr3 != 0) {
return mInternalGr3; return mInternalCr3;
} }
return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
} }
@ -252,7 +252,7 @@ ConvertPageEntryAttribute (
if ((Attributes & EFI_MEMORY_RO) != 0) { if ((Attributes & EFI_MEMORY_RO) != 0) {
if (IsSet) { if (IsSet) {
NewPageEntry &= ~(UINT64)IA32_PG_RW; NewPageEntry &= ~(UINT64)IA32_PG_RW;
if (mInternalGr3 != 0) { if (mInternalCr3 != 0) {
// Environment setup // Environment setup
// ReadOnly page need set Dirty bit for shadow stack // ReadOnly page need set Dirty bit for shadow stack
NewPageEntry |= IA32_PG_D; NewPageEntry |= IA32_PG_D;