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Hack in some DSB, ISB syncronization primatives. Need to do it a little cleaner. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10023 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-02-18 04:25:31 +00:00
parent 5dea9bd6e6
commit 1a27eb4887
5 changed files with 307 additions and 5 deletions
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95
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S Normal file
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@ -0,0 +1,95 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(Cp15IdCode)
.globl ASM_PFX(Cp15CacheInfo)
.globl ASM_PFX(ArmEnableInterrupts)
.globl ASM_PFX(ArmDisableInterrupts)
.globl ASM_PFX(ArmGetInterruptState)
.globl ASM_PFX(ArmInvalidateTlb)
.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
.globl ASM_PFX(ArmGetTranslationTableBaseAddress)
.globl ASM_PFX(ArmSetDomainAccessControl)
.globl ASM_PFX(CPSRMaskInsert)
.globl ASM_PFX(CPSRRead)
#------------------------------------------------------------------------------
ASM_PFX(Cp15IdCode):
mrc p15,0,R0,c0,c0,0
bx LR
ASM_PFX(Cp15CacheInfo):
mrc p15,0,R0,c0,c0,1
bx LR
ASM_PFX(ArmEnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR
ASM_PFX(ArmDisableInterrupts):
mrs R0,CPSR
orr R1,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmGetInterruptState):
mrs R0,CPSR
tst R0,#0x80 @Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
mcr p15,0,r0,c8,c7,0
bx lr
ASM_PFX(ArmSetTranslationTableBaseAddress):
mcr p15,0,r0,c2,c0,0
bx lr
ASM_PFX(ArmGetTranslationTableBaseAddress):
mrc p15,0,r0,c2,c0,0
bx lr
ASM_PFX(ArmSetDomainAccessControl):
mcr p15,0,r0,c3,c0,0
bx lr
ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
stmfd sp!, {r4-r12, lr} @ save all the banked registers
mov r3, sp @ copy the stack pointer into a non-banked register
mrs r2, cpsr @ read the cpsr
bic r2, r2, r0 @ clear mask in the cpsr
and r1, r1, r0 @ clear bits outside the mask in the input
orr r2, r2, r1 @ set field
msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
mov sp, r3 @ restore stack pointer
ldmfd sp!, {r4-r12, lr} @ restore registers
bx lr @ return (hopefully thumb-safe!)
ASM_PFX(CPSRRead):
mrs r0, cpsr
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

139
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm Normal file
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@ -0,0 +1,139 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
//
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
EXPORT Cp15IdCode
EXPORT Cp15CacheInfo
EXPORT ArmEnableInterrupts
EXPORT ArmDisableInterrupts
EXPORT ArmGetInterruptState
EXPORT ArmInvalidateTlb
EXPORT ArmSetTranslationTableBaseAddress
EXPORT ArmGetTranslationTableBaseAddress
EXPORT ArmSetDomainAccessControl
EXPORT CPSRMaskInsert
EXPORT CPSRRead
AREA ArmLibSupport, CODE, READONLY
Cp15IdCode
DSB
ISB
mrc p15,0,R0,c0,c0,0
DSB
ISB
bx LR
Cp15CacheInfo
DSB
ISB
mrc p15,0,R0,c0,c0,1
DSB
ISB
bx LR
ArmEnableInterrupts
DSB
ISB
mrs R0,CPSR
bic R0,R0,#0x80 ;Enable IRQ interrupts
msr CPSR_c,R0
DSB
ISB
bx LR
ArmDisableInterrupts
DSB
ISB
mrs R0,CPSR
orr R1,R0,#0x80 ;Disable IRQ interrupts
msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
DSB
ISB
bx LR
ArmGetInterruptState
DSB
ISB
mrs R0,CPSR
tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
DSB
ISB
bx LR
ArmInvalidateTlb
DSB
ISB
mov r0,#0
mcr p15,0,r0,c8,c7,0
DSB
ISB
bx lr
ArmSetTranslationTableBaseAddress
DSB
ISB
mcr p15,0,r0,c2,c0,0
DSB
ISB
bx lr
ArmGetTranslationTableBaseAddress
DSB
ISB
mrc p15,0,r0,c2,c0,0
DSB
ISB
bx lr
ArmSetDomainAccessControl
DSB
ISB
mcr p15,0,r0,c3,c0,0
DSB
ISB
bx lr
CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
DSB
ISB
stmfd sp!, {r4-r12, lr} ; save all the banked registers
mov r3, sp ; copy the stack pointer into a non-banked register
mrs r2, cpsr ; read the cpsr
bic r2, r2, r0 ; clear mask in the cpsr
and r1, r1, r0 ; clear bits outside the mask in the input
orr r2, r2, r1 ; set field
msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
mov sp, r3 ; restore stack pointer
ldmfd sp!, {r4-r12, lr} ; restore registers
DSB
ISB
bx lr ; return (hopefully thumb-safe!)
CPSRRead
DSB
ISB
mrs r0, cpsr
DSB
ISB
bx lr
END

4
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
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@ -22,8 +22,8 @@
LIBRARY_CLASS = ArmLib
[Sources.common]
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
ArmLibSupport.S | GCC
ArmLibSupport.asm | RVCT
../Common/ArmLib.c
ArmV7Support.S | GCC

6
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
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@ -17,13 +17,13 @@
INF_VERSION = 0x00010005
BASE_NAME = ArmV7LibPrePi
FILE_GUID = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73
MODULE_TYPE = DXE_DRIVER
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmLib
[Sources.common]
../Common/ArmLibSupport.S | GCC
../Common/ArmLibSupport.asm | RVCT
ArmLibSupport.S | GCC
ArmLibSupport.asm | RVCT
../Common/ArmLib.c
ArmV7Support.S | GCC

68
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
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@ -40,59 +40,101 @@ XP_ON EQU ( 0x1:SHL:23 )
ArmInvalidateDataCacheEntryByMVA
DSB
ISB
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
DSB
ISB
BX lr
ArmCleanDataCacheEntryByMVA
DSB
ISB
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
DSB
ISB
BX lr
ArmCleanInvalidateDataCacheEntryByMVA
DSB
ISB
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
DSB
ISB
BX lr
ArmInvalidateDataCacheEntryBySetWay
DSB
ISB
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
DSB
ISB
bx lr
ArmCleanInvalidateDataCacheEntryBySetWay
DSB
ISB
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
DSB
ISB
bx lr
ArmCleanDataCacheEntryBySetWay
DSB
ISB
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
DSB
ISB
bx lr
ArmDrainWriteBuffer
DSB
ISB
mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
DSB
ISB
bx lr
ArmInvalidateInstructionCache
DSB
ISB
MOV R0,#0
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
MOV R0,#0
MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
DSB
ISB
BX LR
ArmEnableMmu
DSB
ISB
mrc p15,0,R0,c1,c0,0
orr R0,R0,#1
mcr p15,0,R0,c1,c0,0
DSB
ISB
bx LR
ArmMmuEnabled
DSB
ISB
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
DSB
ISB
bx LR
ArmDisableMmu
DSB
ISB
mov R0,#0
mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
mrc p15,0,R0,c1,c0,0
@ -102,46 +144,72 @@ ArmDisableMmu
mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
mov R0,#0
mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
DSB
ISB
bx LR
ArmEnableDataCache
DSB
ISB
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmDisableDataCache
DSB
ISB
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmEnableInstructionCache
DSB
ISB
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmDisableInstructionCache
DSB
ISB
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB
ISB
BX LR
ArmEnableBranchPrediction
DSB
ISB
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
DSB
ISB
bx LR
ArmDisableBranchPrediction
DSB
ISB
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0
DSB
ISB
bx LR
END