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IntelFspPkg&IntelFspWrapperPkg: Remove them 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1819

Since there are V2 FSP packages (IntelFsp2Pkg, IntelFsp2WrapperPkg),
this patch removes IntelFspPkg, IntelFspWrapperPkg to remove obsolete
code in edk2 repo.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Ray Ni 2019-06-11 16:59:11 +08:00
parent e8015f2fac
commit 1a48fda531
132 changed files with 0 additions and 17402 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

450
IntelFspPkg/FspDxeIpl/DxeIpl.c
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@ -1,450 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "DxeIpl.h"
//
// Module Globals used in the DXE to PEI hand off
// These must be module globals, so the stack can be switched
//
CONST EFI_DXE_IPL_PPI mDxeIplPpi = {
DxeLoadCore
};
CONST EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI mCustomGuidedSectionExtractionPpi = {
CustomGuidedSectionExtract
};
CONST EFI_PEI_DECOMPRESS_PPI mDecompressPpi = {
Decompress
};
CONST EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gEfiDxeIplPpiGuid,
(VOID *) &mDxeIplPpi
},
{
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiDecompressPpiGuid,
(VOID *) &mDecompressPpi
}
};
CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiEndOfPeiSignalPpiGuid,
NULL
};
/**
Entry point of DXE IPL PEIM.
This function installs DXE IPL PPI and Decompress PPI. It also reloads
itself to memory on non-S3 resume boot path.
@param[in] FileHandle Handle of the file being invoked.
@param[in] PeiServices Describes the list of possible PEI Services.
@retval EFI_SUCESS The entry point of DXE IPL PEIM executes successfully.
@retval Others Some error occurs during the execution of this function.
**/
EFI_STATUS
EFIAPI
PeimInitializeDxeIpl (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
EFI_GUID *ExtractHandlerGuidTable;
UINTN ExtractHandlerNumber;
EFI_PEI_PPI_DESCRIPTOR *GuidPpi;
//
// Get custom extract guided section method guid list
//
ExtractHandlerNumber = ExtractGuidedSectionGetGuidList (&ExtractHandlerGuidTable);
//
// Install custom extraction guid PPI
//
if (ExtractHandlerNumber > 0) {
GuidPpi = (EFI_PEI_PPI_DESCRIPTOR *) AllocatePool (ExtractHandlerNumber * sizeof (EFI_PEI_PPI_DESCRIPTOR));
ASSERT (GuidPpi != NULL);
while (ExtractHandlerNumber-- > 0) {
GuidPpi->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
GuidPpi->Ppi = (VOID *) &mCustomGuidedSectionExtractionPpi;
GuidPpi->Guid = &ExtractHandlerGuidTable[ExtractHandlerNumber];
Status = PeiServicesInstallPpi (GuidPpi++);
ASSERT_EFI_ERROR(Status);
}
}
//
// Install DxeIpl and Decompress PPIs.
//
Status = PeiServicesInstallPpi (mPpiList);
ASSERT_EFI_ERROR(Status);
return Status;
}
/**
The ExtractSection() function processes the input section and
returns a pointer to the section contents. If the section being
extracted does not require processing (if the section
GuidedSectionHeader.Attributes has the
EFI_GUIDED_SECTION_PROCESSING_REQUIRED field cleared), then
OutputBuffer is just updated to point to the start of the
section's contents. Otherwise, *Buffer must be allocated
from PEI permanent memory.
@param[in] This Indicates the
EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI instance.
Buffer containing the input GUIDed section to be
processed. OutputBuffer OutputBuffer is
allocated from PEI permanent memory and contains
the new section stream.
@param[in] InputSection A pointer to the input buffer, which contains
the input section to be processed.
@param[out] OutputBuffer A pointer to a caller-allocated buffer, whose
size is specified by the contents of OutputSize.
@param[out] OutputSize A pointer to a caller-allocated
UINTN in which the size of *OutputBuffer
allocation is stored. If the function
returns anything other than EFI_SUCCESS,
the value of OutputSize is undefined.
@param[out] AuthenticationStatus A pointer to a caller-allocated
UINT32 that indicates the
authentication status of the
output buffer. If the input
section's GuidedSectionHeader.
Attributes field has the
EFI_GUIDED_SECTION_AUTH_STATUS_VALID
bit as clear,
AuthenticationStatus must return
zero. These bits reflect the
status of the extraction
operation. If the function
returns anything other than
EFI_SUCCESS, the value of
AuthenticationStatus is
undefined.
@retval EFI_SUCCESS The InputSection was
successfully processed and the
section contents were returned.
@retval EFI_OUT_OF_RESOURCES The system has insufficient
resources to process the request.
@retval EFI_INVALID_PARAMETER The GUID in InputSection does
not match this instance of the
GUIDed Section Extraction PPI.
**/
EFI_STATUS
EFIAPI
CustomGuidedSectionExtract (
IN CONST EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI *This,
IN CONST VOID *InputSection,
OUT VOID **OutputBuffer,
OUT UINTN *OutputSize,
OUT UINT32 *AuthenticationStatus
)
{
EFI_STATUS Status;
UINT8 *ScratchBuffer;
UINT32 ScratchBufferSize;
UINT32 OutputBufferSize;
UINT16 SectionAttribute;
//
// Init local variable
//
ScratchBuffer = NULL;
//
// Call GetInfo to get the size and attribute of input guided section data.
//
Status = ExtractGuidedSectionGetInfo (
InputSection,
&OutputBufferSize,
&ScratchBufferSize,
&SectionAttribute
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "GetInfo from guided section Failed - %r\n", Status));
return Status;
}
if (ScratchBufferSize != 0) {
//
// Allocate scratch buffer
//
ScratchBuffer = AllocatePages (EFI_SIZE_TO_PAGES (ScratchBufferSize));
if (ScratchBuffer == NULL) {
return EFI_OUT_OF_RESOURCES;
}
}
if (((SectionAttribute & EFI_GUIDED_SECTION_PROCESSING_REQUIRED) != 0) && OutputBufferSize > 0) {
//
// Allocate output buffer
//
*OutputBuffer = AllocatePages (EFI_SIZE_TO_PAGES (OutputBufferSize) + 1);
if (*OutputBuffer == NULL) {
return EFI_OUT_OF_RESOURCES;
}
DEBUG ((DEBUG_INFO, "Customized Guided section Memory Size required is 0x%x and address is 0x%p\n", OutputBufferSize, *OutputBuffer));
//
// *OutputBuffer still is one section. Adjust *OutputBuffer offset,
// skip EFI section header to make section data at page alignment.
//
*OutputBuffer = (VOID *)((UINT8 *) *OutputBuffer + EFI_PAGE_SIZE - sizeof (EFI_COMMON_SECTION_HEADER));
}
Status = ExtractGuidedSectionDecode (
InputSection,
OutputBuffer,
ScratchBuffer,
AuthenticationStatus
);
if (EFI_ERROR (Status)) {
//
// Decode failed
//
DEBUG ((DEBUG_ERROR, "Extract guided section Failed - %r\n", Status));
return Status;
}
*OutputSize = (UINTN) OutputBufferSize;
return EFI_SUCCESS;
}
/**
Decompresses a section to the output buffer.
This function looks up the compression type field in the input section and
applies the appropriate compression algorithm to compress the section to a
callee allocated buffer.
@param[in] This Points to this instance of the
EFI_PEI_DECOMPRESS_PEI PPI.
@param[in] CompressionSection Points to the compressed section.
@param[out] OutputBuffer Holds the returned pointer to the decompressed
sections.
@param[out] OutputSize Holds the returned size of the decompress
section streams.
@retval EFI_SUCCESS The section was decompressed successfully.
OutputBuffer contains the resulting data and
OutputSize contains the resulting size.
**/
EFI_STATUS
EFIAPI
Decompress (
IN CONST EFI_PEI_DECOMPRESS_PPI *This,
IN CONST EFI_COMPRESSION_SECTION *CompressionSection,
OUT VOID **OutputBuffer,
OUT UINTN *OutputSize
)
{
EFI_STATUS Status;
UINT8 *DstBuffer;
UINT8 *ScratchBuffer;
UINT32 DstBufferSize;
UINT32 ScratchBufferSize;
VOID *CompressionSource;
UINT32 CompressionSourceSize;
UINT32 UncompressedLength;
UINT8 CompressionType;
if (CompressionSection->CommonHeader.Type != EFI_SECTION_COMPRESSION) {
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
if (IS_SECTION2 (CompressionSection)) {
CompressionSource = (VOID *) ((UINT8 *) CompressionSection + sizeof (EFI_COMPRESSION_SECTION2));
CompressionSourceSize = (UINT32) (SECTION2_SIZE (CompressionSection) - sizeof (EFI_COMPRESSION_SECTION2));
UncompressedLength = ((EFI_COMPRESSION_SECTION2 *) CompressionSection)->UncompressedLength;
CompressionType = ((EFI_COMPRESSION_SECTION2 *) CompressionSection)->CompressionType;
} else {
CompressionSource = (VOID *) ((UINT8 *) CompressionSection + sizeof (EFI_COMPRESSION_SECTION));
CompressionSourceSize = (UINT32) (SECTION_SIZE (CompressionSection) - sizeof (EFI_COMPRESSION_SECTION));
UncompressedLength = CompressionSection->UncompressedLength;
CompressionType = CompressionSection->CompressionType;
}
//
// This is a compression set, expand it
//
switch (CompressionType) {
case EFI_STANDARD_COMPRESSION:
//
// Load EFI standard compression.
// For compressed data, decompress them to destination buffer.
//
Status = UefiDecompressGetInfo (
CompressionSource,
CompressionSourceSize,
&DstBufferSize,
&ScratchBufferSize
);
if (EFI_ERROR (Status)) {
//
// GetInfo failed
//
DEBUG ((DEBUG_ERROR, "Decompress GetInfo Failed - %r\n", Status));
return EFI_NOT_FOUND;
}
//
// Allocate scratch buffer
//
ScratchBuffer = AllocatePages (EFI_SIZE_TO_PAGES (ScratchBufferSize));
if (ScratchBuffer == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Allocate destination buffer, extra one page for adjustment
//
DstBuffer = AllocatePages (EFI_SIZE_TO_PAGES (DstBufferSize) + 1);
if (DstBuffer == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// DstBuffer still is one section. Adjust DstBuffer offset, skip EFI section header
// to make section data at page alignment.
//
DstBuffer = DstBuffer + EFI_PAGE_SIZE - sizeof (EFI_COMMON_SECTION_HEADER);
//
// Call decompress function
//
Status = UefiDecompress (
CompressionSource,
DstBuffer,
ScratchBuffer
);
if (EFI_ERROR (Status)) {
//
// Decompress failed
//
DEBUG ((DEBUG_ERROR, "Decompress Failed - %r\n", Status));
return EFI_NOT_FOUND;
}
break;
case EFI_NOT_COMPRESSED:
//
// Allocate destination buffer
//
DstBufferSize = UncompressedLength;
DstBuffer = AllocatePages (EFI_SIZE_TO_PAGES (DstBufferSize) + 1);
if (DstBuffer == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Adjust DstBuffer offset, skip EFI section header
// to make section data at page alignment.
//
DstBuffer = DstBuffer + EFI_PAGE_SIZE - sizeof (EFI_COMMON_SECTION_HEADER);
//
// stream is not actually compressed, just encapsulated. So just copy it.
//
CopyMem (DstBuffer, CompressionSource, DstBufferSize);
break;
default:
//
// Don't support other unknown compression type.
//
ASSERT (FALSE);
return EFI_NOT_FOUND;
}
*OutputSize = DstBufferSize;
*OutputBuffer = DstBuffer;
return EFI_SUCCESS;
}
/**
Main entry point to last PEIM.
This function finds DXE Core in the firmware volume and transfer the control to
DXE core.
@param[in] This Entry point for DXE IPL PPI.
@param[in] PeiServices General purpose services available to every PEIM.
@param[in] HobList Address to the Pei HOB list.
@return EFI_SUCCESS DXE core was successfully loaded.
@return EFI_OUT_OF_RESOURCES There are not enough resources to load DXE core.
**/
EFI_STATUS
EFIAPI
DxeLoadCore (
IN CONST EFI_DXE_IPL_PPI *This,
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_HOB_POINTERS HobList
)
{
EFI_STATUS Status;
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP HOB is located at 0x%08X\n", HobList));
//
// End of PEI phase signal
//
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
ASSERT_EFI_ERROR (Status);
//
// Give control back to BootLoader after FspInit
//
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP is waiting for NOTIFY\n"));
FspInitDone ();
//
// BootLoader called FSP again through NotifyPhase
//
FspWaitForNotify ();
//
// Give control back to the boot loader framework caller
//
DEBUG ((DEBUG_INFO | DEBUG_INIT, "============= PEIM FSP is Completed =============\n\n"));
SetFspApiReturnStatus(EFI_SUCCESS);
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_RDYBOOT_EXIT);
Pei2LoaderSwitchStack();
//
// Should not come here
//
while (TRUE) {
DEBUG ((DEBUG_ERROR, "No FSP API should be called after FSP is DONE!\n"));
SetFspApiReturnStatus(EFI_UNSUPPORTED);
Pei2LoaderSwitchStack();
}
return EFI_SUCCESS;
}

186
IntelFspPkg/FspDxeIpl/DxeIpl.h
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@ -1,186 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PEI_DXEIPL_H__
#define __PEI_DXEIPL_H__
#include <PiPei.h>
#include <Ppi/DxeIpl.h>
#include <Ppi/EndOfPeiPhase.h>
#include <Ppi/MemoryDiscovered.h>
#include <Ppi/Decompress.h>
#include <Ppi/FirmwareVolumeInfo.h>
#include <Ppi/GuidedSectionExtraction.h>
#include <Library/DebugLib.h>
#include <Library/PeimEntryPoint.h>
#include <Library/BaseLib.h>
#include <Library/HobLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/UefiDecompressLib.h>
#include <Library/ExtractGuidedSectionLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/FspSwitchStackLib.h>
#include <Library/FspCommonLib.h>
#include <Library/FspPlatformLib.h>
/**
Main entry point to last PEIM.
This function finds DXE Core in the firmware volume and transfer the control to
DXE core.
@param[in] This Entry point for DXE IPL PPI.
@param[in] PeiServices General purpose services available to every PEIM.
@param[in] HobList Address to the Pei HOB list.
@return EFI_SUCCESS DXE core was successfully loaded.
@return EFI_OUT_OF_RESOURCES There are not enough resources to load DXE core.
**/
EFI_STATUS
EFIAPI
DxeLoadCore (
IN CONST EFI_DXE_IPL_PPI *This,
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_HOB_POINTERS HobList
);
/**
Transfers control to DxeCore.
This function performs a CPU architecture specific operations to execute
the entry point of DxeCore with the parameters of HobList.
It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
@param[in] DxeCoreEntryPoint The entry point of DxeCore.
@param[in] HobList The start of HobList passed to DxeCore.
**/
VOID
HandOffToDxeCore (
IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
IN EFI_PEI_HOB_POINTERS HobList
);
/**
Updates the Stack HOB passed to DXE phase.
This function traverses the whole HOB list and update the stack HOB to
reflect the real stack that is used by DXE core.
@param[in] BaseAddress The lower address of stack used by DxeCore.
@param[in] Length The length of stack used by DxeCore.
**/
VOID
UpdateStackHob (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length
);
/**
The ExtractSection() function processes the input section and
returns a pointer to the section contents. If the section being
extracted does not require processing (if the section
GuidedSectionHeader.Attributes has the
EFI_GUIDED_SECTION_PROCESSING_REQUIRED field cleared), then
OutputBuffer is just updated to point to the start of the
section's contents. Otherwise, *Buffer must be allocated
from PEI permanent memory.
@param[in] This Indicates the
EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI instance.
Buffer containing the input GUIDed section to be
processed. OutputBuffer OutputBuffer is
allocated from PEI permanent memory and contains
the new section stream.
@param[in] InputSection A pointer to the input buffer, which contains
the input section to be processed.
@param[out] OutputBuffer A pointer to a caller-allocated buffer, whose
size is specified by the contents of OutputSize.
@param[out] OutputSize A pointer to a caller-allocated
UINTN in which the size of *OutputBuffer
allocation is stored. If the function
returns anything other than EFI_SUCCESS,
the value of OutputSize is undefined.
@param[out] AuthenticationStatus A pointer to a caller-allocated
UINT32 that indicates the
authentication status of the
output buffer. If the input
section's GuidedSectionHeader.
Attributes field has the
EFI_GUIDED_SECTION_AUTH_STATUS_VALID
bit as clear,
AuthenticationStatus must return
zero. These bits reflect the
status of the extraction
operation. If the function
returns anything other than
EFI_SUCCESS, the value of
AuthenticationStatus is
undefined.
@retval EFI_SUCCESS The InputSection was
successfully processed and the
section contents were returned.
@retval EFI_OUT_OF_RESOURCES The system has insufficient
resources to process the request.
@retval EFI_INVALID_PARAMETER The GUID in InputSection does
not match this instance of the
GUIDed Section Extraction PPI.
**/
EFI_STATUS
EFIAPI
CustomGuidedSectionExtract (
IN CONST EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI *This,
IN CONST VOID *InputSection,
OUT VOID **OutputBuffer,
OUT UINTN *OutputSize,
OUT UINT32 *AuthenticationStatus
);
/**
Decompresses a section to the output buffer.
This function looks up the compression type field in the input section and
applies the appropriate compression algorithm to compress the section to a
callee allocated buffer.
@param[in] This Points to this instance of the
EFI_PEI_DECOMPRESS_PEI PPI.
@param[in] CompressionSection Points to the compressed section.
@param[out] OutputBuffer Holds the returned pointer to the decompressed
sections.
@param[out] OutputSize Holds the returned size of the decompress
section streams.
@retval EFI_SUCCESS The section was decompressed successfully.
OutputBuffer contains the resulting data and
OutputSize contains the resulting size.
**/
EFI_STATUS
EFIAPI
Decompress (
IN CONST EFI_PEI_DECOMPRESS_PPI *This,
IN CONST EFI_COMPRESSION_SECTION *CompressionSection,
OUT VOID **OutputBuffer,
OUT UINTN *OutputSize
);
#endif

65
IntelFspPkg/FspDxeIpl/FspDxeIpl.inf
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@ -1,65 +0,0 @@
## @file
# PEIM for DXE IPL
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FspDxeIpl
FILE_GUID = 98C8588C-640A-4bb4-AEA0-3F81CDE17524
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = PeimInitializeDxeIpl
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32
#
[Sources]
DxeIpl.h
DxeIpl.c
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
PcdLib
MemoryAllocationLib
BaseMemoryLib
ExtractGuidedSectionLib
UefiDecompressLib
ReportStatusCodeLib
PeiServicesLib
HobLib
BaseLib
PeimEntryPoint
DebugLib
FspSwitchStackLib
UefiDecompressLib
FspCommonLib
FspPlatformLib
[Ppis]
gEfiDxeIplPpiGuid ## PRODUCES
gEfiEndOfPeiSignalPpiGuid ## SOMETIMES_PRODUCES(Not produced on S3 boot path)
gEfiPeiDecompressPpiGuid ## CONSUMES
[Protocols]
gEfiPciEnumerationCompleteProtocolGuid ## PRODUCES
[Guids]
gEfiEventReadyToBootGuid ## PRODUCES ## Event
[FixedPcd]
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES
[Depex]
gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiLoadFilePpiGuid

74
IntelFspPkg/FspSecCore/FspSecCore.inf
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@ -1,74 +0,0 @@
## @file
# Sec Core for FSP
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FspSecCore
FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09
MODULE_TYPE = SEC
VERSION_STRING = 1.0
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32
#
[Sources]
SecMain.c
SecMain.h
SecFsp.c
SecFsp.h
[Sources.IA32]
Ia32/ResetVec.asm16 | MSFT
Ia32/Stack.asm | MSFT
Ia32/InitializeFpu.asm | MSFT
Ia32/FspApiEntry.asm | MSFT
Ia32/FspHelper.asm | MSFT
Ia32/Stacks.s | GCC
Ia32/InitializeFpu.s | GCC
Ia32/FspApiEntry.s | GCC
Ia32/FspHelper.s | GCC
[Binaries.Ia32]
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib
BaseLib
PciCf8Lib
SerialPortLib
FspSwitchStackLib
FspCommonLib
FspSecPlatformLib
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED
gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize ## CONSUMES
[FixedPcd]
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES
[Ppis]
gEfiTemporaryRamSupportPpiGuid ## PRODUCES

595
IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm
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@ -1,595 +0,0 @@
;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
.586p
.model flat,C
.code
.xmm
INCLUDE SaveRestoreSse.inc
INCLUDE MicrocodeLoad.inc
;
; Following are fixed PCDs
;
EXTERN PcdGet32(PcdTemporaryRamBase):DWORD
EXTERN PcdGet32(PcdTemporaryRamSize):DWORD
EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD
EXTERN PcdGet32(PcdFspAreaSize):DWORD
;
; Following functions will be provided in C
;
EXTERN SecStartup:PROC
EXTERN FspApiCallingCheck:PROC
;
; Following functions will be provided in PlatformSecLib
;
EXTERN AsmGetFspBaseAddress:PROC
EXTERN AsmGetFspInfoHeader:PROC
EXTERN GetBootFirmwareVolumeOffset:PROC
EXTERN Loader2PeiSwitchStack:PROC
EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC
EXTERN SecPlatformInit(SecPlatformInitDefault):PROC
EXTERN SecCarInit:PROC
;
; Define the data length that we saved on the stack top
;
DATA_LEN_OF_PER0 EQU 18h
DATA_LEN_OF_MCUD EQU 18h
DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
;
; Define SSE macros
;
LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister
mov esi, ReturnAddress
movd MmxRegister, esi ; save ReturnAddress into MMX
ENDM
CALL_MMX_EXT MACRO RoutineLabel, MmxRegister
local ReturnAddress
mov esi, offset ReturnAddress
movd MmxRegister, esi ; save ReturnAddress into MMX
jmp RoutineLabel
ReturnAddress:
ENDM
RET_ESI_EXT MACRO MmxRegister
movd esi, MmxRegister ; move ReturnAddress from MMX to ESI
jmp esi
ENDM
CALL_MMX MACRO RoutineLabel
CALL_MMX_EXT RoutineLabel, mm7
ENDM
RET_ESI MACRO
RET_ESI_EXT mm7
ENDM
;------------------------------------------------------------------------------
SecPlatformInitDefault PROC NEAR PUBLIC
; Inputs:
; mm7 -> Return address
; Outputs:
; eax -> 0 - Successful, Non-zero - Failed.
; Register Usage:
; eax is cleared and ebp is used for return address.
; All others reserved.
; Save return address to EBP
movd ebp, mm7
xor eax, eax
exit:
jmp ebp
SecPlatformInitDefault ENDP
;------------------------------------------------------------------------------
LoadMicrocodeDefault PROC NEAR PUBLIC
; Inputs:
; esp -> LoadMicrocodeParams pointer
; Register Usage:
; esp Preserved
; All others destroyed
; Assumptions:
; No memory available, stack is hard-coded and used for return address
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
;
;
; Save return address to EBP
movd ebp, mm7
cmp esp, 0
jz paramerror
mov eax, dword ptr [esp + 4] ; Parameter pointer
cmp eax, 0
jz paramerror
mov esp, eax
mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr
cmp esi, 0
jnz check_main_header
paramerror:
mov eax, 080000002h
jmp exit
mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr
check_main_header:
; Get processor signature and platform ID from the installed processor
; and save into registers for later use
; ebx = processor signature
; edx = platform ID
mov eax, 1
cpuid
mov ebx, eax
mov ecx, MSR_IA32_PLATFORM_ID
rdmsr
mov ecx, edx
shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits
and ecx, 7h ; platform id at bit[52..50]
mov edx, 1
shl edx, cl
; Current register usage
; esp -> stack with paramters
; esi -> microcode update to check
; ebx = processor signature
; edx = platform ID
; Check for valid microcode header
; Minimal test checking for header version and loader version as 1
mov eax, dword ptr 1
cmp [esi].MicrocodeHdr.MicrocodeHdrVersion, eax
jne advance_fixed_size
cmp [esi].MicrocodeHdr.MicrocodeHdrLoader, eax
jne advance_fixed_size
; Check if signature and plaform ID match
cmp ebx, [esi].MicrocodeHdr.MicrocodeHdrProcessor
jne @f
test edx, [esi].MicrocodeHdr.MicrocodeHdrFlags
jnz load_check ; Jif signature and platform ID match
@@:
; Check if extended header exists
; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid
xor eax, eax
cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax
je next_microcode
cmp [esi].MicrocodeHdr.MicrocodeHdrDataSize, eax
je next_microcode
; Then verify total size - sizeof header > data size
mov ecx, [esi].MicrocodeHdr.MicrocodeHdrTotalSize
sub ecx, sizeof MicrocodeHdr
cmp ecx, [esi].MicrocodeHdr.MicrocodeHdrDataSize
jng next_microcode ; Jif extended header does not exist
; Set edi -> extended header
mov edi, esi
add edi, sizeof MicrocodeHdr
add edi, [esi].MicrocodeHdr.MicrocodeHdrDataSize
; Get count of extended structures
mov ecx, [edi].ExtSigHdr.ExtSigHdrCount
; Move pointer to first signature structure
add edi, sizeof ExtSigHdr
check_ext_sig:
; Check if extended signature and platform ID match
cmp [edi].ExtSig.ExtSigProcessor, ebx
jne @f
test [edi].ExtSig.ExtSigFlags, edx
jnz load_check ; Jif signature and platform ID match
@@:
; Check if any more extended signatures exist
add edi, sizeof ExtSig
loop check_ext_sig
next_microcode:
; Advance just after end of this microcode
xor eax, eax
cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax
je @f
add esi, [esi].MicrocodeHdr.MicrocodeHdrTotalSize
jmp check_address
@@:
add esi, dword ptr 2048
jmp check_address
advance_fixed_size:
; Advance by 4X dwords
add esi, dword ptr 1024
check_address:
; Is valid Microcode start point ?
cmp dword ptr [esi].MicrocodeHdr.MicrocodeHdrVersion, 0ffffffffh
jz done
; Is automatic size detection ?
mov eax, [esp].LoadMicrocodeParams.MicrocodeCodeSize
cmp eax, 0ffffffffh
jz @f
; Address >= microcode region address + microcode region size?
add eax, [esp].LoadMicrocodeParams.MicrocodeCodeAddr
cmp esi, eax
jae done ;Jif address is outside of microcode region
jmp check_main_header
@@:
load_check:
; Get the revision of the current microcode update loaded
mov ecx, MSR_IA32_BIOS_SIGN_ID
xor eax, eax ; Clear EAX
xor edx, edx ; Clear EDX
wrmsr ; Load 0 to MSR at 8Bh
mov eax, 1
cpuid
mov ecx, MSR_IA32_BIOS_SIGN_ID
rdmsr ; Get current microcode signature
; Verify this microcode update is not already loaded
cmp [esi].MicrocodeHdr.MicrocodeHdrRevision, edx
je continue
load_microcode:
; EAX contains the linear address of the start of the Update Data
; EDX contains zero
; ECX contains 79h (IA32_BIOS_UPDT_TRIG)
; Start microcode load with wrmsr
mov eax, esi
add eax, sizeof MicrocodeHdr
xor edx, edx
mov ecx, MSR_IA32_BIOS_UPDT_TRIG
wrmsr
mov eax, 1
cpuid
continue:
jmp next_microcode
done:
mov eax, 1
cpuid
mov ecx, MSR_IA32_BIOS_SIGN_ID
rdmsr ; Get current microcode signature
xor eax, eax
cmp edx, 0
jnz exit
mov eax, 08000000Eh
exit:
jmp ebp
LoadMicrocodeDefault ENDP
EstablishStackFsp PROC NEAR PRIVATE
;
; Save parameter pointer in edx
;
mov edx, dword ptr [esp + 4]
;
; Enable FSP STACK
;
mov esp, PcdGet32 (PcdTemporaryRamBase)
add esp, PcdGet32 (PcdTemporaryRamSize)
push DATA_LEN_OF_MCUD ; Size of the data region
push 4455434Dh ; Signature of the data region 'MCUD'
push dword ptr [edx + 12] ; Code size
push dword ptr [edx + 8] ; Code base
push dword ptr [edx + 4] ; Microcode size
push dword ptr [edx] ; Microcode base
;
; Save API entry/exit timestamp into stack
;
push DATA_LEN_OF_PER0 ; Size of the data region
push 30524550h ; Signature of the data region 'PER0'
LOAD_EDX
push edx
LOAD_EAX
push eax
rdtsc
push edx
push eax
;
; Terminator for the data on stack
;
push 0
;
; Set ECX/EDX to the BootLoader temporary memory range
;
mov ecx, PcdGet32 (PcdTemporaryRamBase)
mov edx, ecx
add edx, PcdGet32 (PcdTemporaryRamSize)
sub edx, PcdGet32 (PcdFspTemporaryRamSize)
xor eax, eax
RET_ESI
EstablishStackFsp ENDP
;----------------------------------------------------------------------------
; TempRamInit API
;
; This FSP API will load the microcode update, enable code caching for the
; region specified by the boot loader and also setup a temporary stack to be
; used till main memory is initialized.
;
;----------------------------------------------------------------------------
TempRamInitApi PROC NEAR PUBLIC
;
; Ensure SSE is enabled
;
ENABLE_SSE
;
; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
;
SAVE_REGS
;
; Save timestamp into XMM6
;
rdtsc
SAVE_EAX
SAVE_EDX
;
; Check Parameter
;
mov eax, dword ptr [esp + 4]
cmp eax, 0
mov eax, 80000002h
jz TempRamInitExit
;
; Sec Platform Init
;
CALL_MMX SecPlatformInit
cmp eax, 0
jnz TempRamInitExit
; Load microcode
LOAD_ESP
CALL_MMX LoadMicrocode
SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.
;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init
LOAD_ESP
CALL_MMX SecCarInit
cmp eax, 0
jnz TempRamInitExit
LOAD_ESP
CALL_MMX EstablishStackFsp
LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
TempRamInitExit:
;
; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
;
LOAD_REGS
ret
TempRamInitApi ENDP
;----------------------------------------------------------------------------
; FspInit API
;
; This FSP API will perform the processor and chipset initialization.
; This API will not return. Instead, it transfers the control to the
; ContinuationFunc provided in the parameter.
;
;----------------------------------------------------------------------------
FspInitApi PROC NEAR PUBLIC
mov eax, 1
jmp FspApiCommon
FspInitApi ENDP
;----------------------------------------------------------------------------
; NotifyPhase API
;
; This FSP API will notify the FSP about the different phases in the boot
; process
;
;----------------------------------------------------------------------------
NotifyPhaseApi PROC C PUBLIC
mov eax, 2
jmp FspApiCommon
NotifyPhaseApi ENDP
;----------------------------------------------------------------------------
; FspMemoryInit API
;
; This FSP API is called after TempRamInit and initializes the memory.
;
;----------------------------------------------------------------------------
FspMemoryInitApi PROC NEAR PUBLIC
mov eax, 3
jmp FspApiCommon
FspMemoryInitApi ENDP
;----------------------------------------------------------------------------
; TempRamExitApi API
;
; This API tears down temporary RAM
;
;----------------------------------------------------------------------------
TempRamExitApi PROC C PUBLIC
mov eax, 4
jmp FspApiCommon
TempRamExitApi ENDP
;----------------------------------------------------------------------------
; FspSiliconInit API
;
; This FSP API initializes the CPU and the chipset including the IO
; controllers in the chipset to enable normal operation of these devices.
;
;----------------------------------------------------------------------------
FspSiliconInitApi PROC C PUBLIC
mov eax, 5
jmp FspApiCommon
FspSiliconInitApi ENDP
;----------------------------------------------------------------------------
; FspApiCommon API
;
; This is the FSP API common entry point to resume the FSP execution
;
;----------------------------------------------------------------------------
FspApiCommon PROC C PUBLIC
;
; EAX holds the API index
;
;
; Stack must be ready
;
push eax
add esp, 4
cmp eax, dword ptr [esp - 4]
jz @F
mov eax, 080000003h
jmp exit
@@:
;
; Verify the calling condition
;
pushad
push [esp + 4 * 8 + 4] ; push ApiParam
push eax ; push ApiIdx
call FspApiCallingCheck
add esp, 8
cmp eax, 0
jz @F
mov dword ptr [esp + 4 * 7], eax
popad
ret
@@:
popad
cmp eax, 1 ; FspInit API
jz @F
cmp eax, 3 ; FspMemoryInit API
jz @F
call AsmGetFspInfoHeader
jmp Loader2PeiSwitchStack
@@:
;
; FspInit and FspMemoryInit APIs, setup the initial stack frame
;
;
; Place holder to store the FspInfoHeader pointer
;
push eax
;
; Update the FspInfoHeader pointer
;
push eax
call AsmGetFspInfoHeader
mov [esp + 4], eax
pop eax
;
; Create a Task Frame in the stack for the Boot Loader
;
pushfd ; 2 pushf for 4 byte alignment
cli
pushad
; Reserve 8 bytes for IDT save/restore
sub esp, 8
sidt fword ptr [esp]
;
; Setup new FSP stack
;
mov edi, esp
mov esp, PcdGet32(PcdTemporaryRamBase)
add esp, PcdGet32(PcdTemporaryRamSize)
sub esp, (DATA_LEN_AT_STACK_TOP + 40h)
;
; Pass the API Idx to SecStartup
;
push eax
;
; Pass the BootLoader stack to SecStartup
;
push edi
;
; Pass entry point of the PEI core
;
call AsmGetFspBaseAddress
mov edi, eax
add edi, PcdGet32 (PcdFspAreaSize)
sub edi, 20h
add eax, DWORD PTR ds:[edi]
push eax
;
; Pass BFV into the PEI Core
; It uses relative address to calucate the actual boot FV base
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
; they are different. The code below can handle both cases.
;
call AsmGetFspBaseAddress
mov edi, eax
call GetBootFirmwareVolumeOffset
add eax, edi
push eax
;
; Pass stack base and size into the PEI Core
;
mov eax, PcdGet32(PcdTemporaryRamBase)
add eax, PcdGet32(PcdTemporaryRamSize)
sub eax, PcdGet32(PcdFspTemporaryRamSize)
push eax
push PcdGet32(PcdFspTemporaryRamSize)
;
; Pass Control into the PEI Core
;
call SecStartup
add esp, 4
exit:
ret
FspApiCommon ENDP
END

807
IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s
View File

@ -1,807 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# Provide FSP API entry points.
#
#------------------------------------------------------------------------------
.equ MSR_IA32_PLATFORM_ID, 0x00000017
.equ MSR_IA32_BIOS_UPDT_TRIG, 0x00000079
.equ MSR_IA32_BIOS_SIGN_ID, 0x0000008b
MicrocodeHdr:
.equ MicrocodeHdrVersion, 0x0000
.equ MicrocodeHdrRevision, 0x0004
.equ MicrocodeHdrDate, 0x0008
.equ MicrocodeHdrProcessor, 0x000c
.equ MicrocodeHdrChecksum, 0x0010
.equ MicrocodeHdrLoader, 0x0014
.equ MicrocodeHdrFlags, 0x0018
.equ MicrocodeHdrDataSize, 0x001C
.equ MicrocodeHdrTotalSize, 0x0020
.equ MicrocodeHdrRsvd, 0x0024
MicrocodeHdrEnd:
.equ MicrocodeHdrLength, 0x0030 # MicrocodeHdrLength = MicrocodeHdrEnd - MicrocodeHdr
ExtSigHdr:
.equ ExtSigHdrCount, 0x0000
.equ ExtSigHdrChecksum, 0x0004
.equ ExtSigHdrRsvd, 0x0008
ExtSigHdrEnd:
.equ ExtSigHdrLength, 0x0014 #ExtSigHdrLength = ExtSigHdrEnd - ExtSigHdr
ExtSig:
.equ ExtSigProcessor, 0x0000
.equ ExtSigFlags, 0x0004
.equ ExtSigChecksum, 0x0008
ExtSigEnd:
.equ ExtSigLength, 0x000C #ExtSigLength = ExtSigEnd - ExtSig
LoadMicrocodeParams:
.equ MicrocodeCodeAddr, 0x0000
.equ MicrocodeCodeSize, 0x0004
LoadMicrocodeParamsEnd:
.macro SAVE_REGS
pinsrw $0x00, %ebp, %xmm7
ror $0x10, %ebp
pinsrw $0x01, %ebp, %xmm7
ror $0x10, %ebp
#
pinsrw $0x02, %ebx, %xmm7
ror $0x10, %ebx
pinsrw $0x03, %ebx, %xmm7
ror $0x10, %ebx
#
pinsrw $0x04, %esi, %xmm7
ror $0x10, %esi
pinsrw $0x05, %esi, %xmm7
ror $0x10, %esi
#
pinsrw $0x06, %edi, %xmm7
ror $0x10, %edi
pinsrw $0x07, %edi, %xmm7
ror $0x10, %edi
#
pinsrw $0x00, %esp, %xmm6
ror $0x10, %esp
pinsrw $0x01, %esp, %xmm6
ror $0x10, %esp
.endm
.macro LOAD_REGS
pshufd $0xe4, %xmm7, %xmm7
movd %xmm7, %ebp
pshufd $0xe4, %xmm7, %xmm7
#
pshufd $0x39, %xmm7, %xmm7
movd %xmm7, %ebx
pshufd $0x93, %xmm7, %xmm7
#
pshufd $0x4e, %xmm7, %xmm7
movd %xmm7, %esi
pshufd $0x4e, %xmm7, %xmm7
#
pshufd $0x93, %xmm7, %xmm7
movd %xmm7, %edi
pshufd $0x39, %xmm7, %xmm7
#
movd %xmm6, %esp
.endm
.macro LOAD_EAX
pshufd $0x39, %xmm6, %xmm6
movd %xmm6, %eax
pshufd $0x93, %xmm6, %xmm6
.endm
.macro LOAD_EDX
pshufd $0xe4, %xmm6, %xmm6
movd %xmm6, %edx
pshufd $0xe4, %xmm6, %xmm6
.endm
.macro SAVE_EAX
pinsrw $0x02, %eax, %xmm6
ror $0x10, %eax
pinsrw $0x03, %eax, %xmm6
ror $0x10, %eax
.endm
.macro SAVE_EDX
pinsrw $0x04, %edx, %xmm6
ror $0x10, %edx
pinsrw $0x05, %edx, %xmm6
ror $0x10, %edx
.endm
.macro LOAD_ESP
movd %xmm6, %esp
.endm
.macro ENABLE_SSE
jmp NextAddress
.align 4
#
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
ASM_PFX(mMmxControlWord): .long 0x01F80
SseError:
#
# Processor has to support SSE
#
jmp SseError
NextAddress:
#
# Initialize floating point units
#
finit
fldcw ASM_PFX(mFpuControlWord)
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
#
movl $1, %eax
cpuid
btl $25, %edx
jnc SseError
#
# Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
#
movl %cr4, %eax
orl $BIT9, %eax
movl %eax, %cr4
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction
#
ldmxcsr ASM_PFX(mMmxControlWord)
.endm
#Save in ECX-SLOT 3 in xmm6.
.macro SAVE_EAX_MICROCODE_RET_STATUS
pinsrw $0x6, %eax, %xmm6
ror $0x10, %eax
pinsrw $0x7, %eax, %xmm6
rol $0x10, %eax
.endm
#Restore from ECX-SLOT 3 in xmm6.
.macro LOAD_EAX_MICROCODE_RET_STATUS
pshufd $0x93, %xmm6, %xmm6
movd %xmm6, %eax
pshufd $0x39, %xmm6, %xmm6
.endm
#
# Following are fixed PCDs
#
ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase)
ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize)
ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
#
# Following functions will be provided in C
#
ASM_GLOBAL ASM_PFX(SecStartup)
ASM_GLOBAL ASM_PFX(FspApiCallingCheck)
#
# Following functions will be provided in PlatformSecLib
#
ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress)
ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader)
ASM_GLOBAL ASM_PFX(GetBootFirmwareVolumeOffset)
ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack)
#
# Define the data length that we saved on the stack top
#
.equ DATA_LEN_OF_PER0, 0x018
.equ DATA_LEN_OF_MCUD, 0x018
.equ DATA_LEN_AT_STACK_TOP, (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
#------------------------------------------------------------------------------
# SecPlatformInitDefault
# Inputs:
# mm7 -> Return address
# Outputs:
# eax -> 0 - Successful, Non-zero - Failed.
# Register Usage:
# eax is cleared and ebp is used for return address.
# All others reserved.
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SecPlatformInitDefault)
ASM_PFX(SecPlatformInitDefault):
#
# Save return address to EBP
#
movd %mm7, %ebp
xorl %eax, %eax
SecPlatformInitDefaultExit:
jmp *%ebp
#------------------------------------------------------------------------------
# LoadMicrocodeDefault
#
# Inputs:
# esp -> LoadMicrocodeParams pointer
# Register Usage:
# esp Preserved
# All others destroyed
# Assumptions:
# No memory available, stack is hard-coded and used for return address
# Executed by SBSP and NBSP
# Beginning of microcode update region starts on paragraph boundary
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(LoadMicrocodeDefault)
ASM_PFX(LoadMicrocodeDefault):
#
# Save return address to EBP
#
movd %mm7, %ebp
cmpl $0x00, %esp
jz ParamError
movl 4(%esp), %eax #dword ptr [] Parameter pointer
cmpl $0x00, %eax
jz ParamError
movl %eax, %esp
movl MicrocodeCodeAddr(%esp), %esi
cmpl $0x00, %esi
jnz CheckMainHeader
ParamError:
movl $0x080000002, %eax
jmp LoadMicrocodeExit
CheckMainHeader:
#
# Get processor signature and platform ID from the installed processor
# and save into registers for later use
# ebx = processor signature
# edx = platform ID
#
movl $0x01, %eax
cpuid
movl %eax, %ebx
movl $MSR_IA32_PLATFORM_ID, %ecx
rdmsr
movl %edx, %ecx
shrl $0x12, %ecx # shift (50d-32d=18d=0x12) bits
andl $0x07, %ecx # platform id at bit[52..50]
movl $0x01, %edx
shll %cl,%edx
#
# Current register usage
# esp -> stack with paramters
# esi -> microcode update to check
# ebx = processor signature
# edx = platform ID
#
#
# Check for valid microcode header
# Minimal test checking for header version and loader version as 1
#
movl $0x01, %eax
cmpl %eax, MicrocodeHdrVersion(%esi)
jne AdvanceFixedSize
cmpl %eax, MicrocodeHdrLoader(%esi)
jne AdvanceFixedSize
#
# Check if signature and plaform ID match
#
cmpl MicrocodeHdrProcessor(%esi), %ebx
jne LoadMicrocodeL0
testl MicrocodeHdrFlags(%esi), %edx
jnz LoadCheck #Jif signature and platform ID match
LoadMicrocodeL0:
#
# Check if extended header exists
# First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid
#
xorl %eax, %eax
cmpl %eax, MicrocodeHdrTotalSize(%esi)
je NextMicrocode
cmpl %eax, MicrocodeHdrDataSize(%esi)
je NextMicrocode
#
# Then verify total size - sizeof header > data size
#
movl MicrocodeHdrTotalSize(%esi), %ecx
subl $MicrocodeHdrLength, %ecx
cmpl MicrocodeHdrDataSize(%esi), %ecx
jle NextMicrocode
#
# Set edi -> extended header
#
movl %esi, %edi
addl $MicrocodeHdrLength, %edi
addl MicrocodeHdrDataSize(%esi), %edi
#
# Get count of extended structures
#
movl ExtSigHdrCount(%edi), %ecx
#
# Move pointer to first signature structure
#
addl ExtSigHdrLength, %edi
CheckExtSig:
#
# Check if extended signature and platform ID match
#
cmpl %ebx, ExtSigProcessor(%edi)
jne LoadMicrocodeL1
test %edx, ExtSigFlags(%edi)
jnz LoadCheck # Jif signature and platform ID match
LoadMicrocodeL1:
#
# Check if any more extended signatures exist
#
addl $ExtSigLength, %edi
loop CheckExtSig
NextMicrocode:
#
# Advance just after end of this microcode
#
xorl %eax, %eax
cmpl %eax, MicrocodeHdrTotalSize(%esi)
je LoadMicrocodeL2
addl MicrocodeHdrTotalSize(%esi), %esi
jmp CheckAddress
LoadMicrocodeL2:
addl $0x800, %esi #add esi, dword ptr 2048
jmp CheckAddress
AdvanceFixedSize:
#
# Advance by 4X dwords
#
addl $0x400, %esi #add esi, dword ptr 1024
CheckAddress:
#
# Is valid Microcode start point ?
#
cmpl $0x0ffffffff, MicrocodeHdrVersion(%esi)
#
# Is automatic size detection ?
#
movl MicrocodeCodeSize(%esp), %eax
cmpl $0x0ffffffff, %eax
jz LoadMicrocodeL3
#
# Address >= microcode region address + microcode region size?
#
addl MicrocodeCodeAddr(%esp), %eax
cmpl %eax, %esi
jae Done #Jif address is outside of microcode region
jmp CheckMainHeader
LoadMicrocodeL3:
LoadCheck:
#
# Get the revision of the current microcode update loaded
#
movl $MSR_IA32_BIOS_SIGN_ID, %ecx
xorl %eax, %eax # Clear EAX
xorl %edx, %edx # Clear EDX
wrmsr # Load 0 to MSR at 8Bh
movl $0x01, %eax
cpuid
movl $MSR_IA32_BIOS_SIGN_ID, %ecx
rdmsr # Get current microcode signature
#
# Verify this microcode update is not already loaded
#
cmpl %edx, MicrocodeHdrRevision(%esi)
je Continue
LoadMicrocode0:
#
# EAX contains the linear address of the start of the Update Data
# EDX contains zero
# ECX contains 79h (IA32_BIOS_UPDT_TRIG)
# Start microcode load with wrmsr
#
movl %esi, %eax
addl $MicrocodeHdrLength, %eax
xorl %edx, %edx
movl $MSR_IA32_BIOS_UPDT_TRIG, %ecx
wrmsr
movl $0x01, %eax
cpuid
Continue:
jmp NextMicrocode
Done:
movl $0x01, %eax
cpuid
movl $MSR_IA32_BIOS_SIGN_ID, %ecx
rdmsr # Get current microcode signature
xorl %eax, %eax
cmpl $0x00, %edx
jnz LoadMicrocodeExit
movl $0x08000000E, %eax
LoadMicrocodeExit:
jmp *%ebp
#----------------------------------------------------------------------------
# EstablishStackFsp
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(EstablishStackFsp)
ASM_PFX(EstablishStackFsp):
#
# Save parameter pointer in edx
#
movl 4(%esp), %edx
#
# Enable FSP STACK
#
movl PcdGet32(PcdTemporaryRamBase), %esp
addl PcdGet32(PcdTemporaryRamSize), %esp
pushl $DATA_LEN_OF_MCUD # Size of the data region
pushl $0x4455434D # Signature of the data region 'MCUD'
pushl 12(%edx) # Code size
pushl 8(%edx) # Code base
pushl 4(%edx) # Microcode size
pushl (%edx) # Microcode base
#
# Save API entry/exit timestamp into stack
#
pushl $DATA_LEN_OF_PER0 # Size of the data region
pushl $0x30524550 # Signature of the data region 'PER0'
LOAD_EDX
pushl %edx
LOAD_EAX
pushl %eax
rdtsc
pushl %edx
pushl %eax
#
# Terminator for the data on stack
#
push $0x00
#
# Set ECX/EDX to the BootLoader temporary memory range
#
movl PcdGet32 (PcdTemporaryRamBase), %ecx
movl %ecx, %edx
addl PcdGet32 (PcdTemporaryRamSize), %edx
subl PcdGet32 (PcdFspTemporaryRamSize), %edx
xorl %eax, %eax
movd %mm7, %esi #RET_ESI
jmp *%esi
#----------------------------------------------------------------------------
# TempRamInit API
#
# This FSP API will load the microcode update, enable code caching for the
# region specified by the boot loader and also setup a temporary stack to be
# used till main memory is initialized.
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(TempRamInitApi)
ASM_PFX(TempRamInitApi):
#
# Ensure SSE is enabled
#
ENABLE_SSE
#
# Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
#
SAVE_REGS
#
# Save timestamp into XMM6
#
rdtsc
SAVE_EAX
SAVE_EDX
#
# Check Parameter
#
movl 4(%esp), %eax
cmpl $0x00, %eax
movl $0x80000002, %eax
jz NemInitExit
#
# Sec Platform Init
#
movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit
movd %esi, %mm7
.weak ASM_PFX(SecPlatformInit)
.set ASM_PFX(SecPlatformInit), ASM_PFX(SecPlatformInitDefault)
jmp ASM_PFX(SecPlatformInit)
TempRamInitApiL1:
cmpl $0x00, %eax
jnz NemInitExit
#
# Load microcode
#
LOAD_ESP
movl $TempRamInitApiL2, %esi #CALL_MMX LoadMicrocode
movd %esi, %mm7
.weak ASM_PFX(LoadMicrocode)
.set ASM_PFX(LoadMicrocode), ASM_PFX(LoadMicrocodeDefault)
jmp ASM_PFX(LoadMicrocode)
TempRamInitApiL2:
SAVE_EAX_MICROCODE_RET_STATUS #Save microcode return status in ECX-SLOT 3 in xmm6.
#@note If return value eax is not 0, microcode did not load, but continue and attempt to boot from ECX-SLOT 3 in xmm6.
#
# Call Sec CAR Init
#
LOAD_ESP
movl $TempRamInitApiL3, %esi #CALL_MMX SecCarInit
movd %esi, %mm7
jmp ASM_PFX(SecCarInit)
TempRamInitApiL3:
cmpl $0x00, %eax
jnz NemInitExit
#
# EstablishStackFsp
#
LOAD_ESP
movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp
movd %esi, %mm7
jmp ASM_PFX(EstablishStackFsp)
TempRamInitApiL4:
LOAD_EAX_MICROCODE_RET_STATUS #Restore microcode status if no CAR init error.
NemInitExit:
#
# Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
#
LOAD_REGS
ret
#----------------------------------------------------------------------------
# FspInit API
#
# This FSP API will perform the processor and chipset initialization.
# This API will not return. Instead, it transfers the control to the
# ContinuationFunc provided in the parameter.
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspInitApi)
ASM_PFX(FspInitApi):
movl $0x01, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# NotifyPhase API
#
# This FSP API will notify the FSP about the different phases in the boot
# process
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(NotifyPhaseApi)
ASM_PFX(NotifyPhaseApi):
movl $0x02, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# FspMemoryInit API
#
# This FSP API is called after TempRamInit and initializes the memory.
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspMemoryInitApi)
ASM_PFX(FspMemoryInitApi):
movl $0x03, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# TempRamExitApi API
#
# This API tears down temporary RAM
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(TempRamExitApi)
ASM_PFX(TempRamExitApi):
movl $0x04, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# FspSiliconInit API
#
# This FSP API initializes the CPU and the chipset including the IO
# controllers in the chipset to enable normal operation of these devices.
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspSiliconInitApi)
ASM_PFX(FspSiliconInitApi):
movl $0x05, %eax
jmp FspApiCommon
#----------------------------------------------------------------------------
# FspApiCommon API
#
# This is the FSP API common entry point to resume the FSP execution
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspApiCommon)
ASM_PFX(FspApiCommon):
#
# EAX holds the API index
#
#
# Stack must be ready
#
pushl %eax
addl $0x04, %esp
cmpl -4(%esp), %eax
jz FspApiCommonL0
movl $0x080000003, %eax
jmp FspApiCommonExit
FspApiCommonL0:
#
# Verify the calling condition
#
pushal
pushl 36(%esp) #push ApiParam [esp + 4 * 8 + 4]
pushl %eax #push ApiIdx
call ASM_PFX(FspApiCallingCheck)
addl $0x08, %esp
cmpl $0x00, %eax
jz FspApiCommonL1
movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax
popal
ret
FspApiCommonL1:
popal
cmpl $0x01, %eax # FspInit API
jz FspApiCommonL2
cmpl $0x03, %eax # FspMemoryInit API
jz FspApiCommonL2
call ASM_PFX(AsmGetFspInfoHeader)
jmp Loader2PeiSwitchStack
FspApiCommonL2:
#
# FspInit and FspMemoryInit APIs, setup the initial stack frame
#
#
# Place holder to store the FspInfoHeader pointer
#
pushl %eax
#
# Update the FspInfoHeader pointer
#
pushl %eax
call ASM_PFX(AsmGetFspInfoHeader)
movl %eax, 4(%esp)
popl %eax
#
# Create a Task Frame in the stack for the Boot Loader
#
pushfl # 2 pushf for 4 byte alignment
cli
pushal
#
# Reserve 8 bytes for IDT save/restore
#
subl $0x08, %esp
sidt (%esp)
#
# Setup new FSP stack
#
movl %esp, %edi
movl PcdGet32(PcdTemporaryRamBase), %esp
addl PcdGet32(PcdTemporaryRamSize), %esp
subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp
#
# Pass the API Idx to SecStartup
#
pushl %eax
#
# Pass the BootLoader stack to SecStartup
#
pushl %edi
#
# Pass entry point of the PEI core
#
call ASM_PFX(AsmGetFspBaseAddress)
movl %eax, %edi
addl PcdGet32(PcdFspAreaSize), %edi
subl $0x20, %edi
addl %ds:(%edi), %eax
pushl %eax
#
# Pass BFV into the PEI Core
# It uses relative address to calucate the actual boot FV base
# For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
# PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
# they are different. The code below can handle both cases.
#
call ASM_PFX(AsmGetFspBaseAddress)
movl %eax, %edi
call ASM_PFX(GetBootFirmwareVolumeOffset)
addl %edi, %eax
pushl %eax
#
# Pass stack base and size into the PEI Core
#
movl PcdGet32(PcdTemporaryRamBase), %eax
addl PcdGet32(PcdTemporaryRamSize), %eax
subl PcdGet32(PcdFspTemporaryRamSize), %eax
pushl %eax
pushl PcdGet32(PcdFspTemporaryRamSize)
#
# Pass Control into the PEI Core
#
call ASM_PFX(SecStartup)
addl $4, %esp
FspApiCommonExit:
ret

67
IntelFspPkg/FspSecCore/Ia32/FspHelper.asm
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@ -1,67 +0,0 @@
;; @file
; Provide FSP helper function.
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
.586p
.model flat,C
.code
;
; FspInfoHeaderRelativeOff is patched during build process and initialized to offset of the AsmGetFspBaseAddress
; from the FSP Info header.
;
FspInfoHeaderRelativeOff PROC NEAR PUBLIC
;
; This value will be pached by the build script
;
DD 012345678h
FspInfoHeaderRelativeOff ENDP
;
; Returns FSP Base Address.
;
; This function gets the FSP Info Header using relative addressing and returns the FSP Base from the header structure
;
AsmGetFspBaseAddress PROC NEAR PUBLIC
mov eax, AsmGetFspBaseAddress
sub eax, dword ptr [FspInfoHeaderRelativeOff]
add eax, 01Ch
mov eax, dword ptr [eax]
ret
AsmGetFspBaseAddress ENDP
;
; No stack counter part of AsmGetFspBaseAddress. Return address is in edi.
;
AsmGetFspBaseAddressNoStack PROC NEAR PUBLIC
mov eax, AsmGetFspBaseAddress
sub eax, dword ptr [FspInfoHeaderRelativeOff]
add eax, 01Ch
mov eax, dword ptr [eax]
jmp edi
AsmGetFspBaseAddressNoStack ENDP
;
; Returns FSP Info Header.
;
; This function gets the FSP Info Header using relative addressing and returns it
;
AsmGetFspInfoHeader PROC NEAR PUBLIC
mov eax, AsmGetFspBaseAddress
sub eax, dword ptr [FspInfoHeaderRelativeOff]
ret
AsmGetFspInfoHeader ENDP
;
; No stack counter part of AsmGetFspInfoHeader. Return address is in edi.
;
AsmGetFspInfoHeaderNoStack PROC NEAR PUBLIC
mov eax, AsmGetFspBaseAddress
sub eax, dword ptr [FspInfoHeaderRelativeOff]
jmp edi
AsmGetFspInfoHeaderNoStack ENDP
END

65
IntelFspPkg/FspSecCore/Ia32/FspHelper.s
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@ -1,65 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# Provide FSP helper function.
#
#------------------------------------------------------------------------------
#
# FspInfoHeaderRelativeOff is patched during build process and initialized to offset of the AsmGetFspBaseAddress
# from the FSP Info header.
#
ASM_GLOBAL ASM_PFX(FspInfoHeaderRelativeOff)
ASM_PFX(FspInfoHeaderRelativeOff):
#
# This value will be pached by the build script
#
.long 0x012345678
#
# Returns FSP Base Address.
#
# This function gets the FSP Info Header using relative addressing and returns the FSP Base from the header structure
#
ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress)
ASM_PFX(AsmGetFspBaseAddress):
mov $AsmGetFspBaseAddress, %eax
sub FspInfoHeaderRelativeOff, %eax
add $0x01C, %eax
mov (%eax), %eax
ret
#
# No stack counter part of AsmGetFspBaseAddress. Return address is in edi.
#
ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddressNoStack)
ASM_PFX(AsmGetFspBaseAddressNoStack):
mov $AsmGetFspBaseAddress, %eax
sub FspInfoHeaderRelativeOff, %eax
add $0x01C, %eax
mov (%eax), %eax
jmp *%edi
#
# Returns FSP Info Header.
#
# This function gets the FSP Info Header using relative addressing and returns it
#
ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader)
ASM_PFX(AsmGetFspInfoHeader):
mov $AsmGetFspBaseAddress, %eax
sub FspInfoHeaderRelativeOff, %eax
ret
#
# No stack counter part of AsmGetFspInfoHeader. Return address is in edi.
#
ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeaderNoStack)
ASM_PFX(AsmGetFspInfoHeaderNoStack):
mov $AsmGetFspBaseAddress, %eax
sub FspInfoHeaderRelativeOff, %eax
jmp *%edi

73
IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm
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@ -1,73 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
;------------------------------------------------------------------------------
.686
.model flat,C
.const
;
; Float control word initial value:
; all exceptions masked, double-precision, round-to-nearest
;
mFpuControlWord DW 027Fh
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
mMmxControlWord DD 01F80h
.xmm
.code
;
; Initializes floating point units for requirement of UEFI specification.
;
; This function initializes floating-point control word to 0x027F (all exceptions
; masked,double-precision, round-to-nearest) and multimedia-extensions control word
; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
; for masked underflow).
;
InitializeFloatingPointUnits PROC PUBLIC
push ebx
;
; Initialize floating point units
;
finit
fldcw mFpuControlWord
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
cpuid
bt edx, 25
jnc Done
;
; Set OSFXSR bit 9 in CR4
;
mov eax, cr4
or eax, BIT9
mov cr4, eax
;
; The processor should support SSE instruction and we can use
; ldmxcsr instruction
;
ldmxcsr mMmxControlWord
Done:
pop ebx
ret
InitializeFloatingPointUnits ENDP
END

67
IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s
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@ -1,67 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
#------------------------------------------------------------------------------
#
# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
#
# Multimedia-extensions control word:
# all exceptions masked, round-to-nearest, flush to zero for masked underflow
#
ASM_PFX(mMmxControlWord): .long 0x01F80
#
# Initializes floating point units for requirement of UEFI specification.
#
# This function initializes floating-point control word to 0x027F (all exceptions
# masked,double-precision, round-to-nearest) and multimedia-extensions control word
# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
# for masked underflow).
#
ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
pushl %ebx
#
# Initialize floating point units
#
finit
fldcw ASM_PFX(mFpuControlWord)
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
#
movl $1, %eax
cpuid
btl $25, %edx
jnc Done
#
# Set OSFXSR bit 9 in CR4
#
movl %cr4, %eax
orl $BIT9, %eax
movl %eax, %cr4
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction
#
ldmxcsr ASM_PFX(mMmxControlWord)
Done:
popl %ebx
ret

43
IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc
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@ -1,43 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
;------------------------------------------------------------------------------
MSR_IA32_PLATFORM_ID EQU 000000017h
MSR_IA32_BIOS_UPDT_TRIG EQU 000000079h
MSR_IA32_BIOS_SIGN_ID EQU 00000008bh
MicrocodeHdr STRUCT 1t
MicrocodeHdrVersion DWORD ?
MicrocodeHdrRevision DWORD ?
MicrocodeHdrDate DWORD ?
MicrocodeHdrProcessor DWORD ?
MicrocodeHdrChecksum DWORD ?
MicrocodeHdrLoader DWORD ?
MicrocodeHdrFlags DWORD ?
MicrocodeHdrDataSize DWORD ?
MicrocodeHdrTotalSize DWORD ?
MicrocodeHdrRsvd DWORD 3t DUP (?)
MicrocodeHdr ENDS
ExtSigHdr STRUCT 1t
ExtSigHdrCount DWORD ?
ExtSigHdrChecksum DWORD ?
ExtSigHdrRsvd DWORD 3t DUP (?)
ExtSigHdr ENDS
ExtSig STRUCT 1t
ExtSigProcessor DWORD ?
ExtSigFlags DWORD ?
ExtSigChecksum DWORD ?
ExtSig ENDS
LoadMicrocodeParams STRUCT 1t
MicrocodeCodeAddr DWORD ?
MicrocodeCodeSize DWORD ?
LoadMicrocodeParams ENDS

97
IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16
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@ -1,97 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
;------------------------------------------------------------------------------
.model tiny
.686p
.stack 0h
.code
;
; The layout of this file is fixed. The build tool makes assumption of the layout.
;
ORG 0h
;
; Reserved
;
ReservedData DD 0eeeeeeeeh, 0eeeeeeeeh
ORG 10h
;
; This is located at 0xFFFFFFD0h
;
mov di, "AP"
jmp ApStartup
ORG 20h
;
; Pointer to the entry point of the PEI core
; It is located at 0xFFFFFFE0, and is fixed up by some build tool
; So if the value 8..1 appears in the final FD image, tool failure occurs.
;
PeiCoreEntryPoint DD 12345678h
;
; This is the handler for all kinds of exceptions. Since it's for debugging
; purpose only, nothing except a deadloop would be done here. Developers could
; analyze the cause of the exception if a debugger had been attached.
;
InterruptHandler PROC
jmp $
iret
InterruptHandler ENDP
ORG 30h
;
; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte
; Execution starts here upon power-on/platform-reset.
;
ResetHandler:
nop
nop
ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
; SEC entry point relatvie address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm
;
DB 0e9h
DW -3
ORG 38h
;
; Ap reset vector segment address is at 0xFFFFFFF8
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs
;
ApSegAddress dd 12345678h
ORG 3ch
;
; BFV Base is at 0xFFFFFFFC
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs.
;
BfvBase DD 12345678h
;
; Nothing can go here, otherwise the layout of this file would change.
;
END

178
IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc
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@ -1,178 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Provide macro for register save/restore using SSE registers
;
;------------------------------------------------------------------------------
;
; Define SSE instruction set
;
IFDEF USE_SSE41_FLAG
;
; Define SSE macros using SSE 4.1 instructions
;
SXMMN MACRO XMM, IDX, REG
pinsrd XMM, REG, (IDX AND 3)
ENDM
LXMMN MACRO XMM, REG, IDX
pextrd REG, XMM, (IDX AND 3)
ENDM
ELSE
;
; Define SSE macros using SSE 2 instructions
;
SXMMN MACRO XMM, IDX, REG
pinsrw XMM, REG, (IDX AND 3) * 2
ror REG, 16
pinsrw XMM, REG, (IDX AND 3) * 2 + 1
rol REG, 16
ENDM
LXMMN MACRO XMM, REG, IDX
pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2)) AND 0FFh
movd REG, XMM
pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh
ENDM
ENDIF
;
; XMM7 to save/restore EBP, EBX, ESI, EDI
;
SAVE_REGS MACRO
SXMMN xmm7, 0, ebp
SXMMN xmm7, 1, ebx
SXMMN xmm7, 2, esi
SXMMN xmm7, 3, edi
SAVE_ESP
ENDM
LOAD_REGS MACRO
LXMMN xmm7, ebp, 0
LXMMN xmm7, ebx, 1
LXMMN xmm7, esi, 2
LXMMN xmm7, edi, 3
LOAD_ESP
ENDM
;
; XMM6 to save/restore EAX, EDX, ECX, ESP
;
LOAD_EAX MACRO
LXMMN xmm6, eax, 1
ENDM
SAVE_EAX MACRO
SXMMN xmm6, 1, eax
ENDM
LOAD_EDX MACRO
LXMMN xmm6, edx, 2
ENDM
SAVE_EDX MACRO
SXMMN xmm6, 2, edx
ENDM
SAVE_ECX MACRO
SXMMN xmm6, 3, ecx
ENDM
LOAD_ECX MACRO
LXMMN xmm6, ecx, 3
ENDM
SAVE_ESP MACRO
SXMMN xmm6, 0, esp
ENDM
LOAD_ESP MACRO
movd esp, xmm6
ENDM
;
; XMM5 for calling stack
;
CALL_XMM MACRO Entry
local ReturnAddress
mov esi, offset ReturnAddress
pslldq xmm5, 4
IFDEF USE_SSE41_FLAG
pinsrd xmm5, esi, 0
ELSE
pinsrw xmm5, esi, 0
ror esi, 16
pinsrw xmm5, esi, 1
ENDIF
mov esi, Entry
jmp esi
ReturnAddress:
ENDM
RET_XMM MACRO
movd esi, xmm5
psrldq xmm5, 4
jmp esi
ENDM
ENABLE_SSE MACRO
;
; Initialize floating point units
;
local NextAddress
jmp NextAddress
ALIGN 4
;
; Float control word initial value:
; all exceptions masked, double-precision, round-to-nearest
;
FpuControlWord DW 027Fh
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
MmxControlWord DD 01F80h
SseError:
;
; Processor has to support SSE
;
jmp SseError
NextAddress:
finit
fldcw FpuControlWord
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
cpuid
bt edx, 25
jnc SseError
IFDEF USE_SSE41_FLAG
;
; SSE 4.1 support
;
bt ecx, 19
jnc SseError
ENDIF
;
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
;
mov eax, cr4
or eax, 00000600h
mov cr4, eax
;
; The processor should support SSE instruction and we can use
; ldmxcsr instruction
;
ldmxcsr MmxControlWord
ENDM

76
IntelFspPkg/FspSecCore/Ia32/Stack.asm
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@ -1,76 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Switch the stack from temporary memory to permenent memory.
;
;------------------------------------------------------------------------------
.586p
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; SecSwitchStack (
; UINT32 TemporaryMemoryBase,
; UINT32 PermenentMemoryBase
; );
;------------------------------------------------------------------------------
SecSwitchStack PROC
;
; Save three register: eax, ebx, ecx
;
push eax
push ebx
push ecx
push edx
;
; !!CAUTION!! this function address's is pushed into stack after
; migration of whole temporary memory, so need save it to permenent
; memory at first!
;
mov ebx, [esp + 20] ; Save the first parameter
mov ecx, [esp + 24] ; Save the second parameter
;
; Save this function's return address into permenent memory at first.
; Then, Fixup the esp point to permenent memory
;
mov eax, esp
sub eax, ebx
add eax, ecx
mov edx, dword ptr [esp] ; copy pushed register's value to permenent memory
mov dword ptr [eax], edx
mov edx, dword ptr [esp + 4]
mov dword ptr [eax + 4], edx
mov edx, dword ptr [esp + 8]
mov dword ptr [eax + 8], edx
mov edx, dword ptr [esp + 12]
mov dword ptr [eax + 12], edx
mov edx, dword ptr [esp + 16] ; Update this function's return address into permenent memory
mov dword ptr [eax + 16], edx
mov esp, eax ; From now, esp is pointed to permenent memory
;
; Fixup the ebp point to permenent memory
;
mov eax, ebp
sub eax, ebx
add eax, ecx
mov ebp, eax ; From now, ebp is pointed to permenent memory
pop edx
pop ecx
pop ebx
pop eax
ret
SecSwitchStack ENDP
END

80
IntelFspPkg/FspSecCore/Ia32/Stacks.s
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@ -1,80 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# Switch the stack from temporary memory to permenent memory.
#
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SecSwitchStack)
#------------------------------------------------------------------------------
# VOID
# EFIAPI
# SecSwitchStack (
# UINT32 TemporaryMemoryBase,
# UINT32 PermenentMemoryBase
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
#
# Save four registers: eax, ebx, ecx, edx
#
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
#
# !!CAUTION!! this function address's is pushed into stack after
# migration of whole temporary memory, so need save it to permenent
# memory at first!
#
movl 20(%esp), %ebx # Save the first parameter
movl 24(%esp), %ecx # Save the second parameter
#
# Save this function's return address into permenent memory at first.
# Then, Fixup the esp point to permenent memory
#
movl %esp, %eax
subl %ebx, %eax
addl %ecx, %eax
movl (%esp), %edx # copy pushed register's value to permenent memory
movl %edx, (%eax)
movl 4(%esp), %edx
movl %edx, 4(%eax)
movl 8(%esp), %edx
movl %edx, 8(%eax)
movl 12(%esp), %edx
movl %edx, 12(%eax)
movl 16(%esp), %edx # Update this function's return address into permenent memory
movl %edx, 16(%eax)
movl %eax, %esp # From now, esp is pointed to permenent memory
#
# Fixup the ebp point to permenent memory
#
movl %ebp, %eax
subl %ebx, %eax
addl %ecx, %eax
movl %eax, %ebp # From now, ebp is pointed to permenent memory
#
# Fixup callee's ebp point for PeiDispatch
#
# movl %ebp, %eax
# subl %ebx, %eax
# addl %ecx, %eax
# movl %eax, %ebp # From now, ebp is pointed to permenent memory
popl %edx
popl %ecx
popl %ebx
popl %eax
ret

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/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SecFsp.h"
/**
Calculate the FSP IDT gate descriptor.
@param[in] IdtEntryTemplate IDT gate descriptor template.
@return FSP specific IDT gate descriptor.
**/
UINT64
FspGetExceptionHandler(
IN UINT64 IdtEntryTemplate
)
{
UINT32 Entry;
UINT64 ExceptionHandler;
IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;
FSP_INFO_HEADER *FspInfoHeader;
FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader();
ExceptionHandler = IdtEntryTemplate;
IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler;
Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;
Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);
IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16);
IdtGateDescriptor->Bits.OffsetLow = (UINT16)Entry;
return ExceptionHandler;
}
/**
This function gets the FSP UPD region offset in flash.
@return the offset of the UPD region.
**/
UINT32
EFIAPI
GetFspUpdRegionOffset (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
UINT32 *Offset;
FspData = GetFspGlobalDataPointer ();
//
// It is required to put PcdUpdRegionOffset at offset 0x000C
// for all FSPs.
// gPlatformFspPkgTokenSpaceGuid.PcdUpdRegionOffset | 0x000C | 0x12345678
//
Offset = (UINT32 *)(FspData->FspInfoHeader->ImageBase + \
FspData->FspInfoHeader->CfgRegionOffset + 0x0C);
return *Offset;
}
/**
This interface fills platform specific data.
@param[in,out] FspData Pointer to the FSP global data.
**/
VOID
EFIAPI
SecGetPlatformData (
IN OUT FSP_GLOBAL_DATA *FspData
)
{
FSP_PLAT_DATA *FspPlatformData;
UINT32 TopOfCar;
UINT32 *StackPtr;
UINT32 DwordSize;
FspPlatformData = &FspData->PlatformData;
//
// The entries of platform information, together with the number of them,
// reside in the bottom of stack, left untouched by normal stack operation.
//
TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);
FspPlatformData->DataPtr = NULL;
FspPlatformData->MicrocodeRegionBase = 0;
FspPlatformData->MicrocodeRegionSize = 0;
FspPlatformData->CodeRegionBase = 0;
FspPlatformData->CodeRegionSize = 0;
//
// Pointer to the size field
//
StackPtr = (UINT32 *)(TopOfCar - sizeof(UINT32));
while (*StackPtr != 0) {
if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) {
//
// This following data was pushed onto stack after TempRamInit API
//
DwordSize = 4;
StackPtr = StackPtr - 1 - DwordSize;
CopyMem (&(FspPlatformData->MicrocodeRegionBase), StackPtr, (DwordSize << 2));
StackPtr--;
} else if (*(StackPtr - 1) == FSP_PER0_SIGNATURE) {
//
// This is the performance data for InitTempMemory API entry/exit
//
DwordSize = 4;
StackPtr = StackPtr - 1 - DwordSize;
CopyMem (FspData->PerfData, StackPtr, (DwordSize << 2));
((UINT8 *)(&FspData->PerfData[0]))[7] = FSP_PERF_ID_API_TMPRAMINIT_ENTRY;
((UINT8 *)(&FspData->PerfData[1]))[7] = FSP_PERF_ID_API_TMPRAMINIT_EXIT;
StackPtr--;
} else {
StackPtr -= (*StackPtr);
}
}
}
/**
Initialize the FSP global data region.
It needs to be done as soon as possible after the stack is setup.
@param[in,out] PeiFspData Pointer of the FSP global data.
@param[in] BootLoaderStack BootLoader stack.
@param[in] ApiIdx The index of the FSP API.
**/
VOID
FspGlobalDataInit (
IN OUT FSP_GLOBAL_DATA *PeiFspData,
IN UINT32 BootLoaderStack,
IN UINT8 ApiIdx
)
{
VOID *UpdDataRgnPtr;
FSP_INIT_PARAMS *FspInitParams;
CHAR8 ImageId[9];
UINTN Idx;
//
// Init PCIE_BAR with value and set global FSP data pointer.
// PciExpress Base should have been programmed by platform already.
//
SetFspGlobalDataPointer (PeiFspData);
ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_ENTRY);
//
// Get FSP Header offset
// It may have multiple FVs, so look into the last one for FSP header
//
PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader();
SecGetPlatformData (PeiFspData);
//
// Set API calling mode
//
SetFspApiCallingMode (ApiIdx == 1 ? 0 : 1);
//
// Initialize UPD pointer.
//
FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();
UpdDataRgnPtr = ((FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr)->UpdDataRgnPtr;
if (UpdDataRgnPtr == NULL) {
UpdDataRgnPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + GetFspUpdRegionOffset());
}
SetFspUpdDataPointer (UpdDataRgnPtr);
//
// Initialize serial port
// It might have been done in ProcessLibraryConstructorList(), however,
// the FSP global data is not initialized at that time. So do it again
// for safe.
//
SerialPortInitialize ();
//
// Ensure the golbal data pointer is valid
//
ASSERT (GetFspGlobalDataPointer () == PeiFspData);
for (Idx = 0; Idx < 8; Idx++) {
ImageId[Idx] = PeiFspData->FspInfoHeader->ImageId[Idx];
}
ImageId[Idx] = 0;
DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= PEIM FSP v1.%x (%a v%x.%x.%x.%x) =============\n", \
PeiFspData->FspInfoHeader->HeaderRevision - 1, \
ImageId, \
(PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xff, \
(PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xff, \
(PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xff, \
(PeiFspData->FspInfoHeader->ImageRevision >> 0) & 0xff));
}
/**
Adjust the FSP data pointers after the stack is migrated to memory.
@param[in] OffsetGap The offset gap between the old stack and the new stack.
**/
VOID
FspDataPointerFixUp (
IN UINT32 OffsetGap
)
{
FSP_GLOBAL_DATA *NewFspData;
NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer() + (UINTN)OffsetGap);
SetFspGlobalDataPointer (NewFspData);
}
/**
This function check the FSP API calling condition.
@param[in] ApiIdx Internal index of the FSP API.
@param[in] ApiParam Parameter of the FSP API.
**/
EFI_STATUS
EFIAPI
FspApiCallingCheck (
IN UINT32 ApiIdx,
IN VOID *ApiParam
)
{
EFI_STATUS Status;
FSP_GLOBAL_DATA *FspData;
FSP_INIT_PARAMS *FspInitParams;
FSP_INIT_RT_COMMON_BUFFER *FspRtBuffer;
FspInitParams = (FSP_INIT_PARAMS *) ApiParam;
FspRtBuffer = ((FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr);
Status = EFI_SUCCESS;
FspData = GetFspGlobalDataPointer ();
if (ApiIdx == 1) {
//
// FspInit check
//
if ((UINT32)FspData != 0xFFFFFFFF) {
Status = EFI_UNSUPPORTED;
} else if ((FspRtBuffer == NULL) || ((FspRtBuffer->BootLoaderTolumSize % EFI_PAGE_SIZE) != 0) || (EFI_ERROR(FspUpdSignatureCheck(ApiIdx, ApiParam)))) {
Status = EFI_INVALID_PARAMETER;
}
} else if (ApiIdx == 2) {
//
// NotifyPhase check
//
if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {
Status = EFI_UNSUPPORTED;
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
}
}
} else if (ApiIdx == 3) {
//
// FspMemoryInit check
//
if ((UINT32)FspData != 0xFFFFFFFF) {
Status = EFI_UNSUPPORTED;
} else if ((FspRtBuffer == NULL) || ((FspRtBuffer->BootLoaderTolumSize % EFI_PAGE_SIZE) != 0) || (EFI_ERROR(FspUpdSignatureCheck(ApiIdx, ApiParam)))) {
Status = EFI_INVALID_PARAMETER;
}
} else if (ApiIdx == 4) {
//
// TempRamExit check
//
if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {
Status = EFI_UNSUPPORTED;
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
}
}
} else if (ApiIdx == 5) {
//
// FspSiliconInit check
//
if ((FspData == NULL) || ((UINT32)FspData == 0xFFFFFFFF)) {
Status = EFI_UNSUPPORTED;
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
} else if (EFI_ERROR(FspUpdSignatureCheck(ApiIdx, ApiParam))) {
Status = EFI_INVALID_PARAMETER;
}
}
} else {
Status = EFI_UNSUPPORTED;
}
return Status;
}
/**
This function gets the boot FV offset in FSP.
@return the boot firmware volumen offset inside FSP binary
**/
UINT32
EFIAPI
GetBootFirmwareVolumeOffset (
VOID
)
{
return PcdGet32 (PcdFspBootFirmwareVolumeBase) - PcdGet32 (PcdFspAreaBaseAddress);
}

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/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _SEC_FSP_H_
#define _SEC_FSPE_H_
#include <PiPei.h>
#include <FspApi.h>
#include <Library/PcdLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/SerialPortLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/FspCommonLib.h>
#include <Library/FspSecPlatformLib.h>
#define FSP_MCUD_SIGNATURE SIGNATURE_32 ('M', 'C', 'U', 'D')
#define FSP_PER0_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', '0')
/**
Calculate the FSP IDT gate descriptor.
@param[in] IdtEntryTemplate IDT gate descriptor template.
@return FSP specific IDT gate descriptor.
**/
UINT64
FspGetExceptionHandler(
IN UINT64 IdtEntryTemplate
);
/**
Initialize the FSP global data region.
It needs to be done as soon as possible after the stack is setup.
@param[in,out] PeiFspData Pointer of the FSP global data.
@param[in] BootLoaderStack BootLoader stack.
@param[in] ApiIdx The index of the FSP API.
**/
VOID
FspGlobalDataInit (
IN OUT FSP_GLOBAL_DATA *PeiFspData,
IN UINT32 BootLoaderStack,
IN UINT8 ApiIdx
);
/**
Adjust the FSP data pointers after the stack is migrated to memory.
@param[in] OffsetGap The offset gap between the old stack and the new stack.
**/
VOID
FspDataPointerFixUp (
IN UINT32 OffsetGap
);
/**
This interface returns the base address of FSP binary.
@return FSP binary base address.
**/
UINT32
EFIAPI
AsmGetFspBaseAddress (
VOID
);
/**
This interface gets FspInfoHeader pointer
@return FSP binary base address.
**/
UINT32
EFIAPI
AsmGetFspInfoHeader (
VOID
);
/**
This function gets the FSP UPD region offset in flash.
@return the offset of the UPD region.
**/
UINT32
EFIAPI
GetFspUpdRegionOffset (
VOID
);
#endif

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IntelFspPkg/FspSecCore/SecMain.c
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/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SecMain.h"
#include "SecFsp.h"
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {
SecTemporaryRamSupport
};
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {
{
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiTemporaryRamSupportPpiGuid,
&gSecTemporaryRamSupportPpi
}
};
//
// These are IDT entries pointing to 08:FFFFFFE4h.
//
UINT64 mIdtEntryTemplate = 0xffff8e000008ffe4ULL;
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCore PeiCore entry point.
@param[in] BootLoaderStack BootLoader stack.
@param[in] ApiIdx the index of API.
@return This function never returns.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume,
IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootLoaderStack,
IN UINT32 ApiIdx
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
FSP_GLOBAL_DATA PeiFspData;
UINT64 ExceptionHandler;
//
// Process all libraries constructor function linked to SecCore.
//
ProcessLibraryConstructorList ();
//
// Initialize floating point operating environment
// to be compliant with UEFI spec.
//
InitializeFloatingPointUnits ();
// |-------------------|---->
// |Idt Table |
// |-------------------|
// |PeiService Pointer | PeiStackSize
// |-------------------|
// | |
// | Stack |
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporayRamSize
// | |
// | |
// |-------------------|----> TempRamBase
IdtTableInStack.PeiService = NULL;
ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionHandler, sizeof (UINT64));
}
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
// Initialize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);
//
// Update the base address and length of Pei temporary memory
//
SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;
SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
SecCoreData.TemporaryRamSize = SizeOfRam;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SizeOfRam >> 1;
SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = SizeOfRam >> 1;
//
// Call PeiCore Entry
//
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);
//
// Should never be here
//
CpuDeadLoop ();
}
/**
This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
permanent memory.
@param[in] PeiServices Pointer to the PEI Services Table.
@param[in] TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
Temporary RAM contents.
@param[in] PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
Temporary RAM contents.
@param[in] CopySize Amount of memory to migrate from temporary to permanent memory.
@retval EFI_SUCCESS The data was successfully returned.
@retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
TemporaryMemoryBase > PermanentMemoryBase.
**/
EFI_STATUS
EFIAPI
SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
)
{
IA32_DESCRIPTOR IdtDescriptor;
VOID* OldHeap;
VOID* NewHeap;
VOID* OldStack;
VOID* NewStack;
OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID*)((UINTN)PermanentMemoryBase + CopySize / 2);
OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize / 2);
NewStack = (VOID*)(UINTN)PermanentMemoryBase;
//
// Migrate Heap
//
CopyMem (NewHeap, OldHeap, CopySize / 2);
//
// Migrate Stack
//
CopyMem (NewStack, OldStack, CopySize / 2);
//
// We need *not* fix the return address because currently,
// The PeiCore is executed in flash.
//
//
// Rebase IDT table in permanent memory
//
AsmReadIdtr (&IdtDescriptor);
IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;
AsmWriteIdtr (&IdtDescriptor);
//
// Fixed the FSP data pointer
//
FspDataPointerFixUp ((UINTN)NewStack - (UINTN)OldStack);
//
// SecSwitchStack function must be invoked after the memory migration
// immediately, also we need fixup the stack change caused by new call into
// permanent memory.
//
SecSwitchStack (
(UINT32) (UINTN) OldStack,
(UINT32) (UINTN) NewStack
);
return EFI_SUCCESS;
}

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/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _SEC_CORE_H_
#define _SEC_CORE_H_
#include <PiPei.h>
#include <Ppi/TemporaryRamSupport.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciCf8Lib.h>
#include <Library/SerialPortLib.h>
#include <Library/FspSwitchStackLib.h>
#include <Library/FspCommonLib.h>
#include <FspApi.h>
#define SEC_IDT_ENTRY_COUNT 34
typedef VOID (*PEI_CORE_ENTRY) ( \
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \
);
typedef struct _SEC_IDT_TABLE {
EFI_PEI_SERVICES *PeiService;
UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];
} SEC_IDT_TABLE;
/**
Switch the stack in the temporary memory to the one in the permanent memory.
This function must be invoked after the memory migration immediately. The relative
position of the stack in the temporary and permanent memory is same.
@param[in] TemporaryMemoryBase Base address of the temporary memory.
@param[in] PermenentMemoryBase Base address of the permanent memory.
**/
VOID
EFIAPI
SecSwitchStack (
IN UINT32 TemporaryMemoryBase,
IN UINT32 PermenentMemoryBase
);
/**
This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
permanent memory.
@param[in] PeiServices Pointer to the PEI Services Table.
@param[in] TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
Temporary RAM contents.
@param[in] PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
Temporary RAM contents.
@param[in] CopySize Amount of memory to migrate from temporary to permanent memory.
@retval EFI_SUCCESS The data was successfully returned.
@retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
TemporaryMemoryBase > PermanentMemoryBase.
**/
EFI_STATUS
EFIAPI
SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
);
/**
Initializes floating point units for requirement of UEFI specification.
This function initializes floating-point control word to 0x027F (all exceptions
masked,double-precision, round-to-nearest) and multimedia-extensions control word
(if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
for masked underflow).
**/
VOID
EFIAPI
InitializeFloatingPointUnits (
VOID
);
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCore PeiCore entry point.
@param[in] BootLoaderStack BootLoader stack.
@param[in] ApiIdx the index of API.
@return This function never returns.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume,
IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootLoaderStack,
IN UINT32 ApiIdx
);
/**
Autogenerated function that calls the library constructors for all of the module's
dependent libraries. This function must be called by the SEC Core once a stack has
been established.
**/
VOID
EFIAPI
ProcessLibraryConstructorList (
VOID
);
#endif

BIN
IntelFspPkg/FspSecCore/Vtf0/Bin/ResetVec.ia32.raw
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Binary file not shown.

47
IntelFspPkg/FspSecCore/Vtf0/Build.py
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@ -1,47 +0,0 @@
## @file
# Automate the process of building the various reset vector types
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
import glob
import os
import subprocess
import sys
def RunCommand(commandLine):
#print ' '.join(commandLine)
return subprocess.call(commandLine)
for filename in glob.glob(os.path.join('Bin', '*.raw')):
os.remove(filename)
arch = 'ia32'
debugType = None
output = os.path.join('Bin', 'ResetVec')
output += '.' + arch
if debugType is not None:
output += '.' + debugType
output += '.raw'
commandLine = (
'nasm',
'-D', 'ARCH_%s' % arch.upper(),
'-D', 'DEBUG_%s' % str(debugType).upper(),
'-o', output,
'ResetVectorCode.asm',
)
ret = RunCommand(commandLine)
print '\tASM\t' + output
if ret != 0: sys.exit(ret)
commandLine = (
'python',
'Tools/FixupForRawSection.py',
output,
)
print '\tFIXUP\t' + output
ret = RunCommand(commandLine)
if ret != 0: sys.exit(ret)

97
IntelFspPkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
View File

@ -1,97 +0,0 @@
;; @file
; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;;
BITS 16
;
; The layout of this file is fixed. The build tool makes assumption of the layout.
;
ORG 0x0
;
; Reserved
;
ReservedData: DD 0eeeeeeeeh, 0eeeeeeeeh
; ORG 0x10
TIMES 0x10-($-$$) DB 0
;
; This is located at 0xFFFFFFD0h
;
mov di, "AP"
jmp ApStartup
; ORG 0x20
TIMES 0x20-($-$$) DB 0
; Pointer to the entry point of the PEI core
; It is located at 0xFFFFFFE0, and is fixed up by some build tool
; So if the value 8..1 appears in the final FD image, tool failure occurs.
;
PeiCoreEntryPoint: DD 0x12345678
;
; This is the handler for all kinds of exceptions. Since it's for debugging
; purpose only, nothing except a deadloop would be done here. Developers could
; analyze the cause of the exception if a debugger had been attached.
;
InterruptHandler:
jmp $
iret
; ORG 0x30
TIMES 0x30-($-$$) DB 0
;
; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte
; Execution starts here upon power-on/platform-reset.
;
ResetHandler:
nop
nop
ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
; SEC entry point relatvie address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm
;
DB 0x0e9
DW -3
; ORG 0x38
TIMES 0x38-($-$$) DB 0
;
; Ap reset vector segment address is at 0xFFFFFFF8
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs
;
ApSegAddress: dd 0x12345678
; ORG 0x3c
TIMES 0x3c-($-$$) DB 0
;
; BFV Base is at 0xFFFFFFFC
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs.
;
BfvBase: DD 0x12345678
;
; Nothing can go here, otherwise the layout of this file would change.
;
; END

11
IntelFspPkg/FspSecCore/Vtf0/ResetVectorCode.asm
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@ -1,11 +0,0 @@
;------------------------------------------------------------------------------
; @file
; This file includes all other code files to assemble the reset vector code
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
%include "Ia16/ResetVec.asm16"

104
IntelFspPkg/FspSecCore/Vtf0/Tools/FixupForRawSection.py
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@ -1,104 +0,0 @@
## @file
# Apply fixup to VTF binary image for FFS Raw section
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
import sys
filename = sys.argv[1]
if filename.lower().find('ia32') >= 0:
d = open(sys.argv[1], 'rb').read()
c = ((len(d) + 4 + 7) & ~7) - 4
if c > len(d):
c -= len(d)
f = open(sys.argv[1], 'wb')
f.write('\x90' * c)
f.write(d)
f.close()
else:
from struct import pack
PAGE_PRESENT = 0x01
PAGE_READ_WRITE = 0x02
PAGE_USER_SUPERVISOR = 0x04
PAGE_WRITE_THROUGH = 0x08
PAGE_CACHE_DISABLE = 0x010
PAGE_ACCESSED = 0x020
PAGE_DIRTY = 0x040
PAGE_PAT = 0x080
PAGE_GLOBAL = 0x0100
PAGE_2M_MBO = 0x080
PAGE_2M_PAT = 0x01000
def NopAlign4k(s):
c = ((len(s) + 0xfff) & ~0xfff) - len(s)
return ('\x90' * c) + s
def PageDirectoryEntries4GbOf2MbPages(baseAddress):
s = ''
for i in range(0x800):
i = (
baseAddress + long(i << 21) +
PAGE_2M_MBO +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_DIRTY +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
s = ''
for i in range(0x200):
i = (
pdeBase +
(min(i, 3) << 12) +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def PageMapLevel4Table4GbOf2MbPages(pdptBase):
s = ''
for i in range(0x200):
i = (
pdptBase +
(min(i, 0) << 12) +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def First4GbPageEntries(topAddress):
PDE = PageDirectoryEntries4GbOf2MbPages(0L)
pml4tBase = topAddress - 0x1000
pdptBase = pml4tBase - 0x1000
pdeBase = pdptBase - len(PDE)
PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
return PDE + PDPT + PML4T
def AlignAndAddPageTables():
d = open(sys.argv[1], 'rb').read()
code = NopAlign4k(d)
topAddress = 0x100000000 - len(code)
d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
f = open(sys.argv[1], 'wb')
f.write(d)
f.close()
AlignAndAddPageTables()

305
IntelFspPkg/Include/FspApi.h
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@ -1,305 +0,0 @@
/** @file
Intel FSP API definition from Intel Firmware Support Package External
Architecture Specification v1.1, April 2015, revision 001.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_API_H_
#define _FSP_API_H_
#define FSP_STATUS EFI_STATUS
#define FSPAPI EFIAPI
/**
FSP Init continuation function prototype.
Control will be returned to this callback function after FspInit API call.
@param[in] Status Status of the FSP INIT API.
@param[in] HobBufferPtr Pointer to the HOB data structure defined in the PI specification.
**/
typedef
VOID
(* CONTINUATION_PROC) (
IN EFI_STATUS Status,
IN VOID *HobListPtr
);
#pragma pack(1)
typedef struct {
///
/// Base address of the microcode region.
///
UINT32 MicrocodeRegionBase;
///
/// Length of the microcode region.
///
UINT32 MicrocodeRegionLength;
///
/// Base address of the cacheable flash region.
///
UINT32 CodeRegionBase;
///
/// Length of the cacheable flash region.
///
UINT32 CodeRegionLength;
} FSP_TEMP_RAM_INIT_PARAMS;
typedef struct {
///
/// Non-volatile storage buffer pointer.
///
VOID *NvsBufferPtr;
///
/// Runtime buffer pointer
///
VOID *RtBufferPtr;
///
/// Continuation function address
///
CONTINUATION_PROC ContinuationFunc;
} FSP_INIT_PARAMS;
typedef struct {
///
/// Stack top pointer used by the bootloader.
/// The new stack frame will be set up at this location after FspInit API call.
///
UINT32 *StackTop;
///
/// Current system boot mode.
///
UINT32 BootMode;
///
/// User platform configuraiton data region pointer.
///
VOID *UpdDataRgnPtr;
//
// Below field is added in FSP EAS v1.1
//
///
/// The size of memory to be reserved below the top of low usable memory (TOLUM)
/// for BootLoader usage. This is optional and value can be zero. If non-zero, the
/// size must be a multiple of 4KB.
///
UINT32 BootLoaderTolumSize;
///
/// Reserved
///
UINT32 Reserved[6];
} FSP_INIT_RT_COMMON_BUFFER;
typedef enum {
///
/// Notification code for post PCI enuermation
///
EnumInitPhaseAfterPciEnumeration = 0x20,
///
/// Notification code before transfering control to the payload
///
EnumInitPhaseReadyToBoot = 0x40
} FSP_INIT_PHASE;
typedef struct {
///
/// Notification phase used for NotifyPhase API
///
FSP_INIT_PHASE Phase;
} NOTIFY_PHASE_PARAMS;
typedef struct {
///
/// Non-volatile storage buffer pointer.
///
VOID *NvsBufferPtr;
///
/// Runtime buffer pointer
///
VOID *RtBufferPtr;
///
/// Pointer to the HOB data structure defined in the PI specification
///
VOID **HobListPtr;
} FSP_MEMORY_INIT_PARAMS;
#pragma pack()
/**
This FSP API is called soon after coming out of reset and before memory and stack is
available. This FSP API will load the microcode update, enable code caching for the
region specified by the boot loader and also setup a temporary stack to be used until
main memory is initialized.
A hardcoded stack can be set up with the following values, and the "esp" register
initialized to point to this hardcoded stack.
1. The return address where the FSP will return control after setting up a temporary
stack.
2. A pointer to the input parameter structure
However, since the stack is in ROM and not writeable, this FSP API cannot be called
using the "call" instruction, but needs to be jumped to.
@param[in] TempRaminitParamPtr Address pointer to the FSP_TEMP_RAM_INIT_PARAMS structure.
@retval EFI_SUCCESS Temp RAM was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid..
@retval EFI_NOT_FOUND No valid microcode was found in the microcode region.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR Temp RAM initialization failed.
If this function is successful, the FSP initializes the ECX and EDX registers to point to
a temporary but writeable memory range available to the boot loader and returns with
FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary
memory range and EDX points to the end of the range. Boot loader is free to use the
whole range described. Typically the boot loader can reload the ESP register to point
to the end of this returned range so that it can be used as a standard stack.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_INIT) (
IN FSP_TEMP_RAM_INIT_PARAMS *FspTempRamInitPtr
);
/**
This FSP API is called after TempRamInitEntry. This FSP API initializes the memory,
the CPU and the chipset to enable normal operation of these devices. This FSP API
accepts a pointer to a data structure that will be platform dependent and defined for
each FSP binary. This will be documented in the Integration Guide for each FSP
release.
The boot loader provides a continuation function as a parameter when calling FspInit.
After FspInit completes its execution, it does not return to the boot loader from where
it was called but instead returns control to the boot loader by calling the continuation
function which is passed to FspInit as an argument.
@param[in] FspInitParamPtr Address pointer to the FSP_INIT_PARAMS structure.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_INIT) (
IN OUT FSP_INIT_PARAMS *FspInitParamPtr
);
#define FSP_FSP_INIT FSP_INIT
/**
This FSP API is used to notify the FSP about the different phases in the boot process.
This allows the FSP to take appropriate actions as needed during different initialization
phases. The phases will be platform dependent and will be documented with the FSP
release. The current FSP supports two notify phases:
Post PCI enumeration
Ready To Boot
@param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS
@retval EFI_SUCCESS The notification was handled successfully.
@retval EFI_UNSUPPORTED The notification was not called in the proper order.
@retval EFI_INVALID_PARAMETER The notification code is invalid.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_NOTIFY_PHASE) (
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr
);
/**
This FSP API is called after TempRamInit and initializes the memory.
This FSP API accepts a pointer to a data structure that will be platform dependent
and defined for each FSP binary. This will be documented in Integration guide with
each FSP release.
After FspMemInit completes its execution, it passes the pointer to the HobList and
returns to the boot loader from where it was called. BootLoader is responsible to
migrate it's stack and data to Memory.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
complete the silicon initialization and provides bootloader an opportunity to get
control after system memory is available and before the temporary RAM is torn down.
These APIs are mutually exclusive to the FspInit API.
@param[in][out] FspMemoryInitParamPtr Address pointer to the FSP_MEMORY_INIT_PARAMS
structure.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_MEMORY_INIT) (
IN OUT FSP_MEMORY_INIT_PARAMS *FspMemoryInitParamPtr
);
/**
This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
that will be platform dependent and defined for each FSP binary. This will be
documented in Integration Guide.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
complete the silicon initialization and provides bootloader an opportunity to get
control after system memory is available and before the temporary RAM is torn down.
These APIs are mutually exclusive to the FspInit API.
@param[in][out] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.
This structure is normally defined in the Integration Guide.
And if it is not defined in the Integration Guide, pass NULL.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_TEMP_RAM_EXIT) (
IN OUT VOID *TempRamExitParamPtr
);
/**
This FSP API is called after TempRamExit API.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the
silicon initialization.
These APIs are mutually exclusive to the FspInit API.
@param[in][out] FspSiliconInitParamPtr Pointer to the Silicon Init parameters structure.
This structure is normally defined in the Integration Guide.
And if it is not defined in the Integration Guide, pass NULL.
@retval EFI_SUCCESS FSP execution environment was initialized successfully.
@retval EFI_INVALID_PARAMETER Input parameters are invalid.
@retval EFI_UNSUPPORTED The FSP calling conditions were not met.
@retval EFI_DEVICE_ERROR FSP initialization failed.
**/
typedef
EFI_STATUS
(EFIAPI *FSP_SILICON_INIT) (
IN OUT VOID *FspSiliconInitParamPtr
);
///
/// FSP API Return Status Code for backward compatibility with v1.0
///@{
#define FSP_SUCCESS EFI_SUCCESS
#define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER
#define FSP_UNSUPPORTED EFI_UNSUPPORTED
#define FSP_NOT_READY EFI_NOT_READY
#define FSP_DEVICE_ERROR EFI_DEVICE_ERROR
#define FSP_OUT_OF_RESOURCES EFI_OUT_OF_RESOURCES
#define FSP_VOLUME_CORRUPTED EFI_VOLUME_CORRUPTED
#define FSP_NOT_FOUND EFI_NOT_FOUND
#define FSP_TIMEOUT EFI_TIMEOUT
#define FSP_ABORTED EFI_ABORTED
#define FSP_INCOMPATIBLE_VERSION EFI_INCOMPATIBLE_VERSION
#define FSP_SECURITY_VIOLATION EFI_SECURITY_VIOLATION
#define FSP_CRC_ERROR EFI_CRC_ERROR
///@}
#endif

168
IntelFspPkg/Include/FspInfoHeader.h
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@ -1,168 +0,0 @@
/** @file
Intel FSP Info Header definition from Intel Firmware Support Package External
Architecture Specification v1.1, April 2015, revision 001.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_INFO_HEADER_H_
#define _FSP_INFO_HEADER_H_
#define FSP_HEADER_REVISION_1 1
#define FSP_HEADER_REVISION_2 2
#define FSPE_HEADER_REVISION_1 1
#define FSPP_HEADER_REVISION_1 1
///
/// Fixed FSP header offset in the FSP image
///
#define FSP_INFO_HEADER_OFF 0x94
#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
#pragma pack(1)
typedef struct {
///
/// Byte 0x00: Signature ('FSPH') for the FSP Information Header
///
UINT32 Signature;
///
/// Byte 0x04: Length of the FSP Information Header
///
UINT32 HeaderLength;
///
/// Byte 0x08: Reserved
///
UINT8 Reserved1[3];
///
/// Byte 0x0B: Revision of the FSP Information Header
///
UINT8 HeaderRevision;
///
/// Byte 0x0C: Revision of the FSP binary
///
UINT32 ImageRevision;
///
/// Byte 0x10: Signature string that will help match the FSP Binary to a supported
/// hardware configuration.
///
CHAR8 ImageId[8];
///
/// Byte 0x18: Size of the entire FSP binary
///
UINT32 ImageSize;
///
/// Byte 0x1C: FSP binary preferred base address
///
UINT32 ImageBase;
///
/// Byte 0x20: Attribute for the FSP binary
///
UINT32 ImageAttribute;
///
/// Byte 0x24: Offset of the FSP configuration region
///
UINT32 CfgRegionOffset;
///
/// Byte 0x28: Size of the FSP configuration region
///
UINT32 CfgRegionSize;
///
/// Byte 0x2C: Number of API entries this FSP supports
///
UINT32 ApiEntryNum;
///
/// Byte 0x30: The offset for the API to setup a temporary stack till the memory
/// is initialized.
///
UINT32 TempRamInitEntryOffset;
///
/// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)
///
UINT32 FspInitEntryOffset;
///
/// Byte 0x38: The offset for the API to inform the FSP about the different stages
/// in the boot process
///
UINT32 NotifyPhaseEntryOffset;
///
/// Below fields are added in FSP Revision 2
///
///
/// Byte 0x3C: The offset for the API to initialize the memory
///
UINT32 FspMemoryInitEntryOffset;
///
/// Byte 0x40: The offset for the API to tear down temporary RAM
///
UINT32 TempRamExitEntryOffset;
///
/// Byte 0x44: The offset for the API to initialize the CPU and chipset
///
UINT32 FspSiliconInitEntryOffset;
} FSP_INFO_HEADER;
///
/// Below structure is added in FSP version 2
///
#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')
typedef struct {
///
/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header
///
UINT32 Signature;
///
/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
///
UINT32 Length;
///
/// Byte 0x08: FSP producer defined revision of the table.
///
UINT8 Revision;
///
/// Byte 0x09: Reserved for future use.
///
UINT8 Reserved;
///
/// Byte 0x0A: FSP producer identification string
///
CHAR8 FspProducerId[6];
///
/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
///
UINT32 FspProducerRevision;
///
/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
///
UINT32 FspProducerDataSize;
///
/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
///
} FSP_INFO_EXTENDED_HEADER;
//
// A generic table search algorithm for additional tables can be implemented with a
// signature search algorithm until a terminator signature 'FSPP' is found.
//
#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')
#pragma pack()
#endif

15
IntelFspPkg/Include/Guid/FspHeaderFile.h
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@ -1,15 +0,0 @@
/** @file
Intel FSP Header File Guid definition from Intel Firmware Support Package External
Architecture Specification v1.1, April 2015, revision 001.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_HEADER_FILE_GUID__
#define __FSP_HEADER_FILE_GUID__
extern EFI_GUID gFspHeaderFileGuid;
#endif

16
IntelFspPkg/Include/Guid/GuidHobFsp.h
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@ -1,16 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __GUID_HOB_FSP_GUID__
#define __GUID_HOB_FSP_GUID__
#include <Guid/GuidHobFspEas.h>
#include <GuidHobFspGfx.h>
#include <GuidHobFspTseg.h>
#include <GuidHobFspMisc.h>
#endif

19
IntelFspPkg/Include/Guid/GuidHobFspEas.h
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@ -1,19 +0,0 @@
/** @file
Intel FSP Hob Guid definition from Intel Firmware Support Package External
Architecture Specification v1.1, April 2015, revision 001.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __GUID_HOB_FSP_EAS_GUID__
#define __GUID_HOB_FSP_EAS_GUID__
extern EFI_GUID gFspBootLoaderTemporaryMemoryGuid;
extern EFI_GUID gFspBootLoaderTolumHobGuid; // FSP EAS v1.1
extern EFI_GUID gFspReservedMemoryResourceHobGuid;
extern EFI_GUID gFspNonVolatileStorageHobGuid;
#endif

24
IntelFspPkg/Include/Library/CacheAsRamLib.h
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@ -1,24 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CACHE_AS_RAM_LIB_H_
#define _CACHE_AS_RAM_LIB_H_
/**
This function disable CAR.
@param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD
**/
VOID
EFIAPI
DisableCacheAsRam (
IN BOOLEAN DisableCar
);
#endif

56
IntelFspPkg/Include/Library/CacheLib.h
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@ -1,56 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CACHE_LIB_H_
#define _CACHE_LIB_H_
//
// EFI_MEMORY_CACHE_TYPE
//
typedef INT32 EFI_MEMORY_CACHE_TYPE;
#define EFI_CACHE_UNCACHEABLE 0
#define EFI_CACHE_WRITECOMBINING 1
#define EFI_CACHE_WRITETHROUGH 4
#define EFI_CACHE_WRITEPROTECTED 5
#define EFI_CACHE_WRITEBACK 6
/**
Reset all the MTRRs to a known state.
@retval EFI_SUCCESS All MTRRs have been reset successfully.
**/
EFI_STATUS
EFIAPI
ResetCacheAttributes (
VOID
);
/**
Given the memory range and cache type, programs the MTRRs.
@param[in] MemoryAddress Base Address of Memory to program MTRR.
@param[in] MemoryLength Length of Memory to program MTRR.
@param[in] MemoryCacheType Cache Type.
@retval EFI_SUCCESS Mtrr are set successfully.
@retval EFI_LOAD_ERROR No empty MTRRs to use.
@retval EFI_INVALID_PARAMETER The input parameter is not valid.
@retval others An error occurs when setting MTTR.
**/
EFI_STATUS
EFIAPI
SetCacheAttributes (
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
);
#endif

23
IntelFspPkg/Include/Library/DebugDeviceLib.h
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@ -1,23 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __DEBUG_DEVICE_LIB_H__
#define __DEBUG_DEVICE_LIB_H__
/**
Returns the debug print device enable state.
@return Debug print device enable state.
**/
UINT8
EFIAPI
GetDebugPrintDeviceEnable (
VOID
);
#endif

266
IntelFspPkg/Include/Library/FspCommonLib.h
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@ -1,266 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_COMMON_LIB_H_
#define _FSP_COMMON_LIB_H_
#include <FspGlobalData.h>
#include <FspMeasurePointId.h>
/**
This function sets the FSP global data pointer.
@param[in] FspData Fsp global data pointer.
**/
VOID
EFIAPI
SetFspGlobalDataPointer (
IN FSP_GLOBAL_DATA *FspData
);
/**
This function gets the FSP global data pointer.
**/
FSP_GLOBAL_DATA *
EFIAPI
GetFspGlobalDataPointer (
VOID
);
/**
This function gets back the FSP API parameter passed by the bootlaoder.
@retval ApiParameter FSP API parameter passed by the bootlaoder.
**/
UINT32
EFIAPI
GetFspApiParameter (
VOID
);
/**
This function sets the FSP API parameter in the stack.
@param[in] Value New parameter value.
**/
VOID
EFIAPI
SetFspApiParameter (
IN UINT32 Value
);
/**
This function sets the FSP continuation function parameters in the stack.
@param[in] Value New parameter value to set.
@param[in] Index Parameter index.
**/
VOID
EFIAPI
SetFspContinuationFuncParameter (
IN UINT32 Value,
IN UINT32 Index
);
/**
This function changes the BootLoader return address in stack.
@param[in] ReturnAddress Address to return.
**/
VOID
EFIAPI
SetFspApiReturnAddress (
IN UINT32 ReturnAddress
);
/**
This function set the API status code returned to the BootLoader.
@param[in] ReturnStatus Status code to return.
**/
VOID
EFIAPI
SetFspApiReturnStatus (
IN UINT32 ReturnStatus
);
/**
This function sets the context switching stack to a new stack frame.
@param[in] NewStackTop New core stack to be set.
**/
VOID
EFIAPI
SetFspCoreStackPointer (
IN VOID *NewStackTop
);
/**
This function sets the platform specific data pointer.
@param[in] PlatformData Fsp platform specific data pointer.
**/
VOID
EFIAPI
SetFspPlatformDataPointer (
IN VOID *PlatformData
);
/**
This function gets the platform specific data pointer.
@param[in] PlatformData Fsp platform specific data pointer.
**/
VOID *
EFIAPI
GetFspPlatformDataPointer (
VOID
);
/**
This function sets the UPD data pointer.
@param[in] UpdDataRgnPtr UPD data pointer.
**/
VOID
EFIAPI
SetFspUpdDataPointer (
IN VOID *UpdDataRgnPtr
);
/**
This function gets the UPD data pointer.
@return UpdDataRgnPtr UPD data pointer.
**/
VOID *
EFIAPI
GetFspUpdDataPointer (
VOID
);
/**
This function sets the memory init UPD data pointer.
@param[in] MemoryInitUpdPtr memory init UPD data pointer.
**/
VOID
EFIAPI
SetFspMemoryInitUpdDataPointer (
IN VOID *MemoryInitUpdPtr
);
/**
This function gets the memory init UPD data pointer.
@return memory init UPD data pointer.
**/
VOID *
EFIAPI
GetFspMemoryInitUpdDataPointer (
VOID
);
/**
This function sets the silicon init UPD data pointer.
@param[in] SiliconInitUpdPtr silicon init UPD data pointer.
**/
VOID
EFIAPI
SetFspSiliconInitUpdDataPointer (
IN VOID *SiliconInitUpdPtr
);
/**
This function gets the silicon init UPD data pointer.
@return silicon init UPD data pointer.
**/
VOID *
EFIAPI
GetFspSiliconInitUpdDataPointer (
VOID
);
/**
Set FSP measurement point timestamp.
@param[in] Id Measurement point ID.
@return performance timestamp.
**/
UINT64
EFIAPI
SetFspMeasurePoint (
IN UINT8 Id
);
/**
This function gets the FSP info header pointer.
@retval FspInfoHeader FSP info header pointer
**/
FSP_INFO_HEADER *
EFIAPI
GetFspInfoHeader (
VOID
);
/**
This function gets the FSP info header pointer from the API context.
@retval FspInfoHeader FSP info header pointer
**/
FSP_INFO_HEADER *
EFIAPI
GetFspInfoHeaderFromApiContext (
VOID
);
/**
This function gets the VPD data pointer.
@return VpdDataRgnPtr VPD data pointer.
**/
VOID *
EFIAPI
GetFspVpdDataPointer (
VOID
);
/**
This function gets FSP API calling mode.
@retval API calling mode
**/
UINT8
EFIAPI
GetFspApiCallingMode (
VOID
);
/**
This function sets FSP API calling mode.
@param[in] Mode API calling mode
**/
VOID
EFIAPI
SetFspApiCallingMode (
UINT8 Mode
);
#endif

68
IntelFspPkg/Include/Library/FspPlatformLib.h
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@ -1,68 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_PLATFORM_LIB_H_
#define _FSP_PLATFORM_LIB_H_
/**
Get system memory from HOB.
@param[in,out] LowMemoryLength less than 4G memory length
@param[in,out] HighMemoryLength greater than 4G memory length
**/
VOID
EFIAPI
FspGetSystemMemorySize (
IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength
);
/**
Migrate BootLoader data before destroying CAR.
**/
VOID
EFIAPI
FspMigrateTemporaryMemory (
VOID
);
/**
Set a new stack frame for the continuation function.
**/
VOID
EFIAPI
FspSetNewStackFrame (
VOID
);
/**
This function transfer control to the ContinuationFunc passed in by the
BootLoader.
**/
VOID
EFIAPI
FspInitDone (
VOID
);
/**
This function handle NotifyPhase API call from the BootLoader.
It gives control back to the BootLoader after it is handled. If the
Notification code is a ReadyToBoot event, this function will return
and FSP continues the remaining execution until it reaches the DxeIpl.
**/
VOID
EFIAPI
FspWaitForNotify (
VOID
);
#endif

82
IntelFspPkg/Include/Library/FspSecPlatformLib.h
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@ -1,82 +0,0 @@
/** @file
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_SEC_PLATFORM_LIB_H_
#define _FSP_SEC_PLATFORM_LIB_H_
/**
This function performs platform level initialization.
This function must be in ASM file, because stack is not established yet.
This function is optional. If a library instance does not provide this function, the default empty one will be used.
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
@retval in saved in EAX - 0 means platform initialization success.
other means platform initialization fail.
**/
UINT32
EFIAPI
SecPlatformInit (
VOID
);
/**
This function loads Microcode.
This function must be in ASM file, because stack is not established yet.
This function is optional. If a library instance does not provide this function, the default one will be used.
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
@param TempRamInitParamPtr A data structure to hold microcode parameter. It is saved in ESP.
@retval in saved in EAX - 0 means Microcode is loaded successfully.
other means Microcode is not loaded successfully.
**/
UINT32
EFIAPI
LoadMicrocode (
IN FSP_TEMP_RAM_INIT_PARAMS *TempRamInitParamPtr
);
/**
This function initializes the CAR.
This function must be in ASM file, because stack is not established yet.
The callee should not use XMM6/XMM7.
The return address is saved in MM7.
@param TempRamInitParamPtr A data structure to hold microcode parameter. It is saved in ESP.
@retval in saved in EAX - 0 means CAR initialization success.
other means CAR initialization fail.
**/
UINT32
EFIAPI
SecCarInit (
IN FSP_TEMP_RAM_INIT_PARAMS *TempRamInitParamPtr
);
/**
This function check the signture of UPD.
@param[in] ApiIdx Internal index of the FSP API.
@param[in] ApiParam Parameter of the FSP API.
**/
EFI_STATUS
EFIAPI
FspUpdSignatureCheck (
IN UINT32 ApiIdx,
IN VOID *ApiParam
);
#endif

39
IntelFspPkg/Include/Library/FspSwitchStackLib.h
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@ -1,39 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_SWITCH_STACK_LIB_H_
#define _FSP_SWITCH_STACK_LIB_H_
/**
This function will switch the current stack to the previous saved stack.
Before calling the previous stack has to be set in FSP_GLOBAL_DATA.CoreStack.
EIP
FLAGS 16 bit FLAGS 16 bit
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
DWORD IDT base1
StackPointer: DWORD IDT base2
@return ReturnKey After switching to the saved stack,
this value will be saved in eax before returning.
**/
UINT32
EFIAPI
Pei2LoaderSwitchStack (
VOID
);
#endif

41
IntelFspPkg/Include/Private/FspGlobalData.h
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@ -1,41 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_GLOBAL_DATA_H_
#define _FSP_GLOBAL_DATA_H_
#include <FspInfoHeader.h>
#pragma pack(1)
typedef struct {
VOID *DataPtr;
UINT32 MicrocodeRegionBase;
UINT32 MicrocodeRegionSize;
UINT32 CodeRegionBase;
UINT32 CodeRegionSize;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')
typedef struct {
UINT32 Signature;
UINT32 CoreStack;
FSP_PLAT_DATA PlatformData;
FSP_INFO_HEADER *FspInfoHeader;
VOID *UpdDataRgnPtr;
VOID *MemoryInitUpdPtr;
VOID *SiliconInitUpdPtr;
UINT8 ApiMode;
UINT8 Reserved[3];
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
#pragma pack()
#endif

42
IntelFspPkg/Include/Private/FspMeasurePointId.h
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@ -1,42 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_MEASURE_POINT_ID_H_
#define _FSP_MEASURE_POINT_ID_H_
//
// 0xD0 - 0xEF are reserved for FSP common measure point
//
#define FSP_PERF_ID_MRCINIT_ENTRY 0xD0
#define FSP_PERF_ID_MRCINIT_EXIT (FSP_PERF_ID_MRCINIT_ENTRY + 1)
#define FSP_PERF_ID_SOCINIT_ENTRY 0xD8
#define FSP_PERF_ID_SOCINIT_EXIT (FSP_PERF_ID_SOCINIT_ENTRY + 1)
#define FSP_PERF_ID_PCHINIT_ENTRY 0xDA
#define FSP_PERF_ID_PCHINIT_EXIT (FSP_PERF_ID_PCHINIT_ENTRY + 1)
#define FSP_PERF_ID_CPUINIT_ENTRY 0xE0
#define FSP_PERF_ID_CPUINIT_EXIT (FSP_PERF_ID_CPUINIT_ENTRY + 1)
//
// 0xF0 - 0xFF are reserved for FSP API
//
#define FSP_PERF_ID_API_TMPRAMINIT_ENTRY 0xF0
#define FSP_PERF_ID_API_TMPRAMINIT_EXIT (FSP_PERF_ID_API_TMPRAMINIT_ENTRY + 1)
#define FSP_PERF_ID_API_FSPINIT_ENTRY 0xF2
#define FSP_PERF_ID_API_FSPINIT_EXIT (FSP_PERF_ID_API_FSPINIT_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_POSTPCI_ENTRY 0xF4
#define FSP_PERF_ID_API_NOTIFY_POSTPCI_EXIT (FSP_PERF_ID_API_NOTIFY_POSTPCI_ENTRY + 1)
#define FSP_PERF_ID_API_NOTIFY_RDYBOOT_ENTRY 0xF6
#define FSP_PERF_ID_API_NOTIFY_RDYBOOT_EXIT (FSP_PERF_ID_API_NOTIFY_RDYBOOT_ENTRY + 1)
#endif

26
IntelFspPkg/Include/Private/FspPatchTable.h
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@ -1,26 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_PATCH_TABLE_H_
#define _FSP_PATCH_TABLE_H_
#pragma pack(1)
#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE
typedef struct {
UINT32 Signature;
UINT16 HeaderLength;
UINT8 HeaderRevision;
UINT8 Reserved;
UINT32 PatchEntryNum;
UINT32 PatchData[FixedPcdGet32(PcdFspMaxPatchEntry)];
} FSP_PATCH_TABLE;
#pragma pack()
#endif

13
IntelFspPkg/Include/Private/GuidHobFspGfx.h
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@ -1,13 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __GUID_HOB_FSP_GFX_GUID__
#define __GUID_HOB_FSP_GFX_GUID__
extern EFI_GUID gFspReservedMemoryResourceHobGfxGuid;
#endif

13
IntelFspPkg/Include/Private/GuidHobFspMisc.h
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@ -1,13 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __GUID_HOB_FSP_MISC_GUID__
#define __GUID_HOB_FSP_MISC_GUID__
extern EFI_GUID gFspReservedMemoryResourceHobMiscGuid;
#endif

13
IntelFspPkg/Include/Private/GuidHobFspTseg.h
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@ -1,13 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __GUID_HOB_FSP_TSEG_GUID__
#define __GUID_HOB_FSP_TSEG_GUID__
extern EFI_GUID gFspReservedMemoryResourceHobTsegGuid;
#endif

72
IntelFspPkg/IntelFspPkg.dec
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@ -1,72 +0,0 @@
## @file
# Provides driver and definitions to build fsp in EDKII bios.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = IntelFspPkg
PACKAGE_GUID = 444C6CDF-55BD-4744-8F74-AE98B003B955
PACKAGE_VERSION = 0.1
[Includes]
Include
Include/Private
[LibraryClasses]
## @libraryclass Provides cache-as-ram support.
CacheAsRamLib|Include/Library/CacheAsRamLib.h
## @libraryclass Provides cache setting on MTRR.
CacheLib|Include/Library/CacheLib.h
## @libraryclass Provides debug device abstraction.
DebugDeviceLib|Include/Library/DebugDeviceLib.h
## @libraryclass Provides FSP related services.
FspCommonLib|Include/Library/FspCommonLib.h
## @libraryclass Provides FSP platform related actions.
FspPlatformLib|Include/Library/FspPlatformLib.h
## @libraryclass Provides FSP switch stack function.
FspSwitchStackLib|Include/Library/FspSwitchStackLib.h
## @libraryclass Provides FSP platform sec related actions.
FspSecPlatformLib|Include/Library/FspSecPlatformLib.h
[Guids]
#
# GUID defined in package
#
gIntelFspPkgTokenSpaceGuid = { 0x834c0c5f, 0xadb3, 0x4372, { 0xae, 0xeb, 0x03, 0xe4, 0xe9, 0xe6, 0xc5, 0x91 } }
# Guid define in FSP EAS
gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }
gFspBootLoaderTemporaryMemoryGuid = { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }
gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
gFspBootLoaderTolumHobGuid = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1
# Guid defined by platform
gFspReservedMemoryResourceHobTsegGuid = { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }
gFspReservedMemoryResourceHobGfxGuid = { 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } }
gFspReservedMemoryResourceHobMiscGuid = { 0x00d6b14b, 0x7dd0, 0x4062, { 0x88, 0x21, 0xe5, 0xf9, 0x6a, 0x2a, 0x1b, 0x00 } }
[PcdsFixedAtBuild]
gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002
gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry | 6|UINT32|0x00002002
gIntelFspPkgTokenSpaceGuid.PcdFspAreaBaseAddress |0xFFF80000|UINT32|0x10000001
gIntelFspPkgTokenSpaceGuid.PcdFspAreaSize |0x00040000|UINT32|0x10000002
gIntelFspPkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003
[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]
gIntelFspPkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000
gIntelFspPkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT32|0x46530100

71
IntelFspPkg/IntelFspPkg.dsc
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@ -1,71 +0,0 @@
## @file
# Provides driver and definitions to build fsp in EDKII bios.
#
# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
PLATFORM_NAME = IntelFspPkg
PLATFORM_GUID = 29C6791F-9EBC-4470-A126-2BB47431AE5E
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/IntelFspPkg
SUPPORTED_ARCHITECTURES = IA32
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
[LibraryClasses]
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
# Dummy - test build only
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
DebugDeviceLib|IntelFspPkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf
# FSP override
DebugLib|IntelFspPkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
# FSP specific lib
CacheAsRamLib|IntelFspPkg/Library/BaseCacheAsRamLibNull/BaseCacheAsRamLibNull.inf
CacheLib|IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf
FspCommonLib|IntelFspPkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
FspPlatformLib|IntelFspPkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
FspSwitchStackLib|IntelFspPkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
FspSecPlatformLib|IntelFspPkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
[LibraryClasses.common.PEIM]
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
[Components]
IntelFspPkg/Library/BaseCacheAsRamLibNull/BaseCacheAsRamLibNull.inf
IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf
IntelFspPkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
IntelFspPkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
IntelFspPkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
IntelFspPkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
IntelFspPkg/FspSecCore/FspSecCore.inf
IntelFspPkg/FspDxeIpl/FspDxeIpl.inf
[PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

26
IntelFspPkg/Library/BaseCacheAsRamLibNull/BaseCacheAsRamLibNull.inf
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@ -1,26 +0,0 @@
## @file
# NULL instance of Base cache as RAM.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseCacheAsRamLibNull
FILE_GUID = FBB4A01B-947E-4d82-B27D-1E207C070053
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CacheAsRamLib
[sources.common]
DisableCacheAsRamNull.c
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]

35
IntelFspPkg/Library/BaseCacheAsRamLibNull/DisableCacheAsRamNull.c
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@ -1,35 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/CacheAsRamLib.h>
/**
This function disable CAR.
@param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD
**/
VOID
EFIAPI
DisableCacheAsRam (
IN BOOLEAN DisableCar
)
{
//
// Disable CAR
//
if (DisableCar) {
AsmInvd ();
} else {
AsmWbinvd();
}
return ;
}

29
IntelFspPkg/Library/BaseCacheLib/BaseCacheLib.inf
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@ -1,29 +0,0 @@
## @file
# Instance of BaseCache.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseCacheLib
FILE_GUID = 01359d99-9446-456d-ada4-50a711c03adb
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CacheLib
[sources.IA32]
CacheLib.c
CacheLibInternal.h
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
BaseMemoryLib
CacheAsRamLib

697
IntelFspPkg/Library/BaseCacheLib/CacheLib.c
View File

@ -1,697 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/CacheLib.h>
#include <Library/CacheAsRamLib.h>
#include "CacheLibInternal.h"
/**
Search the memory cache type for specific memory from MTRR.
@param[in] MemoryAddress the address of target memory
@param[in] MemoryLength the length of target memory
@param[in] ValidMtrrAddressMask the MTRR address mask
@param[out] UsedMsrNum the used MSR number
@param[out] UsedMemoryCacheType the cache type for the target memory
@retval EFI_SUCCESS The memory is found in MTRR and cache type is returned
@retval EFI_NOT_FOUND The memory is not found in MTRR
**/
EFI_STATUS
SearchForExactMtrr (
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN UINT64 ValidMtrrAddressMask,
OUT UINT32 *UsedMsrNum,
OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType
);
/**
Check if CacheType match current default setting.
@param[in] MemoryCacheType input cache type to be checked.
@retval TRUE MemoryCacheType is default MTRR setting.
@retval FALSE MemoryCacheType is NOT default MTRR setting.
**/
BOOLEAN
IsDefaultType (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
);
/**
Return MTRR alignment requirement for base address and size.
@param[in] BaseAddress Base address.
@param[in] Size Size.
@retval Zero Alligned.
@retval Non-Zero Not alligned.
**/
UINT32
CheckMtrrAlignment (
IN UINT64 BaseAddress,
IN UINT64 Size
);
typedef struct {
UINT32 Msr;
UINT32 BaseAddress;
UINT32 Length;
} EFI_FIXED_MTRR;
EFI_FIXED_MTRR mFixedMtrrTable[] = {
{ EFI_MSR_IA32_MTRR_FIX64K_00000, 0, 0x10000},
{ EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000},
{ EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000},
{ EFI_MSR_IA32_MTRR_FIX4K_C0000, 0xC0000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_C8000, 0xC8000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_D0000, 0xD0000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_D8000, 0xD8000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_E0000, 0xE0000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_E8000, 0xE8000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_F0000, 0xF0000, 0x1000},
{ EFI_MSR_IA32_MTRR_FIX4K_F8000, 0xF8000, 0x1000}
};
/**
Given the input, check if the number of MTRR is lesser.
if positive or subtractive.
@param[in] Input Length of Memory to program MTRR.
@retval Zero do positive.
@retval Non-Zero do subtractive.
**/
INT8
CheckDirection (
IN UINT64 Input
)
{
return 0;
}
/**
Disable cache and its mtrr.
@param[out] OldMtrr To return the Old MTRR value
**/
VOID
EfiDisableCacheMtrr (
OUT UINT64 *OldMtrr
)
{
UINT64 TempQword;
//
// Disable Cache MTRR
//
*OldMtrr = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);
TempQword = (*OldMtrr) & ~B_EFI_MSR_GLOBAL_MTRR_ENABLE & ~B_EFI_MSR_FIXED_MTRR_ENABLE;
AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);
AsmDisableCache ();
}
/**
Recover cache MTRR.
@param[in] EnableMtrr Whether to enable the MTRR
@param[in] OldMtrr The saved old MTRR value to restore when not to enable the MTRR
**/
VOID
EfiRecoverCacheMtrr (
IN BOOLEAN EnableMtrr,
IN UINT64 OldMtrr
)
{
UINT64 TempQword;
//
// Enable Cache MTRR
//
if (EnableMtrr) {
TempQword = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);
TempQword |= (UINT64)(B_EFI_MSR_GLOBAL_MTRR_ENABLE | B_EFI_MSR_FIXED_MTRR_ENABLE);
} else {
TempQword = OldMtrr;
}
AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);
AsmEnableCache ();
}
/**
Programming MTRR according to Memory address, length, and type.
@param[in] MtrrNumber the variable MTRR index number
@param[in] MemoryAddress the address of target memory
@param[in] MemoryLength the length of target memory
@param[in] MemoryCacheType the cache type of target memory
@param[in] ValidMtrrAddressMask the MTRR address mask
**/
VOID
EfiProgramMtrr (
IN UINTN MtrrNumber,
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,
IN UINT64 ValidMtrrAddressMask
)
{
UINT64 TempQword;
UINT64 OldMtrr;
if (MemoryLength == 0) {
return;
}
EfiDisableCacheMtrr (&OldMtrr);
//
// MTRR Physical Base
//
TempQword = (MemoryAddress & ValidMtrrAddressMask) | MemoryCacheType;
AsmWriteMsr64 (MtrrNumber, TempQword);
//
// MTRR Physical Mask
//
TempQword = ~(MemoryLength - 1);
AsmWriteMsr64 (MtrrNumber + 1, (TempQword & ValidMtrrAddressMask) | B_EFI_MSR_CACHE_MTRR_VALID);
EfiRecoverCacheMtrr (TRUE, OldMtrr);
}
/**
Calculate the maximum value which is a power of 2, but less the MemoryLength.
@param[in] MemoryAddress Memory address.
@param[in] MemoryLength The number to pass in.
@return The maximum value which is align to power of 2 and less the MemoryLength
**/
UINT64
Power2MaxMemory (
IN UINT64 MemoryAddress,
IN UINT64 MemoryLength
)
{
UINT64 Result;
if (MemoryLength == 0) {
return EFI_INVALID_PARAMETER;
}
//
// Compute inital power of 2 size to return
//
Result = GetPowerOfTwo64(MemoryLength);
//
// Special case base of 0 as all ranges are valid
//
if (MemoryAddress == 0) {
return Result;
}
//
// Loop till a value that can be mapped to this base address is found
//
while (CheckMtrrAlignment (MemoryAddress, Result) != 0) {
//
// Need to try the next smaller power of 2
//
Result = RShiftU64 (Result, 1);
}
return Result;
}
/**
Return MTRR alignment requirement for base address and size.
@param[in] BaseAddress Base address.
@param[in] Size Size.
@retval Zero Alligned.
@retval Non-Zero Not alligned.
**/
UINT32
CheckMtrrAlignment (
IN UINT64 BaseAddress,
IN UINT64 Size
)
{
UINT32 ShiftedBase;
UINT32 ShiftedSize;
//
// Shift base and size right 12 bits to allow for larger memory sizes. The
// MTRRs do not use the first 12 bits so this is safe for now. Only supports
// up to 52 bits of physical address space.
//
ShiftedBase = (UINT32) RShiftU64 (BaseAddress, 12);
ShiftedSize = (UINT32) RShiftU64 (Size, 12);
//
// Return the results to the caller of the MOD
//
return ShiftedBase % ShiftedSize;
}
/**
Programs fixed MTRRs registers.
@param[in] MemoryCacheType The memory type to set.
@param[in] Base The base address of memory range.
@param[in] Length The length of memory range.
@retval RETURN_SUCCESS The cache type was updated successfully
@retval RETURN_UNSUPPORTED The requested range or cache type was invalid
for the fixed MTRRs.
**/
EFI_STATUS
ProgramFixedMtrr (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,
IN UINT64 *Base,
IN UINT64 *Len
)
{
UINT32 MsrNum;
UINT32 ByteShift;
UINT64 TempQword;
UINT64 OrMask;
UINT64 ClearMask;
TempQword = 0;
OrMask = 0;
ClearMask = 0;
for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) {
if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) &&
(*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length))) {
break;
}
}
if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) {
return EFI_DEVICE_ERROR;
}
//
// We found the fixed MTRR to be programmed
//
for (ByteShift=0; ByteShift < 8; ByteShift++) {
if ( *Base == (mFixedMtrrTable[MsrNum].BaseAddress + ByteShift * mFixedMtrrTable[MsrNum].Length)) {
break;
}
}
if (ByteShift == 8 ) {
return EFI_DEVICE_ERROR;
}
for (; ((ByteShift<8) && (*Len >= mFixedMtrrTable[MsrNum].Length));ByteShift++) {
OrMask |= LShiftU64((UINT64) MemoryCacheType, (UINT32) (ByteShift* 8));
ClearMask |= LShiftU64((UINT64) 0xFF, (UINT32) (ByteShift * 8));
*Len -= mFixedMtrrTable[MsrNum].Length;
*Base += mFixedMtrrTable[MsrNum].Length;
}
TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask;
AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword);
return EFI_SUCCESS;
}
/**
Check if there is a valid variable MTRR that overlaps the given range.
@param[in] Start Base Address of the range to check.
@param[in] End End address of the range to check.
@retval TRUE Mtrr overlap.
@retval FALSE Mtrr not overlap.
**/
BOOLEAN
CheckMtrrOverlap (
IN EFI_PHYSICAL_ADDRESS Start,
IN EFI_PHYSICAL_ADDRESS End
)
{
return FALSE;
}
/**
Given the memory range and cache type, programs the MTRRs.
@param[in] MemoryAddress Base Address of Memory to program MTRR.
@param[in] MemoryLength Length of Memory to program MTRR.
@param[in] MemoryCacheType Cache Type.
@retval EFI_SUCCESS Mtrr are set successfully.
@retval EFI_LOAD_ERROR No empty MTRRs to use.
@retval EFI_INVALID_PARAMETER The input parameter is not valid.
@retval others An error occurs when setting MTTR.
**/
EFI_STATUS
EFIAPI
SetCacheAttributes (
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
)
{
EFI_STATUS Status;
UINT32 MsrNum, MsrNumEnd;
UINT64 TempQword;
UINT32 LastVariableMtrrForBios;
UINT64 OldMtrr;
UINT32 UsedMsrNum;
EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;
UINT64 ValidMtrrAddressMask;
UINT32 Cpuid_RegEax;
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL);
if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL);
ValidMtrrAddressMask = (LShiftU64((UINT64) 1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);
} else {
ValidMtrrAddressMask = (LShiftU64((UINT64) 1, 36) - 1) & (~(UINT64)0x0FFF);
}
//
// Check for invalid parameter
//
if ((MemoryAddress & ~ValidMtrrAddressMask) != 0 || (MemoryLength & ~ValidMtrrAddressMask) != 0) {
return EFI_INVALID_PARAMETER;
}
if (MemoryLength == 0) {
return EFI_INVALID_PARAMETER;
}
switch (MemoryCacheType) {
case EFI_CACHE_UNCACHEABLE:
case EFI_CACHE_WRITECOMBINING:
case EFI_CACHE_WRITETHROUGH:
case EFI_CACHE_WRITEPROTECTED:
case EFI_CACHE_WRITEBACK:
break;
default:
return EFI_INVALID_PARAMETER;
}
//
// Check if Fixed MTRR
//
if ((MemoryAddress + MemoryLength) <= (1 << 20)) {
Status = EFI_SUCCESS;
EfiDisableCacheMtrr (&OldMtrr);
while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) {
Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength);
}
EfiRecoverCacheMtrr (TRUE, OldMtrr);
return Status;
}
//
// Search if the range attribute has been set before
//
Status = SearchForExactMtrr(
MemoryAddress,
MemoryLength,
ValidMtrrAddressMask,
&UsedMsrNum,
&UsedMemoryCacheType
);
if (!EFI_ERROR(Status)) {
//
// Compare if it has the same type as current setting
//
if (UsedMemoryCacheType == MemoryCacheType) {
return EFI_SUCCESS;
} else {
//
// Different type
//
//
// Check if the set type is the same as Default Type
//
if (IsDefaultType(MemoryCacheType)) {
//
// Clear the MTRR
//
AsmWriteMsr64(UsedMsrNum, 0);
AsmWriteMsr64(UsedMsrNum + 1, 0);
return EFI_SUCCESS;
} else {
//
// Modify the MTRR type
//
EfiProgramMtrr(UsedMsrNum,
MemoryAddress,
MemoryLength,
MemoryCacheType,
ValidMtrrAddressMask
);
return EFI_SUCCESS;
}
}
}
#if 0
//
// @bug - Need to create memory map so that when checking for overlap we
// can determine if an overlap exists based on all caching requests.
//
// Don't waste a variable MTRR if the caching attrib is same as default in MTRR_DEF_TYPE
//
if (MemoryCacheType == (AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) {
if (!CheckMtrrOverlap (MemoryAddress, MemoryAddress+MemoryLength-1)) {
return EFI_SUCCESS;
}
}
#endif
//
// Find first unused MTRR
//
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {
if ((AsmReadMsr64(MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {
break;
}
}
//
// Reserve 1 MTRR pair for OS.
//
LastVariableMtrrForBios = MsrNumEnd - 1 - (EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2);
if (MsrNum > LastVariableMtrrForBios) {
return EFI_LOAD_ERROR;
}
//
// Special case for 1 MB base address
//
if (MemoryAddress == BASE_1MB) {
MemoryAddress = 0;
}
//
// Program MTRRs
//
TempQword = MemoryLength;
if (TempQword == Power2MaxMemory(MemoryAddress, TempQword)) {
EfiProgramMtrr(MsrNum,
MemoryAddress,
MemoryLength,
MemoryCacheType,
ValidMtrrAddressMask
);
} else {
//
// Fill in MTRRs with values. Direction can not be checked for this method
// as we are using WB as the default cache type and only setting areas to UC.
//
do {
//
// Do boundary check so we don't go past last MTRR register
// for BIOS use. Leave one MTRR pair for OS use.
//
if (MsrNum > LastVariableMtrrForBios) {
return EFI_LOAD_ERROR;
}
//
// Set next power of 2 region
//
MemoryLength = Power2MaxMemory(MemoryAddress, TempQword);
EfiProgramMtrr(MsrNum,
MemoryAddress,
MemoryLength,
MemoryCacheType,
ValidMtrrAddressMask
);
MemoryAddress += MemoryLength;
TempQword -= MemoryLength;
MsrNum += 2;
} while (TempQword != 0);
}
return EFI_SUCCESS;
}
/**
Reset all the MTRRs to a known state.
@retval EFI_SUCCESS All MTRRs have been reset successfully.
**/
EFI_STATUS
EFIAPI
ResetCacheAttributes (
VOID
)
{
UINT32 MsrNum, MsrNumEnd;
UINT16 Index;
UINT64 OldMtrr;
UINT64 CacheType;
BOOLEAN DisableCar;
Index = 0;
DisableCar = TRUE;
//
// Determine default cache type
//
CacheType = EFI_CACHE_UNCACHEABLE;
//
// Set default cache type
//
AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);
//
// Disable CAR
//
DisableCacheAsRam (DisableCar);
EfiDisableCacheMtrr (&OldMtrr);
//
// Reset Fixed MTRRs
//
for (Index = 0; Index < V_EFI_FIXED_MTRR_NUMBER; Index++) {
AsmWriteMsr64 (mFixedMtrrTable[Index].Msr, 0);
}
//
// Reset Variable MTRRs
//
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum++) {
AsmWriteMsr64 (MsrNum, 0);
}
//
// Enable Fixed and Variable MTRRs
//
EfiRecoverCacheMtrr (TRUE, OldMtrr);
return EFI_SUCCESS;
}
/**
Search the memory cache type for specific memory from MTRR.
@param[in] MemoryAddress the address of target memory
@param[in] MemoryLength the length of target memory
@param[in] ValidMtrrAddressMask the MTRR address mask
@param[out] UsedMsrNum the used MSR number
@param[out] UsedMemoryCacheType the cache type for the target memory
@retval EFI_SUCCESS The memory is found in MTRR and cache type is returned
@retval EFI_NOT_FOUND The memory is not found in MTRR
**/
EFI_STATUS
SearchForExactMtrr (
IN EFI_PHYSICAL_ADDRESS MemoryAddress,
IN UINT64 MemoryLength,
IN UINT64 ValidMtrrAddressMask,
OUT UINT32 *UsedMsrNum,
OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType
)
{
UINT32 MsrNum, MsrNumEnd;
UINT64 TempQword;
if (MemoryLength == 0) {
return EFI_INVALID_PARAMETER;
}
MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {
TempQword = AsmReadMsr64(MsrNum+1);
if ((TempQword & B_EFI_MSR_CACHE_MTRR_VALID) == 0) {
continue;
}
if ((TempQword & ValidMtrrAddressMask) != ((~(MemoryLength - 1)) & ValidMtrrAddressMask)) {
continue;
}
TempQword = AsmReadMsr64 (MsrNum);
if ((TempQword & ValidMtrrAddressMask) != (MemoryAddress & ValidMtrrAddressMask)) {
continue;
}
*UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE)(TempQword & B_EFI_MSR_CACHE_MEMORY_TYPE);
*UsedMsrNum = MsrNum;
return EFI_SUCCESS;
}
return EFI_NOT_FOUND;
}
/**
Check if CacheType match current default setting.
@param[in] MemoryCacheType input cache type to be checked.
@retval TRUE MemoryCacheType is default MTRR setting.
@retval TRUE MemoryCacheType is NOT default MTRR setting.
**/
BOOLEAN
IsDefaultType (
IN EFI_MEMORY_CACHE_TYPE MemoryCacheType
)
{
if ((AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {
return FALSE;
}
return TRUE;
}

53
IntelFspPkg/Library/BaseCacheLib/CacheLibInternal.h
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@ -1,53 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _CACHE_LIB_INTERNAL_H_
#define _CACHE_LIB_INTERNAL_H_
#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200
#define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F
#define V_EFI_FIXED_MTRR_NUMBER 11
#define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250
#define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258
#define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259
#define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268
#define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269
#define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
#define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
#define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
#define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
#define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
#define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF
#define B_EFI_MSR_CACHE_MTRR_VALID BIT11
#define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
#define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10
#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0)
#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
#define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000
#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
// Leave one MTRR pairs for OS use
#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1
#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \
(EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2)
#define EFI_MSR_IA32_MTRR_CAP 0x000000FE
#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12
#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10
#define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
#define CPUID_EXTENDED_FUNCTION 0x80000000
#endif

29
IntelFspPkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf
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@ -1,29 +0,0 @@
## @file
# Debug device library instance that retrieves the current enabling state for
# the platform debug output device.
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseDebugDeviceLibNull
FILE_GUID = 455D16DC-E3AF-4b5f-A9AD-A4BC198085BD
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugDeviceLib
#
# VALID_ARCHITECTURES = IA32
#
[Sources]
DebugDeviceLibNull.c
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec

25
IntelFspPkg/Library/BaseDebugDeviceLibNull/DebugDeviceLibNull.c
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@ -1,25 +0,0 @@
/** @file
Debug device library instance that retrieves the current enabling state for
the platform debug output device.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
/**
Returns the debug print device enable state.
@return Debug print device enable state.
**/
UINT8
EFIAPI
GetDebugPrintDeviceEnable (
VOID
)
{
return 1;
}

32
IntelFspPkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
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@ -1,32 +0,0 @@
## @file
# Instance of FspCommonLib
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseFspCommonLib
FILE_GUID = 54607F66-D728-448e-A282-49E0404A557F
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = FspCommonLib
[Sources]
FspCommonLib.c
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
BaseMemoryLib
[Pcd]
gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES
[FixedPcd]
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES

477
IntelFspPkg/Library/BaseFspCommonLib/FspCommonLib.c
View File

@ -1,477 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <FspGlobalData.h>
#include <FspApi.h>
#pragma pack(1)
//
// Cont Func Parameter 2 +0x3C
// Cont Func Parameter 1 +0x38
//
// API Parameter +0x34
// API return address +0x30
//
// push FspInfoHeader +0x2C
// pushfd +0x28
// cli
// pushad +0x24
// sub esp, 8 +0x00
// sidt fword ptr [esp]
//
typedef struct {
UINT16 IdtrLimit;
UINT32 IdtrBase;
UINT16 Reserved;
UINT32 Edi;
UINT32 Esi;
UINT32 Ebp;
UINT32 Esp;
UINT32 Ebx;
UINT32 Edx;
UINT32 Ecx;
UINT32 Eax;
UINT16 Flags[2];
UINT32 FspInfoHeader;
UINT32 ApiRet;
UINT32 ApiParam;
} CONTEXT_STACK;
#define CONTEXT_STACK_OFFSET(x) (UINT32)&((CONTEXT_STACK *)(UINTN)0)->x
#pragma pack()
/**
This function sets the FSP global data pointer.
@param[in] FspData Fsp global data pointer.
**/
VOID
EFIAPI
SetFspGlobalDataPointer (
IN FSP_GLOBAL_DATA *FspData
)
{
ASSERT (FspData != NULL);
*((volatile UINT32 *)(UINTN)PcdGet32(PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData;
}
/**
This function gets the FSP global data pointer.
**/
FSP_GLOBAL_DATA *
EFIAPI
GetFspGlobalDataPointer (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = *(FSP_GLOBAL_DATA **)(UINTN)PcdGet32(PcdGlobalDataPointerAddress);
return FspData;
}
/**
This function gets back the FSP API parameter passed by the bootlaoder.
@retval ApiParameter FSP API parameter passed by the bootlaoder.
**/
UINT32
EFIAPI
GetFspApiParameter (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam));
}
/**
This function sets the FSP API parameter in the stack.
@param[in] Value New parameter value.
**/
VOID
EFIAPI
SetFspApiParameter (
IN UINT32 Value
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam)) = Value;
}
/**
This function sets the FSP continuation function parameters in the stack.
@param[in] Value New parameter value to set.
@param[in] Index Parameter index.
**/
VOID
EFIAPI
SetFspContinuationFuncParameter (
IN UINT32 Value,
IN UINT32 Index
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam) + (Index + 1) * sizeof(UINT32)) = Value;
}
/**
This function changes the BootLoader return address in stack.
@param[in] ReturnAddress Address to return.
**/
VOID
EFIAPI
SetFspApiReturnAddress (
IN UINT32 ReturnAddress
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiRet)) = ReturnAddress;
}
/**
This function set the API status code returned to the BootLoader.
@param[in] ReturnStatus Status code to return.
**/
VOID
EFIAPI
SetFspApiReturnStatus (
IN UINT32 ReturnStatus
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(Eax)) = ReturnStatus;
}
/**
This function sets the context switching stack to a new stack frame.
@param[in] NewStackTop New core stack to be set.
**/
VOID
EFIAPI
SetFspCoreStackPointer (
IN VOID *NewStackTop
)
{
FSP_GLOBAL_DATA *FspData;
UINT32 *OldStack;
UINT32 *NewStack;
UINT32 StackContextLen;
FspData = GetFspGlobalDataPointer ();
StackContextLen = sizeof(CONTEXT_STACK) / sizeof(UINT32);
//
// Reserve space for the ContinuationFunc two parameters
//
OldStack = (UINT32 *)FspData->CoreStack;
NewStack = (UINT32 *)NewStackTop - StackContextLen - 2;
FspData->CoreStack = (UINT32)NewStack;
while (StackContextLen-- != 0) {
*NewStack++ = *OldStack++;
}
}
/**
This function sets the platform specific data pointer.
@param[in] PlatformData Fsp platform specific data pointer.
**/
VOID
EFIAPI
SetFspPlatformDataPointer (
IN VOID *PlatformData
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
FspData->PlatformData.DataPtr = PlatformData;
}
/**
This function gets the platform specific data pointer.
@param[in] PlatformData Fsp platform specific data pointer.
**/
VOID *
EFIAPI
GetFspPlatformDataPointer (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
return FspData->PlatformData.DataPtr;
}
/**
This function sets the UPD data pointer.
@param[in] UpdDataRgnPtr UPD data pointer.
**/
VOID
EFIAPI
SetFspUpdDataPointer (
IN VOID *UpdDataRgnPtr
)
{
FSP_GLOBAL_DATA *FspData;
//
// Get the Fsp Global Data Pointer
//
FspData = GetFspGlobalDataPointer ();
//
// Set the UPD pointer.
//
FspData->UpdDataRgnPtr = UpdDataRgnPtr;
}
/**
This function gets the UPD data pointer.
@return UpdDataRgnPtr UPD data pointer.
**/
VOID *
EFIAPI
GetFspUpdDataPointer (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
return FspData->UpdDataRgnPtr;
}
/**
This function sets the memory init UPD data pointer.
@param[in] MemoryInitUpdPtr memory init UPD data pointer.
**/
VOID
EFIAPI
SetFspMemoryInitUpdDataPointer (
IN VOID *MemoryInitUpdPtr
)
{
FSP_GLOBAL_DATA *FspData;
//
// Get the Fsp Global Data Pointer
//
FspData = GetFspGlobalDataPointer ();
//
// Set the memory init UPD pointer.
//
FspData->MemoryInitUpdPtr = MemoryInitUpdPtr;
}
/**
This function gets the memory init UPD data pointer.
@return memory init UPD data pointer.
**/
VOID *
EFIAPI
GetFspMemoryInitUpdDataPointer (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
return FspData->MemoryInitUpdPtr;
}
/**
This function sets the silicon init UPD data pointer.
@param[in] SiliconInitUpdPtr silicon init UPD data pointer.
**/
VOID
EFIAPI
SetFspSiliconInitUpdDataPointer (
IN VOID *SiliconInitUpdPtr
)
{
FSP_GLOBAL_DATA *FspData;
//
// Get the Fsp Global Data Pointer
//
FspData = GetFspGlobalDataPointer ();
//
// Set the silicon init UPD data pointer.
//
FspData->SiliconInitUpdPtr = SiliconInitUpdPtr;
}
/**
This function gets the silicon init UPD data pointer.
@return silicon init UPD data pointer.
**/
VOID *
EFIAPI
GetFspSiliconInitUpdDataPointer (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
return FspData->SiliconInitUpdPtr;
}
/**
Set FSP measurement point timestamp.
@param[in] Id Measurement point ID.
@return performance timestamp.
**/
UINT64
EFIAPI
SetFspMeasurePoint (
IN UINT8 Id
)
{
FSP_GLOBAL_DATA *FspData;
//
// Bit [55: 0] will be the timestamp
// Bit [63:56] will be the ID
//
FspData = GetFspGlobalDataPointer ();
if (FspData->PerfIdx < sizeof(FspData->PerfData) / sizeof(FspData->PerfData[0])) {
FspData->PerfData[FspData->PerfIdx] = AsmReadTsc ();
((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id;
}
return FspData->PerfData[(FspData->PerfIdx)++];
}
/**
This function gets the FSP info header pointer.
@retval FspInfoHeader FSP info header pointer
**/
FSP_INFO_HEADER *
EFIAPI
GetFspInfoHeader (
VOID
)
{
return GetFspGlobalDataPointer()->FspInfoHeader;
}
/**
This function gets the FSP info header pointer using the API stack context.
@retval FspInfoHeader FSP info header pointer using the API stack context
**/
FSP_INFO_HEADER *
EFIAPI
GetFspInfoHeaderFromApiContext (
VOID
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
return (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(FspInfoHeader)));
}
/**
This function gets the VPD data pointer.
@return VpdDataRgnPtr VPD data pointer.
**/
VOID *
EFIAPI
GetFspVpdDataPointer (
VOID
)
{
FSP_INFO_HEADER *FspInfoHeader;
FspInfoHeader = GetFspInfoHeader ();
return (VOID *)(FspInfoHeader->ImageBase + FspInfoHeader->CfgRegionOffset);
}
/**
This function gets FSP API calling mode.
@retval API calling mode
**/
UINT8
EFIAPI
GetFspApiCallingMode (
VOID
)
{
return GetFspGlobalDataPointer()->ApiMode;
}
/**
This function sets FSP API calling mode.
@param[in] Mode API calling mode
**/
VOID
EFIAPI
SetFspApiCallingMode (
UINT8 Mode
)
{
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
FspData->ApiMode = Mode;
}

46
IntelFspPkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
View File

@ -1,46 +0,0 @@
## @file
# Instance of BaseFspDebugLib
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseFspDebugLibSerialPort
FILE_GUID = 9D52E46E-F07E-44e8-9A90-F8576C91C211
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugLib
#
# VALID_ARCHITECTURES = IA32
#
[Sources]
DebugLib.c
[Sources.Ia32]
Ia32/FspDebug.asm | MSFT
Ia32/FspDebug.s | GCC
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
SerialPortLib
BaseMemoryLib
PcdLib
PrintLib
BaseLib
DebugDeviceLib
DebugPrintErrorLevelLib
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue ## CONSUMES
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask ## CONSUMES
gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel ## CONSUMES

415
IntelFspPkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
View File

@ -1,415 +0,0 @@
/** @file
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Library/PrintLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/SerialPortLib.h>
#include <Library/DebugDeviceLib.h>
#include <Library/DebugPrintErrorLevelLib.h>
//
// Define the maximum debug and assert message length that this library supports
//
#define MAX_DEBUG_MESSAGE_LENGTH 0x100
CONST CHAR8 *mHexTable = "0123456789ABCDEF";
//
// VA_LIST can not initialize to NULL for all compiler, so we use this to
// indicate a null VA_LIST
//
VA_LIST mVaListNull;
/**
Get stack frame pointer of function call.
@return StackFramePointer stack frame pointer of function call.
**/
UINT32 *
EFIAPI
GetStackFramePointer (
VOID
);
/**
Prints a debug message to the debug output device if the specified error level is enabled.
If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
GetDebugPrintErrorLevel (), then print the message specified by Format and the
associated variable argument list to the debug output device.
If Format is NULL, then ASSERT().
@param ErrorLevel The error level of the debug message.
@param Format Format string for the debug message to print.
@param ... Variable argument list whose contents are accessed
based on the format string specified by Format.
**/
VOID
EFIAPI
DebugPrint (
IN UINTN ErrorLevel,
IN CONST CHAR8 *Format,
...
)
{
VA_LIST Marker;
VA_START (Marker, Format);
DebugVPrint (ErrorLevel, Format, Marker);
VA_END (Marker);
}
/**
Prints a debug message to the debug output device if the specified
error level is enabled base on Null-terminated format string and a
VA_LIST argument list or a BASE_LIST argument list.
If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
GetDebugPrintErrorLevel (), then print the message specified by Format and
the associated variable argument list to the debug output device.
If Format is NULL, then ASSERT().
@param ErrorLevel The error level of the debug message.
@param Format Format string for the debug message to print.
@param VaListMarker VA_LIST marker for the variable argument list.
@param BaseListMarker BASE_LIST marker for the variable argument list.
**/
VOID
DebugPrintMarker (
IN UINTN ErrorLevel,
IN CONST CHAR8 *Format,
IN VA_LIST VaListMarker,
IN BASE_LIST BaseListMarker
)
{
CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
//
// If Format is NULL, then ASSERT().
//
if (!GetDebugPrintDeviceEnable ()) {
return;
}
//
// Check driver debug mask value and global mask
//
if ((ErrorLevel & GetDebugPrintErrorLevel ()) == 0) {
return;
}
//
// If Format is NULL, then ASSERT().
//
ASSERT (Format != NULL);
//
// Convert the DEBUG() message to an ASCII String
//
if (BaseListMarker == NULL) {
AsciiVSPrint (Buffer, sizeof (Buffer), Format, VaListMarker);
} else {
AsciiBSPrint (Buffer, sizeof (Buffer), Format, BaseListMarker);
}
//
// Send the print string to a Serial Port
//
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
}
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
GetDebugPrintErrorLevel (), then print the message specified by Format and
the associated variable argument list to the debug output device.
If Format is NULL, then ASSERT().
@param ErrorLevel The error level of the debug message.
@param Format Format string for the debug message to print.
@param VaListMarker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
DebugVPrint (
IN UINTN ErrorLevel,
IN CONST CHAR8 *Format,
IN VA_LIST VaListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);
}
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
This function use BASE_LIST which would provide a more compatible
service than VA_LIST.
If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
GetDebugPrintErrorLevel (), then print the message specified by Format and
the associated variable argument list to the debug output device.
If Format is NULL, then ASSERT().
@param ErrorLevel The error level of the debug message.
@param Format Format string for the debug message to print.
@param BaseListMarker BASE_LIST marker for the variable argument list.
**/
VOID
EFIAPI
DebugBPrint (
IN UINTN ErrorLevel,
IN CONST CHAR8 *Format,
IN BASE_LIST BaseListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);
}
/**
Convert an UINT32 value into HEX string sepcified by Buffer.
@param Value The HEX value to convert to string
@param Buffer The pointer to the target buffer to be filled with HEX string
**/
VOID
FillHex (
UINT32 Value,
CHAR8 *Buffer
)
{
INTN Idx;
for (Idx = 7; Idx >= 0; Idx--) {
Buffer[Idx] = mHexTable[Value & 0x0F];
Value >>= 4;
}
}
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
CpuDeadLoop() is called. If neither of these bits are set, then this function
returns immediately after the message is printed to the debug output device.
DebugAssert() must actively prevent recursion. If DebugAssert() is called while
processing another DebugAssert(), then DebugAssert() must return immediately.
If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
If Description is NULL, then a <Description> string of "(NULL) Description" is printed.
**/
VOID
DebugAssertInternal (
VOID
)
{
CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
UINT32 *Frame;
Frame = (UINT32 *)GetStackFramePointer ();
//
// Generate the ASSERT() message in Ascii format
//
AsciiStrnCpyS (
Buffer,
sizeof(Buffer) / sizeof(CHAR8),
"-> EBP:0x00000000 EIP:0x00000000\n",
sizeof(Buffer) / sizeof(CHAR8) - 1
);
SerialPortWrite ((UINT8 *)"ASSERT DUMP:\n", 13);
while (Frame != NULL) {
FillHex ((UINT32)Frame, Buffer + 9);
FillHex (Frame[1], Buffer + 9 + 8 + 8);
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
if ((Frame[0] > (UINT32)Frame) && (Frame[0] < (UINT32)Frame + 0x00100000)) {
Frame = (UINT32 *)Frame[0];
} else {
Frame = NULL;
}
}
//
// Dead loop
//
CpuDeadLoop ();
}
/**
Prints an assert message containing a filename, line number, and description.
This may be followed by a breakpoint or a dead loop.
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
CpuDeadLoop() is called. If neither of these bits are set, then this function
returns immediately after the message is printed to the debug output device.
DebugAssert() must actively prevent recursion. If DebugAssert() is called while
processing another DebugAssert(), then DebugAssert() must return immediately.
If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
If Description is NULL, then a <Description> string of "(NULL) Description" is printed.
@param FileName The pointer to the name of the source file that generated the assert condition.
@param LineNumber The line number in the source file that generated the assert condition
@param Description The pointer to the description of the assert condition.
**/
VOID
EFIAPI
DebugAssert (
IN CONST CHAR8 *FileName,
IN UINTN LineNumber,
IN CONST CHAR8 *Description
)
{
DebugAssertInternal ();
}
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
This function fills Length bytes of Buffer with the value specified by
PcdDebugClearMemoryValue, and returns Buffer.
If Buffer is NULL, then ASSERT().
If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
@param Buffer The pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
@param Length The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
@return Buffer The pointer to the target buffer filled with PcdDebugClearMemoryValue.
**/
VOID *
EFIAPI
DebugClearMemory (
OUT VOID *Buffer,
IN UINTN Length
)
{
return Buffer;
}
/**
Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugAssertEnabled (
VOID
)
{
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
}
/**
Returns TRUE if DEBUG() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugPrintEnabled (
VOID
)
{
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
}
/**
Returns TRUE if DEBUG_CODE() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugCodeEnabled (
VOID
)
{
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
}
/**
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
**/
BOOLEAN
EFIAPI
DebugClearMemoryEnabled (
VOID
)
{
return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
}
/**
Returns TRUE if any one of the bit is set both in ErrorLevel and PcdFixedDebugPrintErrorLevel.
This function compares the bit mask of ErrorLevel and PcdFixedDebugPrintErrorLevel.
@retval TRUE Current ErrorLevel is supported.
@retval FALSE Current ErrorLevel is not supported.
**/
BOOLEAN
EFIAPI
DebugPrintLevelEnabled (
IN CONST UINTN ErrorLevel
)
{
return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);
}

28
IntelFspPkg/Library/BaseFspDebugLibSerialPort/Ia32/FspDebug.asm
View File

@ -1,28 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; FSP Debug functions
;
;------------------------------------------------------------------------------
.386
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT32 *
; EFIAPI
; GetStackFramePointer (
; VOID
; );
;------------------------------------------------------------------------------
GetStackFramePointer PROC PUBLIC
mov eax, ebp
ret
GetStackFramePointer ENDP
END

24
IntelFspPkg/Library/BaseFspDebugLibSerialPort/Ia32/FspDebug.s
View File

@ -1,24 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# FSP Debug functions
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# UINT32 *
# EFIAPI
# GetStackFramePointer (
# VOID
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(GetStackFramePointer)
ASM_PFX(GetStackFramePointer):
mov %ebp, %eax
ret

41
IntelFspPkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
View File

@ -1,41 +0,0 @@
## @file
# Instance of FspPlatformLib
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseFspPlatformLib
FILE_GUID = 7DECCDAF-361F-4ec1-9714-260BAAF6F384
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = FspPlatformLib
[Sources]
FspPlatformMemory.c
FspPlatformNotify.c
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
BaseMemoryLib
MemoryAllocationLib
[Pcd]
gIntelFspPkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
[Guids]
gFspBootLoaderTemporaryMemoryGuid ## PRODUCES ## HOB
[FixedPcd]
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES

173
IntelFspPkg/Library/BaseFspPlatformLib/FspPlatformMemory.c
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@ -1,173 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/HobLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/FspCommonLib.h>
#include <Guid/GuidHobFsp.h>
#include <FspGlobalData.h>
#include <FspApi.h>
/**
Get system memory from HOB.
@param[in,out] LowMemoryLength less than 4G memory length
@param[in,out] HighMemoryLength greater than 4G memory length
**/
VOID
EFIAPI
FspGetSystemMemorySize (
IN OUT UINT64 *LowMemoryLength,
IN OUT UINT64 *HighMemoryLength
)
{
EFI_PEI_HOB_POINTERS Hob;
*HighMemoryLength = 0;
*LowMemoryLength = SIZE_1MB;
//
// Get the HOB list for processing
//
Hob.Raw = GetHobList ();
//
// Collect memory ranges
//
while (!END_OF_HOB_LIST (Hob)) {
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
//
// Need memory above 1MB to be collected here
//
if (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB &&
Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) BASE_4GB) {
*LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);
} else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) BASE_4GB) {
*HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);
}
}
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
}
/**
Migrate BootLoader data before destroying CAR.
**/
VOID
EFIAPI
FspMigrateTemporaryMemory (
VOID
)
{
FSP_INIT_RT_COMMON_BUFFER *FspInitRtBuffer;
UINT32 BootLoaderTempRamStart;
UINT32 BootLoaderTempRamEnd;
UINT32 BootLoaderTempRamSize;
UINT32 OffsetGap;
UINT32 FspParamPtr;
FSP_INIT_PARAMS *FspInitParams;
UINT32 *NewStackTop;
VOID *BootLoaderTempRamHob;
UINT32 UpdDataRgnPtr;
UINT32 MemoryInitUpdPtr;
UINT32 SiliconInitUpdPtr;
VOID *PlatformDataPtr;
UINT8 ApiMode;
ApiMode = GetFspApiCallingMode ();
//
// Get the temporary memory range used by the BootLoader
//
BootLoaderTempRamStart = PcdGet32(PcdTemporaryRamBase);
BootLoaderTempRamSize = PcdGet32(PcdTemporaryRamSize) - PcdGet32(PcdFspTemporaryRamSize);
BootLoaderTempRamEnd = BootLoaderTempRamStart + BootLoaderTempRamSize;
//
// Build a Boot Loader Temporary Memory GUID HOB
//
if (ApiMode == 0) {
BootLoaderTempRamHob = BuildGuidHob (&gFspBootLoaderTemporaryMemoryGuid, BootLoaderTempRamSize);
} else {
BootLoaderTempRamHob = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES (BootLoaderTempRamSize));
}
ASSERT(BootLoaderTempRamHob != NULL);
CopyMem (BootLoaderTempRamHob, (VOID *)BootLoaderTempRamStart, BootLoaderTempRamSize);
OffsetGap = (UINT32)BootLoaderTempRamHob - BootLoaderTempRamStart;
//
// Set a new stack frame for the continuation function
//
if (ApiMode == 0) {
FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();
FspInitRtBuffer = (FSP_INIT_RT_COMMON_BUFFER *)FspInitParams->RtBufferPtr;
NewStackTop = (UINT32 *)FspInitRtBuffer->StackTop - 1;
SetFspCoreStackPointer (NewStackTop);
}
//
// Fix the FspInit Parameter Pointers to the new location.
//
FspParamPtr = GetFspApiParameter ();
if (FspParamPtr >= BootLoaderTempRamStart && FspParamPtr < BootLoaderTempRamEnd) {
SetFspApiParameter(FspParamPtr + OffsetGap);
}
FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();
if ((UINT32)(FspInitParams->RtBufferPtr) >= BootLoaderTempRamStart &&
(UINT32)(FspInitParams->RtBufferPtr) < BootLoaderTempRamEnd) {
FspInitParams->RtBufferPtr = (VOID *)((UINT32)(FspInitParams->RtBufferPtr) + OffsetGap);
}
if ((UINT32)(FspInitParams->NvsBufferPtr) >= BootLoaderTempRamStart &&
(UINT32)(FspInitParams->NvsBufferPtr) < BootLoaderTempRamEnd) {
FspInitParams->NvsBufferPtr = (VOID *)((UINT32)(FspInitParams->NvsBufferPtr) + OffsetGap);
}
if ((UINT32)(((FSP_INIT_RT_COMMON_BUFFER *)(FspInitParams->RtBufferPtr))->UpdDataRgnPtr) >= BootLoaderTempRamStart &&
(UINT32)(((FSP_INIT_RT_COMMON_BUFFER *)(FspInitParams->RtBufferPtr))->UpdDataRgnPtr) < BootLoaderTempRamEnd) {
((FSP_INIT_RT_COMMON_BUFFER *)(FspInitParams->RtBufferPtr))->UpdDataRgnPtr = \
(VOID *)((UINT32)(((FSP_INIT_RT_COMMON_BUFFER *)(FspInitParams->RtBufferPtr))->UpdDataRgnPtr) + OffsetGap);
}
//
// Update UPD pointer in FSP Global Data
//
if (ApiMode == 0) {
UpdDataRgnPtr = (UINT32)((UINT32 *)GetFspUpdDataPointer ());
if (UpdDataRgnPtr >= BootLoaderTempRamStart && UpdDataRgnPtr < BootLoaderTempRamEnd) {
MemoryInitUpdPtr = (UINT32)((UINT32 *)GetFspMemoryInitUpdDataPointer ());
SiliconInitUpdPtr = (UINT32)((UINT32 *)GetFspSiliconInitUpdDataPointer ());
SetFspUpdDataPointer ((VOID *)(UpdDataRgnPtr + OffsetGap));
SetFspMemoryInitUpdDataPointer ((VOID *)(MemoryInitUpdPtr + OffsetGap));
SetFspSiliconInitUpdDataPointer ((VOID *)(SiliconInitUpdPtr + OffsetGap));
}
} else {
MemoryInitUpdPtr = (UINT32)((UINT32 *)GetFspMemoryInitUpdDataPointer ());
if (MemoryInitUpdPtr >= BootLoaderTempRamStart && MemoryInitUpdPtr < BootLoaderTempRamEnd) {
SetFspMemoryInitUpdDataPointer ((VOID *)(MemoryInitUpdPtr + OffsetGap));
}
}
//
// Update Platform data pointer in FSP Global Data
//
PlatformDataPtr = GetFspPlatformDataPointer ();
if (((UINT32)PlatformDataPtr >= BootLoaderTempRamStart) &&
((UINT32)PlatformDataPtr < BootLoaderTempRamEnd)) {
SetFspPlatformDataPointer ((UINT8 *)PlatformDataPtr + OffsetGap);
}
}

191
IntelFspPkg/Library/BaseFspPlatformLib/FspPlatformNotify.c
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@ -1,191 +0,0 @@
/** @file
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/PeiServicesLib.h>
#include <Library/PeiServicesTablePointerLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/FspSwitchStackLib.h>
#include <Library/FspCommonLib.h>
#include <Guid/EventGroup.h>
#include <FspApi.h>
#include <Protocol/PciEnumerationComplete.h>
EFI_PEI_PPI_DESCRIPTOR mPeiPostPciEnumerationPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPciEnumerationCompleteProtocolGuid,
NULL
};
EFI_PEI_PPI_DESCRIPTOR mPeiReadyToBootPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiEventReadyToBootGuid,
NULL
};
UINT32 mFspNotifySequence[] = {
EnumInitPhaseAfterPciEnumeration,
EnumInitPhaseReadyToBoot
};
/**
Install FSP notification.
@param[in] NotificationCode FSP notification code
@retval EFI_SUCCESS Notify FSP successfully
@retval EFI_INVALID_PARAMETER NotificationCode is invalid
**/
EFI_STATUS
EFIAPI
FspNotificationHandler (
IN UINT32 NotificationCode
)
{
EFI_STATUS Status;
Status = EFI_SUCCESS;
switch (NotificationCode) {
case EnumInitPhaseAfterPciEnumeration:
//
// Do POST PCI initialization if needed
//
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n"));
PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi);
break;
case EnumInitPhaseReadyToBoot:
//
// Ready To Boot
//
DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n"));
PeiServicesInstallPpi (&mPeiReadyToBootPpi);
break;
default:
Status = EFI_INVALID_PARAMETER;
break;
}
return Status;
}
/**
This function transfer control to the ContinuationFunc passed in by the
BootLoader.
**/
VOID
EFIAPI
FspInitDone (
VOID
)
{
FSP_INIT_PARAMS *FspInitParams;
if (GetFspApiCallingMode() == 0) {
//
// FspInit API is used, so jump into the ContinuationFunc
//
FspInitParams = (FSP_INIT_PARAMS *)GetFspApiParameter ();
//
// Modify the parameters for ContinuationFunc
//
SetFspContinuationFuncParameter(EFI_SUCCESS, 0);
SetFspContinuationFuncParameter((UINT32)GetHobList(), 1);
//
// Modify the return address to ContinuationFunc
//
SetFspApiReturnAddress((UINT32)FspInitParams->ContinuationFunc);
//
// Give control back to the boot loader framework caller after FspInit is done
// It is done throught the continuation function
//
SetFspMeasurePoint (FSP_PERF_ID_API_FSPINIT_EXIT);
} else {
//
// FspMemoryInit API is used, so return directly
//
//
// This is the end of the FspSiliconInit API
// Give control back to the boot loader
//
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - End\n"));
SetFspApiReturnStatus (EFI_SUCCESS);
}
Pei2LoaderSwitchStack();
}
/**
This function handle NotifyPhase API call from the BootLoader.
It gives control back to the BootLoader after it is handled. If the
Notification code is a ReadyToBoot event, this function will return
and FSP continues the remaining execution until it reaches the DxeIpl.
**/
VOID
FspWaitForNotify (
VOID
)
{
EFI_STATUS Status;
UINT32 NotificationValue;
UINT32 NotificationCount;
UINT8 Count;
NotificationCount = 0;
while (NotificationCount < sizeof(mFspNotifySequence) / sizeof(UINT32)) {
Count = (UINT8)((NotificationCount << 1) & 0x07);
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POSTPCI_ENTRY + Count);
NotificationValue = ((NOTIFY_PHASE_PARAMS *)(UINTN)GetFspApiParameter ())->Phase;
DEBUG ((DEBUG_INFO, "FSP Got Notification. Notification Value : 0x%08X\n", NotificationValue));
if (mFspNotifySequence[NotificationCount] != NotificationValue) {
//
// Notify code does not follow the predefined order
//
DEBUG ((DEBUG_INFO, "Unsupported FSP Notification Value\n"));
SetFspApiReturnStatus(EFI_UNSUPPORTED);
} else {
//
// Process Notification and Give control back to the boot loader framework caller
//
Status = FspNotificationHandler (NotificationValue);
DEBUG ((DEBUG_INFO, "FSP Notification Handler Returns : 0x%08X\n", Status));
SetFspApiReturnStatus(Status);
if (!EFI_ERROR(Status)) {
NotificationCount++;
SetFspApiReturnStatus(EFI_SUCCESS);
if (NotificationValue == EnumInitPhaseReadyToBoot) {
break;
}
}
}
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POSTPCI_EXIT + Count);
Pei2LoaderSwitchStack();
}
//
// Control goes back to the PEI Core and it dispatches further PEIMs.
// DXEIPL is the final one to transfer control back to the boot loader.
//
}

38
IntelFspPkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
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@ -1,38 +0,0 @@
## @file
# Instance of BaseFspSwitchStackLib
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseFspSwitchStackLib
FILE_GUID = 8A5EA987-27F9-4ad0-B07C-D61882BFF4FF
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = FspSwitchStackLib
[Sources.IA32]
FspSwitchStackLib.c
[Sources.IA32]
Ia32/Stack.asm | MSFT
Ia32/Stack.s | GCC
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
[LibraryClasses]
BaseLib
IoLib
[FixedPcd]
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES
gIntelFspPkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES

36
IntelFspPkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
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@ -1,36 +0,0 @@
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/FspCommonLib.h>
/**
Switch the current stack to the previous saved stack.
@param[in] NewStack The new stack to be switched.
@return OldStack After switching to the saved stack,
this value will be saved in eax before returning.
**/
UINT32
SwapStack (
IN UINT32 NewStack
)
{
FSP_GLOBAL_DATA *FspData;
UINT32 OldStack;
FspData = GetFspGlobalDataPointer ();
OldStack = FspData->CoreStack;
FspData->CoreStack = NewStack;
return OldStack;
}

71
IntelFspPkg/Library/BaseFspSwitchStackLib/Ia32/Stack.asm
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@ -1,71 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Switch the stack from temporary memory to permenent memory.
;
;------------------------------------------------------------------------------
.586p
.model flat,C
.code
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; Pei2LoaderSwitchStack (
; VOID
; )
;------------------------------------------------------------------------------
EXTERNDEF C MeasurePoint:PROC
Pei2LoaderSwitchStack PROC C PUBLIC
xor eax, eax
jmp FspSwitchStack
Pei2LoaderSwitchStack ENDP
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; Loader2PeiSwitchStack (
; VOID
; )
;------------------------------------------------------------------------------
Loader2PeiSwitchStack PROC C PUBLIC
jmp FspSwitchStack
Loader2PeiSwitchStack ENDP
;------------------------------------------------------------------------------
; UINT32
; EFIAPI
; FspSwitchStack (
; VOID
; )
;------------------------------------------------------------------------------
EXTERNDEF C SwapStack:PROC
FspSwitchStack PROC C PUBLIC
; Save current contexts
push eax
pushfd
cli
pushad
sub esp, 8
sidt fword ptr [esp]
; Load new stack
push esp
call SwapStack
mov esp, eax
; Restore previous contexts
lidt fword ptr [esp]
add esp, 8
popad
popfd
add esp, 4
ret
FspSwitchStack ENDP
END

72
IntelFspPkg/Library/BaseFspSwitchStackLib/Ia32/Stack.s
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@ -1,72 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# Switch the stack from temporary memory to permenent memory.
#
#------------------------------------------------------------------------------
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# Pei2LoaderSwitchStack (
# VOID
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(Pei2LoaderSwitchStack)
ASM_PFX(Pei2LoaderSwitchStack):
xorl %eax, %eax
jmp ASM_PFX(FspSwitchStack)
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# Loader2PeiSwitchStack (
# VOID
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack)
ASM_PFX(Loader2PeiSwitchStack):
jmp ASM_PFX(FspSwitchStack)
#------------------------------------------------------------------------------
# UINT32
# EFIAPI
# FspSwitchStack (
# VOID
# )
#------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(FspSwitchStack)
ASM_PFX(FspSwitchStack):
#
#Save current contexts
#
push %eax
pushf
cli
pusha
sub $0x08, %esp
sidt (%esp)
#
# Load new stack
#
push %esp
call ASM_PFX(SwapStack)
movl %eax, %esp
#
# Restore previous contexts
#
lidt (%esp)
add $0x08,%esp
popa
popf
add $0x04,%esp
ret

177
IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.asm
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@ -1,177 +0,0 @@
;; @file
; This is the code that goes from real-mode to protected mode.
; It consumes the reset vector, configures the stack.
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
;
; Define assembler characteristics
;
.586p
.xmm
.model flat, c
EXTRN TempRamInitApi:NEAR
EXTRN FspInitApi:NEAR
;
; Contrary to the name, this file contains 16 bit code as well.
;
_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
;----------------------------------------------------------------------------
;
; Procedure: _ModuleEntryPoint
;
; Input: None
;
; Output: None
;
; Destroys: Assume all registers
;
; Description:
;
; Transition to non-paged flat-model protected mode from a
; hard-coded GDT that provides exactly two descriptors.
; This is a bare bones transition to protected mode only
; used for a while in PEI and possibly DXE.
;
; After enabling protected mode, a far jump is executed to
; transfer to PEI using the newly loaded GDT.
;
; Return: None
;
;----------------------------------------------------------------------------
align 16
_ModuleEntryPoint PROC C PUBLIC
;
; Load the GDT table in GdtDesc
;
mov esi, OFFSET GdtDesc
db 66h
lgdt fword ptr cs:[si]
;
; Transition to 16 bit protected mode
;
mov eax, cr0 ; Get control register 0
or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
mov cr0, eax ; Activate protected mode
;
; Now we're in 16 bit protected mode
; Set up the selectors for 32 bit protected mode entry
;
mov ax, SYS_DATA_SEL
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Transition to Flat 32 bit protected mode
; The jump to a far pointer causes the transition to 32 bit mode
;
mov esi, offset ProtectedModeEntryLinearAddress
jmp fword ptr cs:[si]
_ModuleEntryPoint ENDP
_TEXT_REALMODE ENDS
.code
;
; Protected mode portion initializes stack, configures cache, and calls C entry point
;
;----------------------------------------------------------------------------
;
; Procedure: ProtectedModeEntryPoint
;
; Input: Executing in 32 Bit Protected (flat) mode
; cs: 0-4GB
; ds: 0-4GB
; es: 0-4GB
; fs: 0-4GB
; gs: 0-4GB
; ss: 0-4GB
;
; Output: This function never returns
;
; Destroys:
; ecx
; edi
; esi
; esp
;
; Description:
; Perform any essential early platform initilaisation
; Setup a stack
;
;----------------------------------------------------------------------------
ProtectedModeEntryPoint PROC NEAR C PUBLIC
;
; Dummy function. Consume 2 API to make sure they can be linked.
;
mov eax, TempRamInitApi
mov eax, FspInitApi
; Should never return
jmp $
ProtectedModeEntryPoint ENDP
;
; ROM-based Global-Descriptor Table for the PEI Phase
;
align 16
PUBLIC BootGdtTable
;
; GDT[0]: 0x00: Null entry, never used.
;
NULL_SEL equ $ - GDT_BASE ; Selector [0]
GDT_BASE:
BootGdtTable DD 0
DD 0
;
; Linear code segment descriptor
;
LINEAR_CODE_SEL equ $ - GDT_BASE ; Selector [0x8]
DW 0FFFFh ; limit 0xFFFF
DW 0 ; base 0
DB 0
DB 09Bh ; present, ring 0, data, expand-up, not-writable
DB 0CFh ; page-granular, 32-bit
DB 0
;
; System data segment descriptor
;
SYS_DATA_SEL equ $ - GDT_BASE ; Selector [0x10]
DW 0FFFFh ; limit 0xFFFF
DW 0 ; base 0
DB 0
DB 093h ; present, ring 0, data, expand-up, not-writable
DB 0CFh ; page-granular, 32-bit
DB 0
GDT_SIZE EQU $ - BootGDTtable ; Size, in bytes
;
; GDT Descriptor
;
GdtDesc: ; GDT descriptor
DW GDT_SIZE - 1 ; GDT limit
DD OFFSET BootGdtTable ; GDT base address
ProtectedModeEntryLinearAddress LABEL FWORD
ProtectedModeEntryLinearOffset LABEL DWORD
DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
DW LINEAR_CODE_SEL
END

165
IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.s
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@ -1,165 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# This is the code that goes from real-mode to protected mode.
# It consumes the reset vector, configures the stack.
#
#------------------------------------------------------------------------------
#
# Contrary to the name, this file contains 16 bit code as well.
#
.text
#----------------------------------------------------------------------------
#
# Procedure: _ModuleEntryPoint
#
# Input: None
#
# Output: None
#
# Destroys: Assume all registers
#
# Description:
#
# Transition to non-paged flat-model protected mode from a
# hard-coded GDT that provides exactly two descriptors.
# This is a bare bones transition to protected mode only
# used for a while in PEI and possibly DXE.
#
# After enabling protected mode, a far jump is executed to
# transfer to PEI using the newly loaded GDT.
#
# Return: None
#
#----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
#
# Load the GDT table in GdtDesc
#
.byte 0x66,0xbe #movl $GdtDesc, %esi
.long GdtDesc
.byte 0x66,0x2e,0x0f,0x01,0x14 #lgdt %cs:(%si)
#
# Transition to 16 bit protected mode
#
.byte 0x0f,0x20,0xc0 #movl %cr0, %eax # Get control register 0
.byte 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
.byte 0x0f,0x22,0xc0 #movl %eax, %cr0 # Activate protected mode
#
# Now we're in 16 bit protected mode
# Set up the selectors for 32 bit protected mode entry
#
.byte 0xb8 #movw SYS_DATA_SEL, %ax
.word SYS_DATA_SEL
.byte 0x8e,0xd8 #movw %ax, %ds
.byte 0x8e,0xc0 #movw %ax, %es
.byte 0x8e,0xe0 #movw %ax, %fs
.byte 0x8e,0xe8 #movw %ax, %gs
.byte 0x8e,0xd0 #movw %ax, %ss
#
# Transition to Flat 32 bit protected mode
# The jump to a far pointer causes the transition to 32 bit mode
#
.byte 0x66,0xbe #movl ProtectedModeEntryLinearAddress, %esi
.long ProtectedModeEntryLinearAddress
.byte 0x66,0x2e,0xff,0x2c #jmp %cs:(%esi)
#
# Protected mode portion initializes stack, configures cache, and calls C entry point
#
#----------------------------------------------------------------------------
#
# Procedure: ProtectedModeEntryPoint
#
# Input: Executing in 32 Bit Protected (flat) mode
# cs: 0-4GB
# ds: 0-4GB
# es: 0-4GB
# fs: 0-4GB
# gs: 0-4GB
# ss: 0-4GB
#
# Output: This function never returns
#
# Destroys:
# ecx
# edi
# esi
# esp
#
# Description:
# Perform any essential early platform initilaisation
# Setup a stack
#
#----------------------------------------------------------------------------
ProtectedModeEntryPoint:
#
# Dummy function. Consume 2 API to make sure they can be linked.
#
movl ASM_PFX(TempRamInitApi), %eax
movl ASM_PFX(FspInitApi), %eax
#
# Should never return
#
jmp . #'$'
#
# ROM-based Global-Descriptor Table for the PEI Phase
#
.align 16
#
# GDT[0]: 000h: Null entry, never used.
#
.equ NULL_SEL, . - GDT_BASE # Selector [0]
GDT_BASE:
BootGdtTable:
.long 0
.long 0
#
# Linear code segment descriptor
#
.equ LINEAR_CODE_SEL, . - GDT_BASE # Selector [08h]
.word 0xFFFF # limit 0FFFFh
.word 0 # base 0
.byte 0
.byte 0x9B # present, ring 0, data, expand-up, not-writable
.byte 0xCF # page-granular, 32-bit
.byte 0
#
# System data segment descriptor
#
.equ SYS_DATA_SEL, . - GDT_BASE # Selector [010h]
.word 0xFFFF # limit 0FFFFh
.word 0 # base 0
.byte 0
.byte 0x93 # present, ring 0, data, expand-up, not-writable
.byte 0xCF # page-granular, 32-bit
.byte 0
.equ GDT_SIZE, . - BootGdtTable # Size, in bytes
#
# GDT Descriptor
#
GdtDesc: # GDT descriptor
.word GDT_SIZE - 1
.long BootGdtTable
ProtectedModeEntryLinearAddress:
ProtectedModeEntryLinearOffset:
.long ProtectedModeEntryPoint
.word LINEAR_CODE_SEL

45
IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/SecCarInit.asm
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@ -1,45 +0,0 @@
;; @file
; SEC CAR function
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
;
; Define assembler characteristics
;
.586p
.xmm
.model flat, c
RET_ESI MACRO
movd esi, mm7 ; move ReturnAddress from MM7 to ESI
jmp esi
ENDM
.code
;-----------------------------------------------------------------------------
;
; Section: SecCarInit
;
; Description: This function initializes the Cache for Data, Stack, and Code
;
;-----------------------------------------------------------------------------
SecCarInit PROC NEAR PUBLIC
;
; Set up CAR
;
xor eax, eax
SecCarInitExit:
RET_ESI
SecCarInit ENDP
END

31
IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/SecCarInit.s
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@ -1,31 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
# Abstract:
#
# SEC CAR function
#
#------------------------------------------------------------------------------
#-----------------------------------------------------------------------------
#
# Section: SecCarInit
#
# Description: This function initializes the Cache for Data, Stack, and Code
#
#-----------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(SecCarInit)
ASM_PFX(SecCarInit):
#
# Set up CAR
#
xor %eax, %eax
SecCarInitExit:
movd %mm7, %esi #RET_ESI
jmp *%esi

28
IntelFspPkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
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@ -1,28 +0,0 @@
/** @file
Null instance of Platform Sec Lib.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
/**
This function check the signture of UPD.
@param[in] ApiIdx Internal index of the FSP API.
@param[in] ApiParam Parameter of the FSP API.
**/
EFI_STATUS
EFIAPI
FspUpdSignatureCheck (
IN UINT32 ApiIdx,
IN VOID *ApiParam
)
{
return EFI_SUCCESS;
}

53
IntelFspPkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
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@ -1,53 +0,0 @@
## @file
# NULL instance of Platform Sec Lib.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseFspSecPlatformLibNull
FILE_GUID = 03DA99B3-DDF4-4c7e-8CCA-216FC3F1F311
MODULE_TYPE = SEC
VERSION_STRING = 1.0
LIBRARY_CLASS = FspSecPlatformLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32
#
################################################################################
#
# Sources Section - list of files that are required for the build to succeed.
#
################################################################################
[Sources]
PlatformSecLibNull.c
[Sources.IA32]
Ia32/Flat32.asm
Ia32/Flat32.s
Ia32/SecCarInit.asm
Ia32/SecCarInit.s
################################################################################
#
# Package Dependency Section - list of Package files that are required for
# this module.
#
################################################################################
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec

1298
IntelFspPkg/Tools/GenCfgOpt.py
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File diff suppressed because it is too large Load Diff

905
IntelFspPkg/Tools/PatchFv.py
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@ -1,905 +0,0 @@
## @ PatchFv.py
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
import os
import re
import sys
#
# Read data from file
#
# param [in] binfile Binary file
# param [in] offset Offset
# param [in] len Length
#
# retval value Value
#
def readDataFromFile (binfile, offset, len=1):
fd = open(binfile, "r+b")
fsize = os.path.getsize(binfile)
offval = offset & 0xFFFFFFFF
if (offval & 0x80000000):
offval = fsize - (0xFFFFFFFF - offval + 1)
fd.seek(offval)
bytearray = [ord(b) for b in fd.read(len)]
value = 0
idx = len - 1
while idx >= 0:
value = value << 8 | bytearray[idx]
idx = idx - 1
fd.close()
return value
#
# Check FSP header is valid or not
#
# param [in] binfile Binary file
#
# retval boolean True: valid; False: invalid
#
def IsFspHeaderValid (binfile):
fd = open (binfile, "rb")
bindat = fd.read(0x200) # only read first 0x200 bytes
fd.close()
HeaderList = ['FSPH' , 'FSPP' , 'FSPE'] # Check 'FSPH', 'FSPP', and 'FSPE' in the FSP header
OffsetList = []
for each in HeaderList:
if each in bindat:
idx = bindat.index(each)
else:
idx = 0
OffsetList.append(idx)
if not OffsetList[0] or not OffsetList[1]: # If 'FSPH' or 'FSPP' is missing, it will return false
return False
Revision = ord(bindat[OffsetList[0] + 0x0B])
#
# if revision is bigger than 1, it means it is FSP v1.1 or greater revision, which must contain 'FSPE'.
#
if Revision > 1 and not OffsetList[2]:
return False # If FSP v1.1 or greater without 'FSPE', then return false
return True
#
# Patch data in file
#
# param [in] binfile Binary file
# param [in] offset Offset
# param [in] value Patch value
# param [in] len Length
#
# retval len Length
#
def patchDataInFile (binfile, offset, value, len=1):
fd = open(binfile, "r+b")
fsize = os.path.getsize(binfile)
offval = offset & 0xFFFFFFFF
if (offval & 0x80000000):
offval = fsize - (0xFFFFFFFF - offval + 1)
bytearray = []
idx = 0
while idx < len:
bytearray.append(value & 0xFF)
value = value >> 8
idx = idx + 1
fd.seek(offval)
fd.write("".join(chr(b) for b in bytearray))
fd.close()
return len
class Symbols:
def __init__(self):
self.dictSymbolAddress = {}
self.dictGuidNameXref = {}
self.dictFfsOffset = {}
self.dictVariable = {}
self.dictModBase = {}
self.fdFile = None
self.string = ""
self.fdBase = 0xFFFFFFFF
self.fdSize = 0
self.index = 0
self.parenthesisOpenSet = '([{<'
self.parenthesisCloseSet = ')]}>'
#
# Get FD file
#
# retval self.fdFile Retrieve FD file
#
def getFdFile (self):
return self.fdFile
#
# Get FD size
#
# retval self.fdSize Retrieve the size of FD file
#
def getFdSize (self):
return self.fdSize
#
# Create dictionaries
#
# param [in] fvDir FV's directory
# param [in] fvNames All FV's names
#
# retval 0 Created dictionaries successfully
#
def createDicts (self, fvDir, fvNames):
#
# If the fvDir is not a dirctory, then raise an exception
#
if not os.path.isdir(fvDir):
raise Exception ("'%s' is not a valid directory!" % FvDir)
#
# If the Guid.xref is not existing in fvDir, then raise an exception
#
xrefFile = os.path.join(fvDir, "Guid.xref")
if not os.path.exists(xrefFile):
raise Exception("Cannot open GUID Xref file '%s'!" % xrefFile)
#
# Add GUID reference to dictionary
#
self.dictGuidNameXref = {}
self.parseGuidXrefFile(xrefFile)
#
# Split up each FV from fvNames and get the fdBase
#
fvList = fvNames.split(":")
fdBase = fvList.pop()
if len(fvList) == 0:
fvList.append(fdBase)
#
# If the FD file is not existing, then raise an exception
#
fdFile = os.path.join(fvDir, fdBase.strip() + ".fd")
if not os.path.exists(fdFile):
raise Exception("Cannot open FD file '%s'!" % fdFile)
#
# Get the size of the FD file
#
self.fdFile = fdFile
self.fdSize = os.path.getsize(fdFile)
#
# If the INF file, which is the first element of fvList, is not existing, then raise an exception
#
infFile = os.path.join(fvDir, fvList[0].strip()) + ".inf"
if not os.path.exists(infFile):
raise Exception("Cannot open INF file '%s'!" % infFile)
#
# Parse INF file in order to get fdBase and then assign those values to dictVariable
#
self.parseInfFile(infFile)
self.dictVariable = {}
self.dictVariable["FDSIZE"] = self.fdSize
self.dictVariable["FDBASE"] = self.fdBase
#
# Collect information from FV MAP file and FV TXT file then
# put them into dictionaries
#
self.dictSymbolAddress = {}
self.dictFfsOffset = {}
for file in fvList:
#
# If the .Fv.map file is not existing, then raise an exception.
# Otherwise, parse FV MAP file
#
fvFile = os.path.join(fvDir, file.strip()) + ".Fv"
mapFile = fvFile + ".map"
if not os.path.exists(mapFile):
raise Exception("Cannot open MAP file '%s'!" % mapFile)
self.parseFvMapFile(mapFile)
#
# If the .Fv.txt file is not existing, then raise an exception.
# Otherwise, parse FV TXT file
#
fvTxtFile = fvFile + ".txt"
if not os.path.exists(fvTxtFile):
raise Exception("Cannot open FV TXT file '%s'!" % fvTxtFile)
self.parseFvTxtFile(fvTxtFile)
#
# Search all MAP files in FFS directory if it exists then parse MOD MAP file
#
ffsDir = os.path.join(fvDir, "Ffs")
if (os.path.isdir(ffsDir)):
for item in os.listdir(ffsDir):
if len(item) <= 0x24:
continue
mapFile =os.path.join(ffsDir, item, "%s.map" % item[0:0x24])
if not os.path.exists(mapFile):
continue
self.parseModMapFile(item[0x24:], mapFile)
return 0
#
# Get FV offset in FD file
#
# param [in] fvFile FV file
#
# retval offset Got FV offset successfully
#
def getFvOffsetInFd(self, fvFile):
#
# Check if the first 0x70 bytes of fvFile can be found in fdFile
#
fvHandle = open(fvFile, "r+b")
fdHandle = open(self.fdFile, "r+b")
offset = fdHandle.read().find(fvHandle.read(0x70))
fvHandle.close()
fdHandle.close()
if offset == -1:
raise Exception("Could not locate FV file %s in FD!" % fvFile)
return offset
#
# Parse INF file
#
# param [in] infFile INF file
#
# retval 0 Parsed INF file successfully
#
def parseInfFile(self, infFile):
#
# Get FV offset and search EFI_BASE_ADDRESS in the FD file
# then assign the value of EFI_BASE_ADDRESS to fdBase
#
fvOffset = self.getFvOffsetInFd(infFile[0:-4] + ".Fv")
fdIn = open(infFile, "r")
rptLine = fdIn.readline()
self.fdBase = 0xFFFFFFFF
while (rptLine != "" ):
#EFI_BASE_ADDRESS = 0xFFFDF400
match = re.match("^EFI_BASE_ADDRESS\s*=\s*(0x[a-fA-F0-9]+)", rptLine)
if match is not None:
self.fdBase = int(match.group(1), 16) - fvOffset
rptLine = fdIn.readline()
fdIn.close()
if self.fdBase == 0xFFFFFFFF:
raise Exception("Could not find EFI_BASE_ADDRESS in INF file!" % fvFile)
return 0
#
# Parse FV TXT file
#
# param [in] fvTxtFile .Fv.txt file
#
# retval 0 Parsed FV TXT file successfully
#
def parseFvTxtFile(self, fvTxtFile):
#
# Get information from .Fv.txt in order to create a dictionary
# For example,
# self.dictFfsOffset[912740BE-2284-4734-B971-84B027353F0C] = 0x000D4078
#
fvOffset = self.getFvOffsetInFd(fvTxtFile[0:-4])
fdIn = open(fvTxtFile, "r")
rptLine = fdIn.readline()
while (rptLine != "" ):
match = re.match("(0x[a-fA-F0-9]+)\s([0-9a-fA-F\-]+)", rptLine)
if match is not None:
self.dictFfsOffset[match.group(2)] = "0x%08X" % (int(match.group(1), 16) + fvOffset)
rptLine = fdIn.readline()
fdIn.close()
return 0
#
# Parse FV MAP file
#
# param [in] mapFile .Fv.map file
#
# retval 0 Parsed FV MAP file successfully
#
def parseFvMapFile(self, mapFile):
#
# Get information from .Fv.map in order to create dictionaries
# For example,
# self.dictModBase[FspSecCore:BASE] = 4294592776 (0xfffa4908)
# self.dictModBase[FspSecCore:ENTRY] = 4294606552 (0xfffa7ed8)
# self.dictModBase[FspSecCore:TEXT] = 4294593080 (0xfffa4a38)
# self.dictModBase[FspSecCore:DATA] = 4294612280 (0xfffa9538)
# self.dictSymbolAddress[FspSecCore:_SecStartup] = 0x00fffa4a38
#
fdIn = open(mapFile, "r")
rptLine = fdIn.readline()
modName = ""
while (rptLine != "" ):
if rptLine[0] != ' ':
#DxeIpl (Fixed Flash Address, BaseAddress=0x00fffb4310, EntryPoint=0x00fffb4958)
#(GUID=86D70125-BAA3-4296-A62F-602BEBBB9081 .textbaseaddress=0x00fffb4398 .databaseaddress=0x00fffb4178)
match = re.match("([_a-zA-Z0-9\-]+)\s\(.+BaseAddress=(0x[0-9a-fA-F]+),\s+EntryPoint=(0x[0-9a-fA-F]+)\)", rptLine)
if match is not None:
modName = match.group(1)
if len(modName) == 36:
modName = self.dictGuidNameXref[modName.upper()]
self.dictModBase['%s:BASE' % modName] = int (match.group(2), 16)
self.dictModBase['%s:ENTRY' % modName] = int (match.group(3), 16)
match = re.match("\(GUID=([A-Z0-9\-]+)\s+\.textbaseaddress=(0x[0-9a-fA-F]+)\s+\.databaseaddress=(0x[0-9a-fA-F]+)\)", rptLine)
if match is not None:
modName = match.group(1)
if len(modName) == 36:
modName = self.dictGuidNameXref[modName.upper()]
self.dictModBase['%s:TEXT' % modName] = int (match.group(2), 16)
self.dictModBase['%s:DATA' % modName] = int (match.group(3), 16)
else:
# 0x00fff8016c __ModuleEntryPoint
match = re.match("^\s+(0x[a-z0-9]+)\s+([_a-zA-Z0-9]+)", rptLine)
if match is not None:
self.dictSymbolAddress["%s:%s"%(modName, match.group(2))] = match.group(1)
rptLine = fdIn.readline()
fdIn.close()
return 0
#
# Parse MOD MAP file
#
# param [in] moduleName Module name
# param [in] mapFile .Fv.map file
#
# retval 0 Parsed MOD MAP file successfully
# retval 1 There is no moduleEntryPoint in modSymbols
#
def parseModMapFile(self, moduleName, mapFile):
#
# Get information from mapFile by moduleName in order to create a dictionary
# For example,
# self.dictSymbolAddress[FspSecCore:___guard_fids_count] = 0x00fffa4778
#
modSymbols = {}
fdIn = open(mapFile, "r")
reportLines = fdIn.readlines()
fdIn.close()
moduleEntryPoint = "__ModuleEntryPoint"
reportLine = reportLines[0]
if reportLine.strip().find("Archive member included") != -1:
#GCC
# 0x0000000000001d55 IoRead8
patchMapFileMatchString = "\s+(0x[0-9a-fA-F]{16})\s+([^\s][^0x][_a-zA-Z0-9\-]+)\s"
matchKeyGroupIndex = 2
matchSymbolGroupIndex = 1
prefix = '_'
else:
#MSFT
#0003:00000190 _gComBase 00007a50 SerialPo
patchMapFileMatchString = "^\s[0-9a-fA-F]{4}:[0-9a-fA-F]{8}\s+(\w+)\s+([0-9a-fA-F]{8}\s+)"
matchKeyGroupIndex = 1
matchSymbolGroupIndex = 2
prefix = ''
for reportLine in reportLines:
match = re.match(patchMapFileMatchString, reportLine)
if match is not None:
modSymbols[prefix + match.group(matchKeyGroupIndex)] = match.group(matchSymbolGroupIndex)
# Handle extra module patchable PCD variable in Linux map since it might have different format
# .data._gPcd_BinaryPatch_PcdVpdBaseAddress
# 0x0000000000003714 0x4 /tmp/ccmytayk.ltrans1.ltrans.o
handleNext = False
if matchSymbolGroupIndex == 1:
for reportLine in reportLines:
if handleNext:
handleNext = False
pcdName = match.group(1)
match = re.match("\s+(0x[0-9a-fA-F]{16})\s+", reportLine)
if match is not None:
modSymbols[prefix + pcdName] = match.group(1)
else:
match = re.match("^\s\.data\.(_gPcd_BinaryPatch[_a-zA-Z0-9\-]+)", reportLine)
if match is not None:
handleNext = True
continue
if not moduleEntryPoint in modSymbols:
return 1
modEntry = '%s:%s' % (moduleName,moduleEntryPoint)
if not modEntry in self.dictSymbolAddress:
modKey = '%s:ENTRY' % moduleName
if modKey in self.dictModBase:
baseOffset = self.dictModBase['%s:ENTRY' % moduleName] - int(modSymbols[moduleEntryPoint], 16)
else:
return 2
else:
baseOffset = int(self.dictSymbolAddress[modEntry], 16) - int(modSymbols[moduleEntryPoint], 16)
for symbol in modSymbols:
fullSym = "%s:%s" % (moduleName, symbol)
if not fullSym in self.dictSymbolAddress:
self.dictSymbolAddress[fullSym] = "0x00%08x" % (baseOffset+ int(modSymbols[symbol], 16))
return 0
#
# Parse Guid.xref file
#
# param [in] xrefFile the full directory of Guid.xref file
#
# retval 0 Parsed Guid.xref file successfully
#
def parseGuidXrefFile(self, xrefFile):
#
# Get information from Guid.xref in order to create a GuidNameXref dictionary
# The dictGuidNameXref, for example, will be like
# dictGuidNameXref [1BA0062E-C779-4582-8566-336AE8F78F09] = FspSecCore
#
fdIn = open(xrefFile, "r")
rptLine = fdIn.readline()
while (rptLine != "" ):
match = re.match("([0-9a-fA-F\-]+)\s([_a-zA-Z0-9]+)", rptLine)
if match is not None:
self.dictGuidNameXref[match.group(1).upper()] = match.group(2)
rptLine = fdIn.readline()
fdIn.close()
return 0
#
# Get current character
#
# retval elf.string[self.index]
# retval '' Exception
#
def getCurr(self):
try:
return self.string[self.index]
except Exception:
return ''
#
# Check to see if it is last index
#
# retval self.index
#
def isLast(self):
return self.index == len(self.string)
#
# Move to next index
#
def moveNext(self):
self.index += 1
#
# Skip space
#
def skipSpace(self):
while not self.isLast():
if self.getCurr() in ' \t':
self.moveNext()
else:
return
#
# Parse value
#
# retval value
#
def parseValue(self):
self.skipSpace()
var = ''
while not self.isLast():
char = self.getCurr()
if char.lower() in '_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789:-':
var += char
self.moveNext()
else:
break
if ':' in var:
partList = var.split(':')
if len(partList) != 2:
raise Exception("Unrecognized expression %s" % var)
modName = partList[0]
modOff = partList[1]
if ('-' not in modName) and (modOff[0] in '0123456789'):
# MOD: OFFSET
var = self.getModGuid(modName) + ":" + modOff
if '-' in var: # GUID:OFFSET
value = self.getGuidOff(var)
else:
value = self.getSymbols(var)
self.synUsed = True
else:
if var[0] in '0123456789':
value = self.getNumber(var)
else:
value = self.getVariable(var)
return int(value)
#
# Parse single operation
#
# retval ~self.parseBrace() or self.parseValue()
#
def parseSingleOp(self):
self.skipSpace()
char = self.getCurr()
if char == '~':
self.moveNext()
return ~self.parseBrace()
else:
return self.parseValue()
#
# Parse symbol of Brace([, {, <)
#
# retval value or self.parseSingleOp()
#
def parseBrace(self):
self.skipSpace()
char = self.getCurr()
parenthesisType = self.parenthesisOpenSet.find(char)
if parenthesisType >= 0:
self.moveNext()
value = self.parseExpr()
self.skipSpace()
if self.getCurr() != self.parenthesisCloseSet[parenthesisType]:
raise Exception("No closing brace")
self.moveNext()
if parenthesisType == 1: # [ : Get content
value = self.getContent(value)
elif parenthesisType == 2: # { : To address
value = self.toAddress(value)
elif parenthesisType == 3: # < : To offset
value = self.toOffset(value)
return value
else:
return self.parseSingleOp()
#
# Parse symbol of Multiplier(*)
#
# retval value or self.parseSingleOp()
#
def parseMul(self):
values = [self.parseBrace()]
while True:
self.skipSpace()
char = self.getCurr()
if char == '*':
self.moveNext()
values.append(self.parseBrace())
else:
break
value = 1
for each in values:
value *= each
return value
#
# Parse symbol of And(&) and Or(|)
#
# retval value
#
def parseAndOr(self):
values = [self.parseMul()]
op = None
value = 0xFFFFFFFF
while True:
self.skipSpace()
char = self.getCurr()
if char == '&':
self.moveNext()
values.append(self.parseMul())
op = char
elif char == '|':
div_index = self.index
self.moveNext()
values.append(self.parseMul())
value = 0
op = char
else:
break
for each in values:
if op == '|':
value |= each
else:
value &= each
return value
#
# Parse symbol of Add(+) and Minus(-)
#
# retval sum(values)
#
def parseAddMinus(self):
values = [self.parseAndOr()]
while True:
self.skipSpace()
char = self.getCurr()
if char == '+':
self.moveNext()
values.append(self.parseAndOr())
elif char == '-':
self.moveNext()
values.append(-1 * self.parseAndOr())
else:
break
return sum(values)
#
# Parse expression
#
# retval self.parseAddMinus()
#
def parseExpr(self):
return self.parseAddMinus()
#
# Get result
#
# retval value
#
def getResult(self):
value = self.parseExpr()
self.skipSpace()
if not self.isLast():
raise Exception("Unexpected character found '%s'" % self.getCurr())
return value
#
# Get module GUID
#
# retval value
#
def getModGuid(self, var):
guid = (guid for guid,name in self.dictGuidNameXref.items() if name==var)
try:
value = guid.next()
except Exception:
raise Exception("Unknown module name %s !" % var)
return value
#
# Get variable
#
# retval value
#
def getVariable(self, var):
value = self.dictVariable.get(var, None)
if value == None:
raise Exception("Unrecognized variable '%s'" % var)
return value
#
# Get number
#
# retval value
#
def getNumber(self, var):
var = var.strip()
if var.startswith('0x'): # HEX
value = int(var, 16)
else:
value = int(var, 10)
return value
#
# Get content
#
# param [in] value
#
# retval value
#
def getContent(self, value):
if (value >= self.fdBase) and (value < self.fdBase + self.fdSize):
value = value - self.fdBase
if value >= self.fdSize:
raise Exception("Invalid file offset 0x%08x !" % value)
return readDataFromFile (self.fdFile, value, 4)
#
# Change value to address
#
# param [in] value
#
# retval value
#
def toAddress(self, value):
if value < self.fdSize:
value = value + self.fdBase
return value
#
# Change value to offset
#
# param [in] value
#
# retval value
#
def toOffset(self, value):
if value > self.fdBase:
value = value - self.fdBase
return value
#
# Get GUID offset
#
# param [in] value
#
# retval value
#
def getGuidOff(self, value):
# GUID:Offset
symbolName = value.split(':')
if len(symbolName) == 2 and self.dictFfsOffset.has_key(symbolName[0]):
value = (int(self.dictFfsOffset[symbolName[0]], 16) + int(symbolName[1], 16)) & 0xFFFFFFFF
else:
raise Exception("Unknown GUID %s !" % value)
return value
#
# Get symbols
#
# param [in] value
#
# retval ret
#
def getSymbols(self, value):
if self.dictSymbolAddress.has_key(value):
# Module:Function
ret = int (self.dictSymbolAddress[value], 16)
else:
raise Exception("Unknown symbol %s !" % value)
return ret
#
# Evaluate symbols
#
# param [in] expression
# param [in] isOffset
#
# retval value & 0xFFFFFFFF
#
def evaluate(self, expression, isOffset):
self.index = 0
self.synUsed = False
self.string = expression
value = self.getResult()
if isOffset:
if self.synUsed:
# Consider it as an address first
if (value >= self.fdBase) and (value < self.fdBase + self.fdSize):
value = value - self.fdBase
if value & 0x80000000:
# Consider it as a negative offset next
offset = (~value & 0xFFFFFFFF) + 1
if offset < self.fdSize:
value = self.fdSize - offset
if value >= self.fdSize:
raise Exception("Invalid offset expression !")
return value & 0xFFFFFFFF
#
# Print out the usage
#
def usage():
print "Usage: \n\tPatchFv FvBuildDir [FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\""
def main():
#
# Parse the options and args
#
symTables = Symbols()
#
# If the arguments are less than 4, then return an error.
#
if len(sys.argv) < 4:
Usage()
return 1
#
# If it fails to create dictionaries, then return an error.
#
if symTables.createDicts(sys.argv[1], sys.argv[2]) != 0:
print "ERROR: Failed to create symbol dictionary!!"
return 2
#
# Get FD file and size
#
fdFile = symTables.getFdFile()
fdSize = symTables.getFdSize()
try:
#
# Check to see if FSP header is valid
#
ret = IsFspHeaderValid(fdFile)
if ret == False:
raise Exception ("The FSP header is not valid. Stop patching FD.")
comment = ""
for fvFile in sys.argv[3:]:
#
# Check to see if it has enough arguments
#
items = fvFile.split(",")
if len (items) < 2:
raise Exception("Expect more arguments for '%s'!" % fvFile)
comment = ""
command = ""
params = []
for item in items:
item = item.strip()
if item.startswith("@"):
comment = item[1:]
elif item.startswith("$"):
command = item[1:]
else:
if len(params) == 0:
isOffset = True
else :
isOffset = False
#
# Parse symbols then append it to params
#
params.append (symTables.evaluate(item, isOffset))
#
# Patch a new value into FD file if it is not a command
#
if command == "":
# Patch a DWORD
if len (params) == 2:
offset = params[0]
value = params[1]
oldvalue = readDataFromFile(fdFile, offset, 4)
ret = patchDataInFile (fdFile, offset, value, 4) - 4
else:
raise Exception ("Patch command needs 2 parameters !")
if ret:
raise Exception ("Patch failed for offset 0x%08X" % offset)
else:
print "Patched offset 0x%08X:[%08X] with value 0x%08X # %s" % (offset, oldvalue, value, comment)
elif command == "COPY":
#
# Copy binary block from source to destination
#
if len (params) == 3:
src = symTables.toOffset(params[0])
dest = symTables.toOffset(params[1])
clen = symTables.toOffset(params[2])
if (dest + clen <= fdSize) and (src + clen <= fdSize):
oldvalue = readDataFromFile(fdFile, src, clen)
ret = patchDataInFile (fdFile, dest, oldvalue, clen) - clen
else:
raise Exception ("Copy command OFFSET or LENGTH parameter is invalid !")
else:
raise Exception ("Copy command needs 3 parameters !")
if ret:
raise Exception ("Copy failed from offset 0x%08X to offset 0x%08X!" % (src, dest))
else :
print "Copied %d bytes from offset 0x%08X ~ offset 0x%08X # %s" % (clen, src, dest, comment)
else:
raise Exception ("Unknown command %s!" % command)
return 0
except Exception as (ex):
print "ERROR: %s" % ex
return 1
if __name__ == '__main__':
sys.exit(main())

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IntelFspPkg/Tools/UserManuals/GenCfgOptUserManual.docx
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193
IntelFspWrapperPkg/FspInitPei/FindPeiCore.c
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@ -1,193 +0,0 @@
/** @file
Locate the entry point for the PEI Core
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/BaseLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include "SecMain.h"
/**
Find core image base.
@param[in] BootFirmwareVolumePtr Point to the boot firmware volume.
@param[out] SecCoreImageBase The base address of the SEC core image.
@param[out] PeiCoreImageBase The base address of the PEI core image.
**/
EFI_STATUS
EFIAPI
FindImageBase (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,
OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
)
{
EFI_PHYSICAL_ADDRESS CurrentAddress;
EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
EFI_FFS_FILE_HEADER *File;
UINT32 Size;
EFI_PHYSICAL_ADDRESS EndOfFile;
EFI_COMMON_SECTION_HEADER *Section;
EFI_PHYSICAL_ADDRESS EndOfSection;
*SecCoreImageBase = 0;
*PeiCoreImageBase = 0;
CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;
EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;
//
// Loop through the FFS files in the Boot Firmware Volume
//
for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {
CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;
if (CurrentAddress > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
}
File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
if (IS_FFS_FILE2 (File)) {
Size = FFS_FILE2_SIZE (File);
if (Size <= 0x00FFFFFF) {
return EFI_NOT_FOUND;
}
} else {
Size = FFS_FILE_SIZE (File);
if (Size < sizeof (EFI_FFS_FILE_HEADER)) {
return EFI_NOT_FOUND;
}
}
EndOfFile = CurrentAddress + Size;
if (EndOfFile > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
}
//
// Look for SEC Core / PEI Core files
//
if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&
File->Type != EFI_FV_FILETYPE_PEI_CORE) {
continue;
}
//
// Loop through the FFS file sections within the FFS file
//
if (IS_FFS_FILE2 (File)) {
EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));
} else {
EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));
}
for (;;) {
CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;
Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
if (IS_SECTION2 (Section)) {
Size = SECTION2_SIZE (Section);
if (Size <= 0x00FFFFFF) {
return EFI_NOT_FOUND;
}
} else {
Size = SECTION_SIZE (Section);
if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {
return EFI_NOT_FOUND;
}
}
EndOfSection = CurrentAddress + Size;
if (EndOfSection > EndOfFile) {
return EFI_NOT_FOUND;
}
//
// Look for executable sections
//
if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {
if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {
if (IS_SECTION2 (Section)) {
*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));
} else {
*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
} else {
if (IS_SECTION2 (Section)) {
*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));
} else {
*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
}
break;
}
}
//
// Both SEC Core and PEI Core images found
//
if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {
return EFI_SUCCESS;
}
}
}
/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param[in] BootFirmwareVolumePtr Point to the boot firmware volume.
@param[out] PeiCoreEntryPoint The entry point of the PEI core.
**/
VOID
EFIAPI
FindAndReportEntryPoints (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS SecCoreImageBase;
EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
//
// Find SEC Core and PEI Core image base
//
Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);
ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));
//
// Report SEC Core debug information when remote debug is enabled
//
ImageContext.ImageAddress = SecCoreImageBase;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
//
// Report PEI Core debug information when remote debug is enabled
//
ImageContext.ImageAddress = PeiCoreImageBase;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
//
// Find PEI Core entry point
//
Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
if (EFI_ERROR (Status)) {
*PeiCoreEntryPoint = 0;
}
return;
}

60
IntelFspWrapperPkg/FspInitPei/FspInitPei.c
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@ -1,60 +0,0 @@
/** @file
This PEIM initialize FSP.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "FspInitPei.h"
/**
This is the entrypoint of PEIM
@param[in] FileHandle Handle of the file being invoked.
@param[in] PeiServices Describes the list of possible PEI Services.
@retval EFI_SUCCESS if it completed successfully.
**/
EFI_STATUS
EFIAPI
FspPeiEntryPoint (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
FSP_INFO_HEADER *FspHeader;
UINT8 PcdFspApiVersion;
DEBUG ((DEBUG_INFO, "FspPeiEntryPoint\n"));
PcdFspApiVersion = 1;
FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", FspHeader));
if (FspHeader == NULL) {
return EFI_DEVICE_ERROR;
}
ASSERT (FspHeader->TempRamInitEntryOffset != 0);
ASSERT (FspHeader->FspInitEntryOffset != 0);
ASSERT (FspHeader->NotifyPhaseEntryOffset != 0);
if ((PcdGet8 (PcdFspApiVersion) >= 2) &&
(FspHeader->HeaderRevision >= FSP_HEADER_REVISION_2) &&
(FspHeader->ApiEntryNum >= 6) ) {
ASSERT (FspHeader->FspMemoryInitEntryOffset != 0);
ASSERT (FspHeader->TempRamExitEntryOffset != 0);
ASSERT (FspHeader->FspSiliconInitEntryOffset != 0);
PcdFspApiVersion = PcdGet8 (PcdFspApiVersion);
}
DEBUG ((DEBUG_INFO, "PcdFspApiVersion - 0x%x\n", PcdFspApiVersion));
if (PcdFspApiVersion == 1) {
PeiFspInitV1 (FspHeader);
} else {
PeiFspInitV2 (FspHeader);
}
return EFI_SUCCESS;
}

58
IntelFspWrapperPkg/FspInitPei/FspInitPei.h
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@ -1,58 +0,0 @@
/** @file
This is PEIM header file.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_INIT_PEI_H_
#define _FSP_INIT_PEI_H_
#include <PiPei.h>
#include <Library/PeimEntryPoint.h>
#include <Library/PeiServicesLib.h>
#include <Library/PeiServicesTablePointerLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/FspPlatformInfoLib.h>
#include <Library/FspPlatformSecLib.h>
#include <Library/FspHobProcessLib.h>
#include <Library/FspApiLib.h>
#include <Ppi/FspInitDone.h>
#include <Ppi/EndOfPeiPhase.h>
#include <Ppi/MemoryDiscovered.h>
#include <Ppi/TemporaryRamDone.h>
extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;
/**
Do FSP initialization based on FspApi version 1.
@param[in] FspHeader FSP header pointer.
@return FSP initialization status.
**/
EFI_STATUS
PeiFspInitV1 (
IN FSP_INFO_HEADER *FspHeader
);
/**
Do FSP initialization based on FspApi version 2.
@param[in] FspHeader FSP header pointer.
@return FSP initialization status.
**/
EFI_STATUS
PeiFspInitV2 (
IN FSP_INFO_HEADER *FspHeader
);
#endif

85
IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
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@ -1,85 +0,0 @@
## @file
# FSP PEI Module
#
# This PEIM initialize FSP.
# In FSP API V1 mode, it will be invoked twice by pei core. In 1st entry, it will
# call FspInit API. In 2nd entry, it will parse the hoblist from fsp and report
# them into pei core.
# In FSP API V2 mode, it will be invoked only once. It will call FspMemoryInit API,
# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
# notify to call FspSiliconInit API.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FspInitPeim
FILE_GUID = BC59E2E1-7492-4031-806E-C48DCCC3A026
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = FspPeiEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32
#
[Sources]
FspInitPei.c
FspInitPei.h
FspInitPeiV1.c
FspInitPeiV2.c
FspNotifyS3.c
SecMain.c
SecMain.h
FindPeiCore.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
IntelFspPkg/IntelFspPkg.dec
IntelFspWrapperPkg/IntelFspWrapperPkg.dec
[LibraryClasses]
PeimEntryPoint
PeiServicesLib
PeiServicesTablePointerLib
BaseLib
BaseMemoryLib
DebugLib
HobLib
FspPlatformInfoLib
FspHobProcessLib
FspPlatformSecLib
DebugAgentLib
UefiCpuLib
PeCoffGetEntryPointLib
PeCoffExtraActionLib
FspApiLib
[Ppis]
gTopOfTemporaryRamPpiGuid ## PRODUCES
gFspInitDonePpiGuid ## PRODUCES
gEfiEndOfPeiSignalPpiGuid ## PRODUCES
gEfiTemporaryRamDonePpiGuid ## PRODUCES
gEfiPeiMemoryDiscoveredPpiGuid ## PRODUCES
[FixedPcd]
gFspWrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported ## CONSUMES
[Pcd]
gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdFspApiVersion ## CONSUMES
[Depex]
gEfiPeiMasterBootModePpiGuid

176
IntelFspWrapperPkg/FspInitPei/FspInitPeiV1.c
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/** @file
In FSP API V1 mode, it will be invoked twice by pei core. In 1st entry, it will
call FspInit API. In 2nd entry, it will parse the hoblist from fsp and report
them into pei core.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "FspInitPei.h"
/**
FSP Init continuation function.
Control will be returned to this callback function after FspInit API call.
@param[in] Status Status of the FSP INIT API
@param[in] HobListPtr Pointer to the HOB data structure defined in the PI specification.
**/
VOID
ContinuationFunc (
IN EFI_STATUS Status,
IN VOID *HobListPtr
)
{
EFI_BOOT_MODE BootMode;
UINT64 StackSize;
EFI_PHYSICAL_ADDRESS StackBase;
DEBUG ((DEBUG_INFO, "ContinuationFunc - %r\n", Status));
DEBUG ((DEBUG_INFO, "HobListPtr - 0x%x\n", HobListPtr));
if (Status != EFI_SUCCESS) {
CpuDeadLoop ();
}
//
// Can not call any PeiServices
//
BootMode = GetBootMode ();
GetStackInfo (BootMode, TRUE, &StackSize, &StackBase);
DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", StackBase));
DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", StackSize));
CallPeiCoreEntryPoint (
HobListPtr,
(VOID *)(UINTN)StackBase,
(VOID *)(UINTN)(StackBase + StackSize)
);
}
/**
Call FspInit API.
@param[in] FspHeader FSP header pointer.
**/
VOID
PeiFspInit (
IN FSP_INFO_HEADER *FspHeader
)
{
FSP_INIT_PARAMS FspInitParams;
FSP_INIT_RT_COMMON_BUFFER FspRtBuffer;
UINT8 FspUpdRgn[FixedPcdGet32 (PcdMaxUpdRegionSize)];
UINT32 UpdRegionSize;
EFI_BOOT_MODE BootMode;
UINT64 StackSize;
EFI_PHYSICAL_ADDRESS StackBase;
EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "PeiFspInit enter\n"));
PeiServicesGetBootMode (&BootMode);
DEBUG ((DEBUG_INFO, "BootMode - 0x%x\n", BootMode));
GetStackInfo (BootMode, FALSE, &StackSize, &StackBase);
DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", StackBase));
DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", StackSize));
ZeroMem (&FspRtBuffer, sizeof(FspRtBuffer));
FspRtBuffer.StackTop = (UINT32 *)(UINTN)(StackBase + StackSize);
FspRtBuffer.BootMode = BootMode;
/* Platform override any UPD configs */
UpdRegionSize = GetUpdRegionSize();
DEBUG ((DEBUG_INFO, "UpdRegionSize - 0x%x\n", UpdRegionSize));
DEBUG ((DEBUG_INFO, "sizeof(FspUpdRgn) - 0x%x\n", sizeof(FspUpdRgn)));
ASSERT(sizeof(FspUpdRgn) >= UpdRegionSize);
ZeroMem (FspUpdRgn, UpdRegionSize);
FspRtBuffer.UpdDataRgnPtr = UpdateFspUpdConfigs (FspUpdRgn);
FspRtBuffer.BootLoaderTolumSize = 0;
ZeroMem (&FspInitParams, sizeof(FspInitParams));
FspInitParams.NvsBufferPtr = GetNvsBuffer ();
DEBUG ((DEBUG_INFO, "NvsBufferPtr - 0x%x\n", FspInitParams.NvsBufferPtr));
FspInitParams.RtBufferPtr = (VOID *)&FspRtBuffer;
FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ContinuationFunc;
SaveSecContext (GetPeiServicesTablePointer ());
DEBUG ((DEBUG_INFO, "FspInitParams - 0x%x\n", &FspInitParams));
DEBUG ((DEBUG_INFO, " NvsBufferPtr - 0x%x\n", FspInitParams.NvsBufferPtr));
DEBUG ((DEBUG_INFO, " RtBufferPtr - 0x%x\n", FspInitParams.RtBufferPtr));
DEBUG ((DEBUG_INFO, " StackTop - 0x%x\n", FspRtBuffer.StackTop));
DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", FspRtBuffer.BootMode));
DEBUG ((DEBUG_INFO, " UpdDataRgnPtr - 0x%x\n", FspRtBuffer.UpdDataRgnPtr));
DEBUG ((DEBUG_INFO, " ContinuationFunc - 0x%x\n", FspInitParams.ContinuationFunc));
Status = CallFspInit (FspHeader, &FspInitParams);
//
// Should never return
//
DEBUG((DEBUG_ERROR, "FSP Init failed, status: 0x%x\n", Status));
CpuDeadLoop ();
}
/**
Do FSP initialization based on FspApi version 1.
@param[in] FspHeader FSP header pointer.
@return FSP initialization status.
**/
EFI_STATUS
PeiFspInitV1 (
IN FSP_INFO_HEADER *FspHeader
)
{
EFI_STATUS Status;
FSP_INIT_DONE_PPI *FspInitDone;
VOID *FspHobList;
EFI_BOOT_MODE BootMode;
Status = PeiServicesLocatePpi (
&gFspInitDonePpiGuid,
0,
NULL,
(VOID **) &FspInitDone
);
if (EFI_ERROR (Status)) {
//
// 1st entry
//
DEBUG ((DEBUG_INFO, "1st entry\n"));
PeiFspInit (FspHeader);
//
// Never return here, for FspApi version 1.
//
CpuDeadLoop ();
} else {
//
// 2nd entry for FspApi version 1 only.
//
DEBUG ((DEBUG_INFO, "2nd entry\n"));
Status = FspInitDone->GetFspHobList (GetPeiServicesTablePointer (), FspInitDone, &FspHobList);
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
FspHobProcess (FspHobList);
//
// Register EndOfPei Notify for S3 to run FspNotifyPhase
//
PeiServicesGetBootMode (&BootMode);
if (BootMode == BOOT_ON_S3_RESUME) {
Status = PeiServicesNotifyPpi (&mS3EndOfPeiNotifyDesc);
ASSERT_EFI_ERROR (Status);
}
}
return EFI_SUCCESS;
}

332
IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
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@ -1,332 +0,0 @@
/** @file
In FSP API V2 mode, it will be invoked only once. It will call FspMemoryInit API,
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "FspInitPei.h"
/**
Return Hob list produced by FSP.
@param[in] PeiServices The pointer to the PEI Services Table.
@param[in] This The pointer to this instance of this PPI.
@param[out] FspHobList The pointer to Hob list produced by FSP.
@return EFI_SUCCESS FReturn Hob list produced by FSP successfully.
**/
EFI_STATUS
EFIAPI
FspInitDoneGetFspHobListV2 (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN FSP_INIT_DONE_PPI *This,
OUT VOID **FspHobList
);
FSP_INIT_DONE_PPI mFspInitDonePpiV2 = {
FspInitDoneGetFspHobListV2
};
EFI_PEI_PPI_DESCRIPTOR mPeiFspInitDonePpiV2 = {
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gFspInitDonePpiGuid,
&mFspInitDonePpiV2
};
/**
This function is called after PEI core discover memory and finish migration.
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_STATUS Always return EFI_SUCCESS
**/
EFI_STATUS
EFIAPI
PeiMemoryDiscoveredNotify (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
IN VOID *Ppi
);
EFI_PEI_NOTIFY_DESCRIPTOR mPeiMemoryDiscoveredNotifyDesc = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiMemoryDiscoveredPpiGuid,
PeiMemoryDiscoveredNotify
};
/**
TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
@retval EFI_SUCCESS Use of Temporary RAM was disabled.
@retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
**/
EFI_STATUS
EFIAPI
PeiTemporaryRamDone (
VOID
);
EFI_PEI_TEMPORARY_RAM_DONE_PPI mPeiTemporaryRamDonePpi = {
PeiTemporaryRamDone
};
EFI_PEI_PPI_DESCRIPTOR mPeiTemporaryRamDoneDesc = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiTemporaryRamDonePpiGuid,
&mPeiTemporaryRamDonePpi
};
/**
Return Hob list produced by FSP.
@param[in] PeiServices The pointer to the PEI Services Table.
@param[in] This The pointer to this instance of this PPI.
@param[out] FspHobList The pointer to Hob list produced by FSP.
@return EFI_SUCCESS FReturn Hob list produced by FSP successfully.
**/
EFI_STATUS
EFIAPI
FspInitDoneGetFspHobListV2 (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN FSP_INIT_DONE_PPI *This,
OUT VOID **FspHobList
)
{
EFI_HOB_GUID_TYPE *GuidHob;
GuidHob = GetFirstGuidHob (&gFspInitDonePpiGuid);
if (GuidHob != NULL) {
*FspHobList = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
return EFI_SUCCESS;
} else {
return EFI_NOT_FOUND;
}
}
/**
Call FspMemoryInit API.
@param[in] FspHeader FSP header pointer.
@return Status returned by FspMemoryInit API.
**/
EFI_STATUS
PeiFspMemoryInit (
IN FSP_INFO_HEADER *FspHeader
)
{
FSP_MEMORY_INIT_PARAMS FspMemoryInitParams;
FSP_INIT_RT_COMMON_BUFFER FspRtBuffer;
UINT8 FspUpdRgn[FixedPcdGet32 (PcdMaxUpdRegionSize)];
UINT32 UpdRegionSize;
EFI_BOOT_MODE BootMode;
UINT64 StackSize;
EFI_PHYSICAL_ADDRESS StackBase;
EFI_STATUS Status;
VOID *FspHobList;
VOID *HobData;
DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
PeiServicesGetBootMode (&BootMode);
DEBUG ((DEBUG_INFO, "BootMode - 0x%x\n", BootMode));
GetStackInfo (BootMode, FALSE, &StackSize, &StackBase);
DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", StackBase));
DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", StackSize));
ZeroMem (&FspRtBuffer, sizeof(FspRtBuffer));
FspRtBuffer.StackTop = (UINT32 *)(UINTN)(StackBase + StackSize);
FspRtBuffer.BootMode = BootMode;
/* Platform override any UPD configs */
UpdRegionSize = GetUpdRegionSize();
DEBUG ((DEBUG_INFO, "UpdRegionSize - 0x%x\n", UpdRegionSize));
DEBUG ((DEBUG_INFO, "sizeof(FspUpdRgn) - 0x%x\n", sizeof(FspUpdRgn)));
ASSERT(sizeof(FspUpdRgn) >= UpdRegionSize);
ZeroMem (FspUpdRgn, UpdRegionSize);
FspRtBuffer.UpdDataRgnPtr = UpdateFspUpdConfigs (FspUpdRgn);
FspRtBuffer.BootLoaderTolumSize = GetBootLoaderTolumSize ();
ZeroMem (&FspMemoryInitParams, sizeof(FspMemoryInitParams));
FspMemoryInitParams.NvsBufferPtr = GetNvsBuffer ();
DEBUG ((DEBUG_INFO, "NvsBufferPtr - 0x%x\n", FspMemoryInitParams.NvsBufferPtr));
FspMemoryInitParams.RtBufferPtr = (VOID *)&FspRtBuffer;
FspHobList = NULL;
FspMemoryInitParams.HobListPtr = &FspHobList;
DEBUG ((DEBUG_INFO, "FspMemoryInitParams - 0x%x\n", &FspMemoryInitParams));
DEBUG ((DEBUG_INFO, " NvsBufferPtr - 0x%x\n", FspMemoryInitParams.NvsBufferPtr));
DEBUG ((DEBUG_INFO, " RtBufferPtr - 0x%x\n", FspMemoryInitParams.RtBufferPtr));
DEBUG ((DEBUG_INFO, " StackTop - 0x%x\n", FspRtBuffer.StackTop));
DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", FspRtBuffer.BootMode));
DEBUG ((DEBUG_INFO, " UpdDataRgnPtr - 0x%x\n", FspRtBuffer.UpdDataRgnPtr));
DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", FspMemoryInitParams.HobListPtr));
Status = CallFspMemoryInit (FspHeader, &FspMemoryInitParams);
DEBUG((DEBUG_INFO, "FspMemoryInit status: 0x%x\n", Status));
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, " HobListPtr (returned) - 0x%x\n", FspHobList));
ASSERT (FspHobList != NULL);
FspHobProcessForMemoryResource (FspHobList);
//
// FspHobList is not complete at this moment.
// Save FspHobList pointer to hob, so that it can be got later
//
HobData = BuildGuidHob (
&gFspInitDonePpiGuid,
sizeof (VOID *)
);
ASSERT (HobData != NULL);
CopyMem (HobData, &FspHobList, sizeof (FspHobList));
return Status;
}
/**
TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
@retval EFI_SUCCESS Use of Temporary RAM was disabled.
@retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
**/
EFI_STATUS
EFIAPI
PeiTemporaryRamDone (
VOID
)
{
EFI_STATUS Status;
VOID *TempRamExitParam;
FSP_INFO_HEADER *FspHeader;
FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
if (FspHeader == NULL) {
return EFI_DEVICE_ERROR;
}
DEBUG ((DEBUG_INFO, "PeiTemporaryRamDone enter\n"));
TempRamExitParam = GetTempRamExitParam ();
Status = CallTempRamExit (FspHeader, TempRamExitParam);
DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS;
}
/**
This function is called after PEI core discover memory and finish migration.
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_STATUS Always return EFI_SUCCESS
**/
EFI_STATUS
EFIAPI
PeiMemoryDiscoveredNotify (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
IN VOID *Ppi
)
{
EFI_STATUS Status;
VOID *FspSiliconInitParam;
FSP_INFO_HEADER *FspHeader;
VOID *FspHobList;
EFI_HOB_GUID_TYPE *GuidHob;
if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {
FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
} else {
FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));
}
if (FspHeader == NULL) {
return EFI_DEVICE_ERROR;
}
DEBUG ((DEBUG_INFO, "PeiMemoryDiscoveredNotify enter\n"));
FspSiliconInitParam = GetFspSiliconInitParam ();
Status = CallFspSiliconInit (FspHeader, FspSiliconInitParam);
DEBUG((DEBUG_ERROR, "FspSiliconInit status: 0x%x\n", Status));
ASSERT_EFI_ERROR (Status);
//
// Now FspHobList complete, process it
//
GuidHob = GetFirstGuidHob (&gFspInitDonePpiGuid);
ASSERT (GuidHob != NULL);
FspHobList = *(VOID **)GET_GUID_HOB_DATA (GuidHob);
DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
FspHobProcessForOtherData (FspHobList);
//
// Install FspInitDonePpi so that any other driver can consume this info.
//
Status = PeiServicesInstallPpi (&mPeiFspInitDonePpiV2);
ASSERT_EFI_ERROR(Status);
return EFI_SUCCESS;
}
/**
Do FSP initialization based on FspApi version 2.
@param[in] FspHeader FSP header pointer.
@return FSP initialization status.
**/
EFI_STATUS
PeiFspInitV2 (
IN FSP_INFO_HEADER *FspHeader
)
{
EFI_STATUS Status;
EFI_BOOT_MODE BootMode;
Status = PeiFspMemoryInit (FspHeader);
ASSERT_EFI_ERROR (Status);
//
// Install TempramDonePpi to run TempRamExit
//
Status = PeiServicesInstallPpi (&mPeiTemporaryRamDoneDesc);
ASSERT_EFI_ERROR(Status);
//
// Register MemoryDiscovered Nofity to run FspSiliconInit
//
Status = PeiServicesNotifyPpi (&mPeiMemoryDiscoveredNotifyDesc);
ASSERT_EFI_ERROR (Status);
//
// Register EndOfPei Notify for S3 to run FspNotifyPhase
//
PeiServicesGetBootMode (&BootMode);
if (BootMode == BOOT_ON_S3_RESUME) {
Status = PeiServicesNotifyPpi (&mS3EndOfPeiNotifyDesc);
ASSERT_EFI_ERROR (Status);
}
return EFI_SUCCESS;
}

74
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@ -1,74 +0,0 @@
/** @file
In EndOfPei notify, it will call FspNotifyPhase API.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "FspInitPei.h"
/**
This function handles S3 resume task at the end of PEI
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_STATUS Always return EFI_SUCCESS
**/
EFI_STATUS
EFIAPI
S3EndOfPeiNotify (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
IN VOID *Ppi
);
EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiEndOfPeiSignalPpiGuid,
S3EndOfPeiNotify
};
/**
This function handles S3 resume task at the end of PEI
@param[in] PeiServices Pointer to PEI Services Table.
@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
caused this function to execute.
@param[in] Ppi Pointer to the PPI data associated with this function.
@retval EFI_STATUS Always return EFI_SUCCESS
**/
EFI_STATUS
EFIAPI
S3EndOfPeiNotify (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
IN VOID *Ppi
)
{
NOTIFY_PHASE_PARAMS NotifyPhaseParams;
EFI_STATUS Status;
FSP_INFO_HEADER *FspHeader;
FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
if (FspHeader == NULL) {
return EFI_DEVICE_ERROR;
}
DEBUG ((DEBUG_INFO, "S3EndOfPeiNotify enter\n"));
NotifyPhaseParams.Phase = EnumInitPhaseAfterPciEnumeration;
Status = CallFspNotifyPhase (FspHeader, &NotifyPhaseParams);
DEBUG((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration status: 0x%x\n", Status));
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
Status = CallFspNotifyPhase (FspHeader, &NotifyPhaseParams);
DEBUG((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot status: 0x%x\n", Status));
return EFI_SUCCESS;
}

304
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@ -1,304 +0,0 @@
/** @file
C functions in SEC
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SecMain.h"
EFI_PEI_PPI_DESCRIPTOR mPeiSecMainPpi[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gTopOfTemporaryRamPpiGuid,
NULL // To be patched later.
},
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gFspInitDonePpiGuid,
&gFspInitDonePpi
},
};
FSP_INIT_DONE_PPI gFspInitDonePpi = {
FspInitDoneGetFspHobList
};
//
// These are IDT entries pointing to 10:FFFFFFE4h.
//
UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] Context The first input parameter of InitializeDebugAgent().
**/
VOID
EFIAPI
SecStartupPhase2(
IN VOID *Context
);
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
UINT32 PeiStackSize;
PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);
if (PeiStackSize == 0) {
PeiStackSize = (SizeOfRam >> 1);
}
ASSERT (PeiStackSize < SizeOfRam);
//
// Process all libraries constructor function linked to SecCore.
//
ProcessLibraryConstructorList ();
DEBUG ((DEBUG_INFO, "FspPei - SecStartup\n"));
//
// Initialize floating point operating environment
// to be compliant with UEFI spec.
//
InitializeFloatingPointUnits ();
// |-------------------|---->
// |Idt Table |
// |-------------------|
// |PeiService Pointer | PeiStackSize
// |-------------------|
// | |
// | Stack |
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporayRamSize
// | |
// | |
// |-------------------|----> TempRamBase
IdtTableInStack.PeiService = 0;
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));
}
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
// Update the base address and length of Pei temporary memory
//
SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;
SecCoreData.BootFirmwareVolumeSize = (UINTN)(SIZE_4GB - (UINTN) BootFirmwareVolume);
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
SecCoreData.TemporaryRamSize = SizeOfRam;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;
SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = PeiStackSize;
DEBUG ((DEBUG_INFO, "BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));
DEBUG ((DEBUG_INFO, "BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));
DEBUG ((DEBUG_INFO, "TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase));
DEBUG ((DEBUG_INFO, "TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize));
DEBUG ((DEBUG_INFO, "PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase));
DEBUG ((DEBUG_INFO, "PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize));
DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", SecCoreData.StackBase));
DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", SecCoreData.StackSize));
//
// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);
}
/**
This API patch the TopOfTemporaryRam value in SecPpiList.
@param[in,out] SecPpiList PPI list to be patched.
@param[in] TopOfTemporaryRam The top of Temporary Ram.
**/
VOID
PatchTopOfTemporaryRamPpi (
IN OUT EFI_PEI_PPI_DESCRIPTOR *SecPpiList,
IN VOID *TopOfTemporaryRam
)
{
SecPpiList[0].Ppi = TopOfTemporaryRam;
}
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] Context The first input parameter of InitializeDebugAgent().
**/
VOID
EFIAPI
SecStartupPhase2(
IN VOID *Context
)
{
EFI_SEC_PEI_HAND_OFF *SecCoreData;
EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINT32 Index;
EFI_PEI_PPI_DESCRIPTOR LocalSecPpiList[sizeof(mPeiSecMainPpi)/sizeof(mPeiSecMainPpi[0])];
EFI_PEI_PPI_DESCRIPTOR AllSecPpiList[FixedPcdGet32(PcdSecCoreMaxPpiSupported)];
EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;
//
// Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug
// is enabled.
//
FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
if (PeiCoreEntryPoint == NULL)
{
CpuDeadLoop ();
}
CopyMem (LocalSecPpiList, mPeiSecMainPpi, sizeof(mPeiSecMainPpi));
PatchTopOfTemporaryRamPpi (LocalSecPpiList, (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize));
//
// Perform platform specific initialization before entering PeiCore.
//
PpiList = SecPlatformMain (SecCoreData);
if (PpiList != NULL) {
//
// Remove the terminal flag from the terminal Ppi
//
CopyMem (AllSecPpiList, LocalSecPpiList, sizeof (LocalSecPpiList));
for (Index = 0; Index < PcdGet32 (PcdSecCoreMaxPpiSupported); Index ++) {
if ((AllSecPpiList[Index].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) == EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) {
break;
}
}
AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
//
// Append the platform additional Ppi list
//
Index += 1;
while (Index < PcdGet32 (PcdSecCoreMaxPpiSupported) &&
((PpiList->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST)) {
CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));
Index++;
PpiList++;
}
//
// Check whether the total Ppis exceeds the max supported Ppi.
//
if (Index >= PcdGet32 (PcdSecCoreMaxPpiSupported)) {
//
// the total Ppi is larger than the supported Max
// PcdSecCoreMaxPpiSupported can be enlarged to solve it.
//
CpuDeadLoop ();
} else {
//
// Add the terminal Ppi
//
CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));
}
//
// Set PpiList to the total Ppi
//
PpiList = &AllSecPpiList[0];
} else {
//
// No addition Ppi, PpiList directly point to the common Ppi list.
//
PpiList = &LocalSecPpiList[0];
}
//
// Transfer the control to the PEI core
//
ASSERT (PeiCoreEntryPoint != NULL);
(*PeiCoreEntryPoint) (SecCoreData, PpiList);
//
// Should not come here.
//
return ;
}
/**
Return Hob list produced by FSP.
@param[in] PeiServices The pointer to the PEI Services Table.
@param[in] This The pointer to this instance of this PPI.
@param[out] FspHobList The pointer to Hob list produced by FSP.
@return EFI_SUCCESS FReturn Hob list produced by FSP successfully.
**/
EFI_STATUS
EFIAPI
FspInitDoneGetFspHobList (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN FSP_INIT_DONE_PPI *This,
OUT VOID **FspHobList
)
{
VOID *TopOfTemporaryRamPpi;
EFI_STATUS Status;
Status = (*PeiServices)->LocatePpi (
PeiServices,
&gTopOfTemporaryRamPpiGuid,
0,
NULL,
(VOID **) &TopOfTemporaryRamPpi
);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
*FspHobList = (VOID *)(UINTN)(*(UINT32 *)((UINTN)TopOfTemporaryRamPpi - sizeof(UINT32)));
return EFI_SUCCESS;
}

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@ -1,110 +0,0 @@
/** @file
Master header file for SecCore.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _SEC_CORE_H_
#define _SEC_CORE_H_
#include <PiPei.h>
#include <Ppi/TopOfTemporaryRam.h>
#include <Ppi/FspInitDone.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/FspPlatformSecLib.h>
#include <Library/FspPlatformInfoLib.h>
#include <Library/UefiCpuLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/PeCoffExtraActionLib.h>
#include <Library/DebugAgentLib.h>
#include <FspApi.h>
#include <FspInfoHeader.h>
#define SEC_IDT_ENTRY_COUNT 34
typedef struct _SEC_IDT_TABLE {
//
// Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base
// address should be 8-byte alignment.
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
// EFI_PEI_SERVICES**
//
UINT64 PeiService;
UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];
} SEC_IDT_TABLE;
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
);
/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param[in] BootFirmwareVolumePtr Point to the boot firmware volume.
@param[out] PeiCoreEntryPoint Point to the PEI core entry point.
**/
VOID
EFIAPI
FindAndReportEntryPoints (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
);
/**
Autogenerated function that calls the library constructors for all of the module's
dependent libraries. This function must be called by the SEC Core once a stack has
been established.
**/
VOID
EFIAPI
ProcessLibraryConstructorList (
VOID
);
/**
Return Hob list produced by FSP.
@param[in] PeiServices The pointer to the PEI Services Table.
@param[in] This The pointer to this instance of this PPI.
@param[out] FspHobList The pointer to Hob list produced by FSP.
@return EFI_SUCCESS FReturn Hob list produced by FSP successfully.
**/
EFI_STATUS
EFIAPI
FspInitDoneGetFspHobList (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN FSP_INIT_DONE_PPI *This,
OUT VOID **FspHobList
);
extern FSP_INIT_DONE_PPI gFspInitDonePpi;
#endif

170
IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
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@ -1,170 +0,0 @@
/** @file
This driver will register two callbacks to call fsp's notifies.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Protocol/PciEnumerationComplete.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiLib.h>
#include <Library/FspApiLib.h>
/**
Relocate this image under 4G memory.
@param ImageHandle Handle of driver image.
@param SystemTable Pointer to system table.
@retval EFI_SUCCESS Image successfully relocated.
@retval EFI_ABORTED Failed to relocate image.
**/
EFI_STATUS
RelocateImageUnder4GIfNeeded (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
);
FSP_INFO_HEADER *mFspHeader = NULL;
/**
PciEnumerationComplete Protocol notification event handler.
@param[in] Event Event whose notification function is being invoked.
@param[in] Context Pointer to the notification function's context.
**/
VOID
EFIAPI
OnPciEnumerationComplete (
IN EFI_EVENT Event,
IN VOID *Context
)
{
NOTIFY_PHASE_PARAMS NotifyPhaseParams;
EFI_STATUS Status;
VOID *Interface;
//
// Try to locate it because gEfiPciEnumerationCompleteProtocolGuid will trigger it once when registration.
// Just return if it is not found.
//
Status = gBS->LocateProtocol (
&gEfiPciEnumerationCompleteProtocolGuid,
NULL,
&Interface
);
if (EFI_ERROR (Status)) {
return ;
}
NotifyPhaseParams.Phase = EnumInitPhaseAfterPciEnumeration;
Status = CallFspNotifyPhase (mFspHeader, &NotifyPhaseParams);
if (Status != EFI_SUCCESS) {
DEBUG((DEBUG_ERROR, "FSP NotifyPhase AfterPciEnumeration failed, status: 0x%x\n", Status));
} else {
DEBUG((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration Success.\n"));
}
}
/**
Notification function of EVT_GROUP_READY_TO_BOOT event group.
This is a notification function registered on EVT_GROUP_READY_TO_BOOT event group.
When the Boot Manager is about to load and execute a boot option, it reclaims variable
storage if free size is below the threshold.
@param[in] Event Event whose notification function is being invoked.
@param[in] Context Pointer to the notification function's context.
**/
VOID
EFIAPI
OnReadyToBoot (
IN EFI_EVENT Event,
IN VOID *Context
)
{
NOTIFY_PHASE_PARAMS NotifyPhaseParams;
EFI_STATUS Status;
gBS->CloseEvent (Event);
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
Status = CallFspNotifyPhase (mFspHeader, &NotifyPhaseParams);
if (Status != EFI_SUCCESS) {
DEBUG((DEBUG_ERROR, "FSP NotifyPhase ReadyToBoot failed, status: 0x%x\n", Status));
} else {
DEBUG((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot Success.\n"));
}
}
/**
Main entry for the FSP DXE module.
This routine registers two callbacks to call fsp's notifies.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
FspDxeEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_EVENT ReadyToBootEvent;
VOID *Registration;
EFI_EVENT ProtocolNotifyEvent;
//
// Load this driver's image to memory
//
Status = RelocateImageUnder4GIfNeeded (ImageHandle, SystemTable);
if (EFI_ERROR (Status)) {
return EFI_SUCCESS;
}
if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {
mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
} else {
mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));
}
DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", mFspHeader));
if (mFspHeader == NULL) {
return EFI_DEVICE_ERROR;
}
ProtocolNotifyEvent = EfiCreateProtocolNotifyEvent (
&gEfiPciEnumerationCompleteProtocolGuid,
TPL_CALLBACK,
OnPciEnumerationComplete,
NULL,
&Registration
);
ASSERT (ProtocolNotifyEvent != NULL);
Status = EfiCreateEventReadyToBootEx (
TPL_CALLBACK,
OnReadyToBoot,
NULL,
&ReadyToBootEvent
);
ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS;
}

55
IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
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@ -1,55 +0,0 @@
## @file
# FSP DXE Module
#
# This driver will register two callbacks to call fsp's notifies.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FspNotifyDxe
FILE_GUID = 8714C537-6D4B-4247-AA6C-29E8495F9100
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = FspDxeEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
FspNotifyDxe.c
LoadBelow4G.c
[Packages]
MdePkg/MdePkg.dec
IntelFspPkg/IntelFspPkg.dec
IntelFspWrapperPkg/IntelFspWrapperPkg.dec
[LibraryClasses]
UefiDriverEntryPoint
UefiBootServicesTableLib
DebugLib
BaseMemoryLib
UefiLib
FspApiLib
PeCoffLib
CacheMaintenanceLib
DxeServicesLib
[Protocols]
gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES
[Pcd]
gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase ## CONSUMES
gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize ## CONSUMES
[Depex]
TRUE

145
IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c
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@ -1,145 +0,0 @@
/** @file
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PeCoffLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/UefiLib.h>
/**
Relocate this image under 4G memory.
@param ImageHandle Handle of driver image.
@param SystemTable Pointer to system table.
@retval EFI_SUCCESS Image successfully relocated.
@retval EFI_ABORTED Failed to relocate image.
**/
EFI_STATUS
RelocateImageUnder4GIfNeeded (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINT8 *Buffer;
UINTN BufferSize;
EFI_HANDLE NewImageHandle;
UINTN Pages;
EFI_PHYSICAL_ADDRESS FfsBuffer;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
VOID *Interface;
//
// If it is already <4G, no need do relocate
//
if ((UINTN)RelocateImageUnder4GIfNeeded < 0xFFFFFFFF) {
return EFI_SUCCESS;
}
//
// If locate gEfiCallerIdGuid success, it means 2nd entry.
//
Status = gBS->LocateProtocol (&gEfiCallerIdGuid, NULL, &Interface);
if (!EFI_ERROR (Status)) {
DEBUG ((EFI_D_INFO, "FspNotifyDxe - 2nd entry\n"));
return EFI_SUCCESS;
}
DEBUG ((EFI_D_INFO, "FspNotifyDxe - 1st entry\n"));
//
// Here we install a dummy handle
//
NewImageHandle = NULL;
Status = gBS->InstallProtocolInterface (
&NewImageHandle,
&gEfiCallerIdGuid,
EFI_NATIVE_INTERFACE,
NULL
);
ASSERT_EFI_ERROR (Status);
//
// Reload image itself to <4G mem
//
Status = GetSectionFromAnyFv (
&gEfiCallerIdGuid,
EFI_SECTION_PE32,
0,
(VOID **) &Buffer,
&BufferSize
);
ASSERT_EFI_ERROR (Status);
ImageContext.Handle = Buffer;
ImageContext.ImageRead = PeCoffLoaderImageReadFromMemory;
//
// Get information about the image being loaded
//
Status = PeCoffLoaderGetImageInfo (&ImageContext);
ASSERT_EFI_ERROR (Status);
if (ImageContext.SectionAlignment > EFI_PAGE_SIZE) {
Pages = EFI_SIZE_TO_PAGES ((UINTN) (ImageContext.ImageSize + ImageContext.SectionAlignment));
} else {
Pages = EFI_SIZE_TO_PAGES ((UINTN) ImageContext.ImageSize);
}
FfsBuffer = 0xFFFFFFFF;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiBootServicesCode,
Pages,
&FfsBuffer
);
ASSERT_EFI_ERROR (Status);
ImageContext.ImageAddress = (PHYSICAL_ADDRESS)(UINTN)FfsBuffer;
//
// Align buffer on section boundary
//
ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;
ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)ImageContext.SectionAlignment - 1);
//
// Load the image to our new buffer
//
Status = PeCoffLoaderLoadImage (&ImageContext);
ASSERT_EFI_ERROR (Status);
//
// Relocate the image in our new buffer
//
Status = PeCoffLoaderRelocateImage (&ImageContext);
ASSERT_EFI_ERROR (Status);
//
// Free the buffer allocated by ReadSection since the image has been relocated in the new buffer
//
gBS->FreePool (Buffer);
//
// Flush the instruction cache so the image data is written before we execute it
//
InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize);
DEBUG ((EFI_D_INFO, "Loading driver at 0x%08x EntryPoint=0x%08x\n", (UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.EntryPoint));
Status = ((EFI_IMAGE_ENTRY_POINT)(UINTN)(ImageContext.EntryPoint)) (NewImageHandle, gST);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Error: Image at 0x%08x start failed: %r\n", ImageContext.ImageAddress, Status));
gBS->FreePages (FfsBuffer, Pages);
}
//
// return error to unload >4G copy, if we already relocate itself to <4G.
//
return EFI_ALREADY_STARTED;
}

193
IntelFspWrapperPkg/FspWrapperSecCore/FindPeiCore.c
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@ -1,193 +0,0 @@
/** @file
Locate the entry point for the PEI Core
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/BaseLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include "SecMain.h"
/**
Find core image base.
@param[in] BootFirmwareVolumePtr Point to the boot firmware volume.
@param[out] SecCoreImageBase The base address of the SEC core image.
@param[out] PeiCoreImageBase The base address of the PEI core image.
**/
EFI_STATUS
EFIAPI
FindImageBase (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,
OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
)
{
EFI_PHYSICAL_ADDRESS CurrentAddress;
EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
EFI_FFS_FILE_HEADER *File;
UINT32 Size;
EFI_PHYSICAL_ADDRESS EndOfFile;
EFI_COMMON_SECTION_HEADER *Section;
EFI_PHYSICAL_ADDRESS EndOfSection;
*SecCoreImageBase = 0;
*PeiCoreImageBase = 0;
CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;
EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;
//
// Loop through the FFS files in the Boot Firmware Volume
//
for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {
CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;
if (CurrentAddress > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
}
File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
if (IS_FFS_FILE2 (File)) {
Size = FFS_FILE2_SIZE (File);
if (Size <= 0x00FFFFFF) {
return EFI_NOT_FOUND;
}
} else {
Size = FFS_FILE_SIZE (File);
if (Size < sizeof (EFI_FFS_FILE_HEADER)) {
return EFI_NOT_FOUND;
}
}
EndOfFile = CurrentAddress + Size;
if (EndOfFile > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
}
//
// Look for SEC Core / PEI Core files
//
if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&
File->Type != EFI_FV_FILETYPE_PEI_CORE) {
continue;
}
//
// Loop through the FFS file sections within the FFS file
//
if (IS_FFS_FILE2 (File)) {
EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));
} else {
EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));
}
for (;;) {
CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;
Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
if (IS_SECTION2 (Section)) {
Size = SECTION2_SIZE (Section);
if (Size <= 0x00FFFFFF) {
return EFI_NOT_FOUND;
}
} else {
Size = SECTION_SIZE (Section);
if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {
return EFI_NOT_FOUND;
}
}
EndOfSection = CurrentAddress + Size;
if (EndOfSection > EndOfFile) {
return EFI_NOT_FOUND;
}
//
// Look for executable sections
//
if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {
if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {
if (IS_SECTION2 (Section)) {
*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));
} else {
*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
} else {
if (IS_SECTION2 (Section)) {
*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));
} else {
*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
}
break;
}
}
//
// Both SEC Core and PEI Core images found
//
if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {
return EFI_SUCCESS;
}
}
}
/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param[in] BootFirmwareVolumePtr Point to the boot firmware volume.
@param[out] PeiCoreEntryPoint The entry point of the PEI core.
**/
VOID
EFIAPI
FindAndReportEntryPoints (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS SecCoreImageBase;
EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
//
// Find SEC Core and PEI Core image base
//
Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);
ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));
//
// Report SEC Core debug information when remote debug is enabled
//
ImageContext.ImageAddress = SecCoreImageBase;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
//
// Report PEI Core debug information when remote debug is enabled
//
ImageContext.ImageAddress = PeiCoreImageBase;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
//
// Find PEI Core entry point
//
Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
if (EFI_ERROR (Status)) {
*PeiCoreEntryPoint = 0;
}
return;
}

61
IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf
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@ -1,61 +0,0 @@
## @file
# This is the first module taking control of the platform upon power-on/reset.
#
# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FspWrapperSecCore
FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09
MODULE_TYPE = SEC
VERSION_STRING = 1.0
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32
#
[Sources]
SecMain.c
SecMain.h
FindPeiCore.c
[Sources.IA32]
Ia32/ResetVec.asm16 | MSFT
Ia32/ResetVec.asm16 | INTEL
Ia32/Dummy.asm
[Binaries.Ia32]
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
IntelFspPkg/IntelFspPkg.dec
IntelFspWrapperPkg/IntelFspWrapperPkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
DebugLib
FspPlatformInfoLib
FspPlatformSecLib
DebugAgentLib
UefiCpuLib
PeCoffGetEntryPointLib
PeCoffExtraActionLib
[Ppis]
gTopOfTemporaryRamPpiGuid ## CONSUMES
[FixedPcd]
gFspWrapperTokenSpaceGuid.PcdSecCoreMaxPpiSupported ## CONSUMES
[Pcd]
gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES

20
IntelFspWrapperPkg/FspWrapperSecCore/Ia32/Dummy.asm
View File

@ -1,20 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; Dummy.asm
;
; Abstract:
;
; To pass build
;
;------------------------------------------------------------------------------
.586p
.model flat,C
.code
END

100
IntelFspWrapperPkg/FspWrapperSecCore/Ia32/ResetVec.asm16
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@ -1,100 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; ResetVec.asm
;
; Abstract:
;
; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
;------------------------------------------------------------------------------
.model tiny
.686p
.stack 0h
.code
;
; The layout of this file is fixed. The build tool makes assumption of the layout.
;
ORG 0h
;
; Reserved
;
ReservedData DD 0eeeeeeeeh, 0eeeeeeeeh
ORG 10h
;
; This is located at 0xFFFFFFD0h
;
mov di, "AP"
jmp ApStartup
ORG 20h
;
; Pointer to the entry point of the PEI core
; It is located at 0xFFFFFFE0, and is fixed up by some build tool
; So if the value 8..1 appears in the final FD image, tool failure occurs.
;
PeiCoreEntryPoint DD 87654321h
;
; This is the handler for all kinds of exceptions. Since it's for debugging
; purpose only, nothing except a deadloop would be done here. Developers could
; analyze the cause of the exception if a debugger had been attached.
;
InterruptHandler PROC
jmp $
iret
InterruptHandler ENDP
ORG 30h
;
; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte
; Execution starts here upon power-on/platform-reset.
;
ResetHandler:
nop
nop
ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
; SEC entry point relatvie address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm
;
DB 0e9h
DW -3
ORG 38h
;
; Ap reset vector segment address is at 0xFFFFFFF8
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs
;
ApSegAddress dd 12345678h
ORG 3ch
;
; BFV Base is at 0xFFFFFFFC
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs.
;
BfvBase DD 12345678h
;
; Nothing can go here, otherwise the layout of this file would change.
;
END

258
IntelFspWrapperPkg/FspWrapperSecCore/SecMain.c
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@ -1,258 +0,0 @@
/** @file
C functions in SEC
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SecMain.h"
EFI_PEI_PPI_DESCRIPTOR mPeiSecMainPpi[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gTopOfTemporaryRamPpiGuid,
NULL // To be patched later.
},
};
//
// These are IDT entries pointing to 10:FFFFFFE4h.
//
UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] Context The first input parameter of InitializeDebugAgent().
**/
VOID
EFIAPI
SecStartupPhase2(
IN VOID *Context
);
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
UINT32 PeiStackSize;
PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);
if (PeiStackSize == 0) {
PeiStackSize = (SizeOfRam >> 1);
}
ASSERT (PeiStackSize < SizeOfRam);
//
// Process all libraries constructor function linked to SecCore.
//
ProcessLibraryConstructorList ();
DEBUG ((DEBUG_INFO, "SecCore - SecStartup\n"));
//
// Initialize floating point operating environment
// to be compliant with UEFI spec.
//
InitializeFloatingPointUnits ();
// |-------------------|---->
// |Idt Table |
// |-------------------|
// |PeiService Pointer | PeiStackSize
// |-------------------|
// | |
// | Stack |
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporayRamSize
// | |
// | |
// |-------------------|----> TempRamBase
IdtTableInStack.PeiService = 0;
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));
}
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
// Update the base address and length of Pei temporary memory
//
SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;
SecCoreData.BootFirmwareVolumeSize = (UINTN)(SIZE_4GB - (UINTN) BootFirmwareVolume);
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
SecCoreData.TemporaryRamSize = SizeOfRam;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;
SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = PeiStackSize;
DEBUG ((DEBUG_INFO, "BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));
DEBUG ((DEBUG_INFO, "BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));
DEBUG ((DEBUG_INFO, "TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase));
DEBUG ((DEBUG_INFO, "TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize));
DEBUG ((DEBUG_INFO, "PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase));
DEBUG ((DEBUG_INFO, "PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize));
DEBUG ((DEBUG_INFO, "StackBase - 0x%x\n", SecCoreData.StackBase));
DEBUG ((DEBUG_INFO, "StackSize - 0x%x\n", SecCoreData.StackSize));
//
// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);
}
/**
This API patch the TopOfTemporaryRam value in SecPpiList.
@param[in,out] SecPpiList PPI list to be patched.
@param[in] TopOfTemporaryRam The top of CAR.
**/
VOID
PatchTopOfTemporaryRamPpi (
IN OUT EFI_PEI_PPI_DESCRIPTOR *SecPpiList,
IN VOID *TopOfTemporaryRam
)
{
SecPpiList[0].Ppi = TopOfTemporaryRam;
}
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] Context The first input parameter of InitializeDebugAgent().
**/
VOID
EFIAPI
SecStartupPhase2(
IN VOID *Context
)
{
EFI_SEC_PEI_HAND_OFF *SecCoreData;
EFI_PEI_PPI_DESCRIPTOR *PpiList;
UINT32 Index;
EFI_PEI_PPI_DESCRIPTOR LocalSecPpiList[sizeof(mPeiSecMainPpi)/sizeof(mPeiSecMainPpi[0])];
EFI_PEI_PPI_DESCRIPTOR AllSecPpiList[FixedPcdGet32(PcdSecCoreMaxPpiSupported)];
EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;
//
// Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug
// is enabled.
//
FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
if (PeiCoreEntryPoint == NULL)
{
CpuDeadLoop ();
}
CopyMem (LocalSecPpiList, mPeiSecMainPpi, sizeof(mPeiSecMainPpi));
PatchTopOfTemporaryRamPpi (LocalSecPpiList, (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize));
//
// Perform platform specific initialization before entering PeiCore.
//
PpiList = SecPlatformMain (SecCoreData);
if (PpiList != NULL) {
//
// Remove the terminal flag from the terminal Ppi
//
CopyMem (AllSecPpiList, LocalSecPpiList, sizeof (LocalSecPpiList));
for (Index = 0; Index < PcdGet32 (PcdSecCoreMaxPpiSupported); Index ++) {
if ((AllSecPpiList[Index].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) == EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) {
break;
}
}
AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
//
// Append the platform additional Ppi list
//
Index += 1;
while (Index < PcdGet32 (PcdSecCoreMaxPpiSupported) &&
((PpiList->Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST)) {
CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));
Index++;
PpiList++;
}
//
// Check whether the total Ppis exceeds the max supported Ppi.
//
if (Index >= PcdGet32 (PcdSecCoreMaxPpiSupported)) {
//
// the total Ppi is larger than the supported Max
// PcdSecCoreMaxPpiSupported can be enlarged to solve it.
//
CpuDeadLoop ();
} else {
//
// Add the terminal Ppi
//
CopyMem (&AllSecPpiList[Index], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));
}
//
// Set PpiList to the total Ppi
//
PpiList = &AllSecPpiList[0];
} else {
//
// No addition Ppi, PpiList directly point to the common Ppi list.
//
PpiList = &LocalSecPpiList[0];
}
//
// Transfer the control to the PEI core
//
ASSERT (PeiCoreEntryPoint != NULL);
(*PeiCoreEntryPoint) (SecCoreData, PpiList);
//
// Should not come here.
//
return ;
}

90
IntelFspWrapperPkg/FspWrapperSecCore/SecMain.h
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@ -1,90 +0,0 @@
/** @file
Master header file for SecCore.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _SEC_CORE_H_
#define _SEC_CORE_H_
#include <PiPei.h>
#include <Ppi/TopOfTemporaryRam.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/FspPlatformSecLib.h>
#include <Library/FspPlatformInfoLib.h>
#include <Library/UefiCpuLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/PeCoffExtraActionLib.h>
#include <Library/DebugAgentLib.h>
#include <FspApi.h>
#include <FspInfoHeader.h>
#define SEC_IDT_ENTRY_COUNT 34
typedef struct _SEC_IDT_TABLE {
//
// Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base
// address should be 8-byte alignment.
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
// EFI_PEI_SERVICES**
//
UINT64 PeiService;
UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];
} SEC_IDT_TABLE;
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
);
/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param[in] BootFirmwareVolumePtr Point to the boot firmware volume.
@param[out] PeiCoreEntryPoint Point to the PEI core entry point.
**/
VOID
EFIAPI
FindAndReportEntryPoints (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
);
/**
Autogenerated function that calls the library constructors for all of the module's
dependent libraries. This function must be called by the SEC Core once a stack has
been established.
**/
VOID
EFIAPI
ProcessLibraryConstructorList (
VOID
);
#endif

BIN
IntelFspWrapperPkg/FspWrapperSecCore/Vtf0/Bin/ResetVec.ia32.raw
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Binary file not shown.

47
IntelFspWrapperPkg/FspWrapperSecCore/Vtf0/Build.py
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@ -1,47 +0,0 @@
## @file
# Automate the process of building the various reset vector types
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
import glob
import os
import subprocess
import sys
def RunCommand(commandLine):
#print ' '.join(commandLine)
return subprocess.call(commandLine)
for filename in glob.glob(os.path.join('Bin', '*.raw')):
os.remove(filename)
arch = 'ia32'
debugType = None
output = os.path.join('Bin', 'ResetVec')
output += '.' + arch
if debugType is not None:
output += '.' + debugType
output += '.raw'
commandLine = (
'nasm',
'-D', 'ARCH_%s' % arch.upper(),
'-D', 'DEBUG_%s' % str(debugType).upper(),
'-o', output,
'ResetVectorCode.asm',
)
ret = RunCommand(commandLine)
print '\tASM\t' + output
if ret != 0: sys.exit(ret)
commandLine = (
'python',
'Tools/FixupForRawSection.py',
output,
)
print '\tFIXUP\t' + output
ret = RunCommand(commandLine)
if ret != 0: sys.exit(ret)

97
IntelFspWrapperPkg/FspWrapperSecCore/Vtf0/Ia16/ResetVec.asm16
View File

@ -1,97 +0,0 @@
;; @file
; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;;
BITS 16
;
; The layout of this file is fixed. The build tool makes assumption of the layout.
;
ORG 0x0
;
; Reserved
;
ReservedData: DD 0eeeeeeeeh, 0eeeeeeeeh
; ORG 0x10
TIMES 0x10-($-$$) DB 0
;
; This is located at 0xFFFFFFD0h
;
mov di, "AP"
jmp ApStartup
; ORG 0x20
TIMES 0x20-($-$$) DB 0
; Pointer to the entry point of the PEI core
; It is located at 0xFFFFFFE0, and is fixed up by some build tool
; So if the value 8..1 appears in the final FD image, tool failure occurs.
;
PeiCoreEntryPoint: DD 0x12345678
;
; This is the handler for all kinds of exceptions. Since it's for debugging
; purpose only, nothing except a deadloop would be done here. Developers could
; analyze the cause of the exception if a debugger had been attached.
;
InterruptHandler:
jmp $
iret
; ORG 0x30
TIMES 0x30-($-$$) DB 0
;
; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte
; Execution starts here upon power-on/platform-reset.
;
ResetHandler:
nop
nop
ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
; SEC entry point relatvie address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm
;
DB 0x0e9
DW -3
; ORG 0x38
TIMES 0x38-($-$$) DB 0
;
; Ap reset vector segment address is at 0xFFFFFFF8
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs
;
ApSegAddress: dd 0x12345678
; ORG 0x3c
TIMES 0x3c-($-$$) DB 0
;
; BFV Base is at 0xFFFFFFFC
; This will be fixed up by some build tool,
; so if the value 1..8 appears in the final FD image,
; tool failure occurs.
;
BfvBase: DD 0x12345678
;
; Nothing can go here, otherwise the layout of this file would change.
;
; END

11
IntelFspWrapperPkg/FspWrapperSecCore/Vtf0/ResetVectorCode.asm
View File

@ -1,11 +0,0 @@
;------------------------------------------------------------------------------
; @file
; This file includes all other code files to assemble the reset vector code
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
%include "Ia16/ResetVec.asm16"

104
IntelFspWrapperPkg/FspWrapperSecCore/Vtf0/Tools/FixupForRawSection.py
View File

@ -1,104 +0,0 @@
## @file
# Apply fixup to VTF binary image for FFS Raw section
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
import sys
filename = sys.argv[1]
if filename.lower().find('ia32') >= 0:
d = open(sys.argv[1], 'rb').read()
c = ((len(d) + 4 + 7) & ~7) - 4
if c > len(d):
c -= len(d)
f = open(sys.argv[1], 'wb')
f.write('\x90' * c)
f.write(d)
f.close()
else:
from struct import pack
PAGE_PRESENT = 0x01
PAGE_READ_WRITE = 0x02
PAGE_USER_SUPERVISOR = 0x04
PAGE_WRITE_THROUGH = 0x08
PAGE_CACHE_DISABLE = 0x010
PAGE_ACCESSED = 0x020
PAGE_DIRTY = 0x040
PAGE_PAT = 0x080
PAGE_GLOBAL = 0x0100
PAGE_2M_MBO = 0x080
PAGE_2M_PAT = 0x01000
def NopAlign4k(s):
c = ((len(s) + 0xfff) & ~0xfff) - len(s)
return ('\x90' * c) + s
def PageDirectoryEntries4GbOf2MbPages(baseAddress):
s = ''
for i in range(0x800):
i = (
baseAddress + long(i << 21) +
PAGE_2M_MBO +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_DIRTY +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
s = ''
for i in range(0x200):
i = (
pdeBase +
(min(i, 3) << 12) +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def PageMapLevel4Table4GbOf2MbPages(pdptBase):
s = ''
for i in range(0x200):
i = (
pdptBase +
(min(i, 0) << 12) +
PAGE_CACHE_DISABLE +
PAGE_ACCESSED +
PAGE_READ_WRITE +
PAGE_PRESENT
)
s += pack('Q', i)
return s
def First4GbPageEntries(topAddress):
PDE = PageDirectoryEntries4GbOf2MbPages(0L)
pml4tBase = topAddress - 0x1000
pdptBase = pml4tBase - 0x1000
pdeBase = pdptBase - len(PDE)
PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
return PDE + PDPT + PML4T
def AlignAndAddPageTables():
d = open(sys.argv[1], 'rb').read()
code = NopAlign4k(d)
topAddress = 0x100000000 - len(code)
d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
f = open(sys.argv[1], 'wb')
f.write(d)
f.close()
AlignAndAddPageTables()

103
IntelFspWrapperPkg/Include/Library/FspApiLib.h
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@ -1,103 +0,0 @@
/** @file
Provide FSP API related function.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_API_LIB_H__
#define __FSP_API_LIB_H__
#include <FspApi.h>
#include <FspInfoHeader.h>
/**
Find FSP header pointer.
@param[in] FlashFvFspBase Flash address of FSP FV.
@return FSP header pointer.
**/
FSP_INFO_HEADER *
EFIAPI
FspFindFspHeader (
IN EFI_PHYSICAL_ADDRESS FlashFvFspBase
);
/**
Call FSP API - FspInit.
@param[in] FspHeader FSP header pointer.
@param[in] FspInitParams Address pointer to the FSP_INIT_PARAMS structure.
@return EFI status returned by FspInit API.
**/
EFI_STATUS
EFIAPI
CallFspInit (
IN FSP_INFO_HEADER *FspHeader,
IN FSP_INIT_PARAMS *FspInitParams
);
/**
Call FSP API - FspNotifyPhase.
@param[in] FspHeader FSP header pointer.
@param[in] NotifyPhaseParams Address pointer to the NOTIFY_PHASE_PARAMS structure.
@return EFI status returned by FspNotifyPhase API.
**/
EFI_STATUS
EFIAPI
CallFspNotifyPhase (
IN FSP_INFO_HEADER *FspHeader,
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParams
);
/**
Call FSP API - FspMemoryInit.
@param[in] FspHeader FSP header pointer.
@param[in,out] FspMemoryInitParams Address pointer to the FSP_MEMORY_INIT_PARAMS structure.
@return EFI status returned by FspMemoryInit API.
**/
EFI_STATUS
EFIAPI
CallFspMemoryInit (
IN FSP_INFO_HEADER *FspHeader,
IN OUT FSP_MEMORY_INIT_PARAMS *FspMemoryInitParams
);
/**
Call FSP API - TempRamExit.
@param[in] FspHeader FSP header pointer.
@param[in,out] TempRamExitParam Address pointer to the TempRamExit parameters structure.
@return EFI status returned by TempRamExit API.
**/
EFI_STATUS
EFIAPI
CallTempRamExit (
IN FSP_INFO_HEADER *FspHeader,
IN OUT VOID *TempRamExitParam
);
/**
Call FSP API - FspSiliconInit.
@param[in] FspHeader FSP header pointer.
@param[in,out] FspSiliconInitParam Address pointer to the Silicon Init parameters structure.
@return EFI status returned by FspSiliconInit API.
**/
EFI_STATUS
EFIAPI
CallFspSiliconInit (
IN FSP_INFO_HEADER *FspHeader,
IN OUT VOID *FspSiliconInitParam
);
#endif

51
IntelFspWrapperPkg/Include/Library/FspHobProcessLib.h
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@ -1,51 +0,0 @@
/** @file
Provide FSP hob process related function.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_HOB_PROCESS_LIB_H__
#define __FSP_HOB_PROCESS_LIB_H__
/**
BIOS process FspBobList.
@param[in] FspHobList Pointer to the HOB data structure produced by FSP.
@return If platform process the FSP hob list successfully.
**/
EFI_STATUS
EFIAPI
FspHobProcess (
IN VOID *FspHobList
);
/**
BIOS process FspBobList for Memory Resource Descriptor.
@param[in] FspHobList Pointer to the HOB data structure produced by FSP.
@return If platform process the FSP hob list successfully.
**/
EFI_STATUS
EFIAPI
FspHobProcessForMemoryResource (
IN VOID *FspHobList
);
/**
BIOS process FspBobList for other data (not Memory Resource Descriptor).
@param[in] FspHobList Pointer to the HOB data structure produced by FSP.
@return If platform process the FSP hob list successfully.
**/
EFI_STATUS
EFIAPI
FspHobProcessForOtherData (
IN VOID *FspHobList
);
#endif

149
IntelFspWrapperPkg/Include/Library/FspPlatformInfoLib.h
View File

@ -1,149 +0,0 @@
/** @file
Provide FSP platform information related function.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FSP_PLATFORM_INFO_LIB_H__
#define __FSP_PLATFORM_INFO_LIB_H__
/**
Get current boot mode.
@note At this point, memory is ready, PeiServices are NOT available to use.
Platform can get some data from chipset register.
@return BootMode current boot mode.
**/
UINT32
EFIAPI
GetBootMode (
VOID
);
/**
Get NVS buffer parameter.
@note At this point, memory is NOT ready, PeiServices are available to use.
@return NvsBuffer NVS buffer parameter.
**/
VOID *
EFIAPI
GetNvsBuffer (
VOID
);
/**
Get UPD region size.
@note At this point, memory is NOT ready, PeiServices are available to use.
@return UPD region size.
**/
UINT32
EFIAPI
GetUpdRegionSize (
VOID
);
/**
This function overrides the default configurations in the UPD data region.
@param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strcture.
@return FspUpdRgnPtr A pointer to the UPD data region data strcture.
**/
VOID *
EFIAPI
UpdateFspUpdConfigs (
IN OUT VOID *FspUpdRgnPtr
);
/**
Get BootLoader Tolum size.
@note At this point, memory is NOT ready, PeiServices are available to use.
@return BootLoader Tolum size.
**/
UINT32
EFIAPI
GetBootLoaderTolumSize (
VOID
);
/**
Get TempRamExit parameter.
@note At this point, memory is ready, PeiServices are available to use.
@return TempRamExit parameter.
**/
VOID *
EFIAPI
GetTempRamExitParam (
VOID
);
/**
Get FspSiliconInit parameter.
@note At this point, memory is ready, PeiServices are available to use.
@return FspSiliconInit parameter.
**/
VOID *
EFIAPI
GetFspSiliconInitParam (
VOID
);
/**
Get S3 PEI memory information.
@note At this point, memory is ready, and PeiServices are available to use.
Platform can get some data from SMRAM directly.
@param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
@param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
@return If S3 PEI memory information is got successfully.
**/
EFI_STATUS
EFIAPI
GetS3MemoryInfo (
OUT UINT64 *S3PeiMemSize,
OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
);
/**
Get stack information according to boot mode.
@note If BootMode is BOOT_ON_S3_RESUME or BOOT_ON_FLASH_UPDATE,
this stack should be in some reserved memory space.
@note If FspInitDone is TRUE, memory is ready, but no PeiServices there.
Platform can get some data from SMRAM directly.
@note If FspInitDone is FALSE, memory is NOT ready, but PeiServices are available to use.
Platform can get some data from variable via VariablePpi.
@param[in] BootMode Current boot mode.
@param[in] FspInitDone If FspInit is called.
@param[out] StackSize Stack size to be used in PEI phase.
@param[out] StackBase Stack base to be used in PEI phase.
@return If Stack information is got successfully.
**/
EFI_STATUS
EFIAPI
GetStackInfo (
IN UINT32 BootMode,
IN BOOLEAN FspInitDone,
OUT UINT64 *StackSize,
OUT EFI_PHYSICAL_ADDRESS *StackBase
);
#endif

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