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IntelFsp2WrapperPkg: Add FSP*_ARCH_UPD.

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781

Provides sample code to include FSPT_ARCH_UPD initial values with
UPD header revision set to 2.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu 2020-06-18 20:59:37 +08:00 committed by mergify[bot]
parent 89f569ae8e
commit 1a99203052
1 changed files with 24 additions and 2 deletions
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26
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
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@ -1,7 +1,7 @@
/** @file /** @file
Sample to provide TempRamInitParams data. Sample to provide TempRamInitParams data.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -18,17 +18,39 @@ typedef struct {
typedef struct { typedef struct {
FSP_UPD_HEADER FspUpdHeader; FSP_UPD_HEADER FspUpdHeader;
//
// If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
//
FSPT_ARCH_UPD FsptArchUpd;
FSPT_CORE_UPD FsptCoreUpd; FSPT_CORE_UPD FsptCoreUpd;
} FSPT_UPD_CORE_DATA; } FSPT_UPD_CORE_DATA;
GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = { GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
{ {
0x4450555F54505346, 0x4450555F54505346,
0x00, //
// UPD header revision must be equal or greater than 2 when the structure is compliant with FSP spec 2.2.
//
0x02,
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
} }
}, },
//
// If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
//
{
0x01,
{
0x00, 0x00, 0x00
},
0x00000020,
0x00000000,
{
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
},
{ {
((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)), ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)), ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),