mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Unify the Secure and Normal FD and FV PCD naming
With this change, we now have these following PCDs values to define the location of the Secure and Normal firmwares: - gArmTokenSpaceGuid.PcdSecureFd(BaseAddress|Size) - gArmTokenSpaceGuid.PcdSecureFv(BaseAddress|Size) - gArmTokenSpaceGuid.PcdNormalFd(BaseAddress|Size) - gArmTokenSpaceGuid.PcdNormalFv(BaseAddress|Size) git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11806 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
9d074e739f
commit
1ad14bc86b
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@ -87,12 +87,16 @@
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#
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gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015
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gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
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gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F
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gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
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#
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# ARM Normal (or Non Secure) Firmware PCDs
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#
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0|UINT32|0x0000002B
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gArmTokenSpaceGuid.PcdNormalFdSize|0|UINT32|0x0000002C
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress|0|UINT32|0x0000002D
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gArmTokenSpaceGuid.PcdNormalFvSize|0|UINT32|0x0000002E
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# System Memory (DRAM): These PCDs define the region of in-built system memory
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# Some platforms can get DRAM extensions, these additional regions will be declared
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@ -340,10 +340,6 @@
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Size of SEC Stack for Normal World
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# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
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gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
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# System Memory (256MB)
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0x70000000
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gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000
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@ -344,10 +344,6 @@
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Stack for each of the 4 CPU cores
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# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
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gArmTokenSpaceGuid.PcdNormalFdSize|0x00100000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
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# System Memory (256MB)
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0x70000000
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gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000
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@ -27,8 +27,8 @@
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[FD.ArmRealViewEb_EFI]
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BaseAddress = 0x40000000 # The base address of the FLASH Device.
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Size = 0x00200000 # The size in bytes of the FLASH Device
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BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress
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Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize
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ErasePolarity = 1
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BlockSize = 0x00010000
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NumBlocks = 0x20
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@ -50,11 +50,11 @@ NumBlocks = 0x20
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################################################################################
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0x00000000|0x00050000
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gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
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gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
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FV = FVMAIN_SEC
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0x00050000|0x00100000
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize
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FV = FVMAIN_COMPACT
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################################################################################
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@ -27,8 +27,8 @@
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[FD.ArmRealViewEb_EFI]
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BaseAddress = 0x40000000 # The base address of the FLASH Device.
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Size = 0x00200000 # The size in bytes of the FLASH Device
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BaseAddress = 0x40000000|gArmTokenSpaceGuid.PcdNormalFdBaseAddress
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Size = 0x00200000|gArmTokenSpaceGuid.PcdNormalFdSize
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ErasePolarity = 1
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BlockSize = 0x00010000
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NumBlocks = 0x20
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@ -50,11 +50,11 @@ NumBlocks = 0x20
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################################################################################
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0x00000000|0x00050000
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gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
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gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
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FV = FVMAIN_SEC
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0x00050000|0x00100000
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvSize
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FV = FVMAIN_COMPACT
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################################################################################
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@ -27,10 +27,10 @@
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[FD.Sec_ArmVExpress_EFI]
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BaseAddress = 0x44000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device.
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Size = 0x00200000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
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Size = 0x00080000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
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ErasePolarity = 1
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BlockSize = 0x00001000
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NumBlocks = 0x200
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NumBlocks = 0x80
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################################################################################
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#
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@ -48,8 +48,8 @@ NumBlocks = 0x200
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#
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################################################################################
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0x00000000|0x00200000
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gEmbeddedTokenSpaceGuid.PcdFlashFvSecBase|gEmbeddedTokenSpaceGuid.PcdFlashFvSecSize
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0x00000000|0x00080000
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gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvBaseSize
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FV = FVMAIN_SEC
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@ -83,7 +83,7 @@ NumBlocks = 0x200
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################################################################################
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0x00000000|0x00200000
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress|gArmTokenSpaceGuid.PcdNormalFvBaseSize
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FV = FVMAIN_COMPACT
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@ -147,11 +147,10 @@ READ_LOCK_STATUS = TRUE
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INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
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INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
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INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
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INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
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INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
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INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
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INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
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INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
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INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
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INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
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INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
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INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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@ -78,7 +78,7 @@ Returns:
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BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));
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BuildFvHob (FixedPcdGet32(PcdFlashFvMainBase), FixedPcdGet32(PcdFlashFvMainSize));
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BuildFvHob (PcdGet32(PcdNormalFvBaseAddress), PcdGet32(PcdNormalFvSize));
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BootMode = ArmPlatformGetBootMode ();
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Status = (**PeiServices).SetBootMode (PeiServices, (UINT8) BootMode);
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@ -47,10 +47,12 @@
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gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
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[FixedPcd]
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress # The base address of the FLASH Device.
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gArmTokenSpaceGuid.PcdNormalFdSize # The size in bytes of the FLASH Device
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress
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gArmTokenSpaceGuid.PcdNormalFdSize
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress
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gArmTokenSpaceGuid.PcdNormalFvSize
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gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize
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gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
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@ -77,8 +77,8 @@ VOID primary_main (
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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@ -39,8 +39,8 @@ VOID primary_main (
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFdBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFdSize);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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@ -35,8 +35,8 @@ ASM_PFX(_ModuleEntryPoint):
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_SetupStack:
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# Setup Stack for the 4 CPU cores
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)
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mov r3,r0 @ r3 = core_id
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mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
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@ -55,7 +55,7 @@ _AllocateGlobalPeiVariables:
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_PrepareArguments:
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# The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
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LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
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add r2, r2, #4
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ldr r1, [r2]
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@ -53,7 +53,7 @@ _AllocateGlobalPeiVariables
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_PrepareArguments
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// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
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LoadConstantToReg (FixedPcdGet32(PcdNormalFvBaseAddress), r2)
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add r2, r2, #4
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ldr r1, [r2]
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@ -53,8 +53,8 @@
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gArmPlatformTokenSpaceGuid.PcdStandalone
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[FixedPcd]
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress
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gArmTokenSpaceGuid.PcdNormalFdSize
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress
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gArmTokenSpaceGuid.PcdNormalFvSize
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
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@ -42,7 +42,6 @@
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IoLib
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ArmLib
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ArmPlatformLib
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SerialPortLib
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[Ppis]
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gEfiTemporaryRamSupportPpiGuid
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@ -51,8 +50,8 @@
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gArmPlatformTokenSpaceGuid.PcdStandalone
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[FixedPcd]
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress
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gArmTokenSpaceGuid.PcdNormalFdSize
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress
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gArmTokenSpaceGuid.PcdNormalFvSize
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
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@ -121,18 +121,18 @@ CEntryPoint (
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// If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
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if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) {
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// Initialize system memory (DRAM)
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ArmPlatformInitializeSystemMemory();
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ArmPlatformInitializeSystemMemory ();
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}
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// Some platform can change their physical memory mapping
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ArmPlatformBootRemapping();
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ArmPlatformBootRemapping ();
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}
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// Test if Trustzone is supported on this platform
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if (ArmPlatformTrustzoneSupported()) {
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if (FixedPcdGet32(PcdMPCoreSupport)) {
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// Setup SMP in Non Secure world
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ArmSetupSmpNonSecure(CoreId);
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ArmSetupSmpNonSecure (CoreId);
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}
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// Enter Monitor Mode
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@ -206,7 +206,7 @@ CEntryPoint (
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// If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address
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if (FeaturePcdGet(PcdStandalone) == FALSE) {
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if (CoreId == ARM_PRIMARY_CORE) {
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress);
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UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
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// Patch the DRAM to make an infinite loop at the start address
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*StartAddress = 0xEAFFFFFE; // opcode for while(1)
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@ -215,7 +215,7 @@ CEntryPoint (
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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// To enter into Non Secure state, we need to make a return from exception
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return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
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return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
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} else {
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// When the primary core is stopped by the hardware debugger to copy the firmware
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// into DRAM. The secondary cores are still running. As soon as the first bytes of
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@ -229,7 +229,7 @@ CEntryPoint (
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}
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} else {
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// To enter into Non Secure state, we need to make a return from exception
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return_from_exception(PcdGet32(PcdNormalFdBaseAddress));
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return_from_exception(PcdGet32(PcdNormalFvBaseAddress));
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}
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//-------------------- Non Secure Mode ---------------------
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@ -247,7 +247,7 @@ NonSecureWaitForFirmware (
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VOID (*secondary_start)(VOID);
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// The secondary cores will execute the firmware once wake from WFI.
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secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress);
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secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress);
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ArmCallWFI();
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@ -52,7 +52,7 @@
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gArmTokenSpaceGuid.PcdVFPEnabled
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress
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gArmTokenSpaceGuid.PcdNormalFvBaseAddress
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize
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