mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmJunoPkg: Enable PCI and SATA support
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17414 6f19259b-4bc3-4df7-8a09-765794883524
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@ -129,6 +129,17 @@
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gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000
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#
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# PLDA PCI Root Complex
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#
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gArmPlatformTokenSpaceGuid.PcdPciBusMax|255
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gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x5f800000
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gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x00800000
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x50000000
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x08000000
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x4000000000
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x100000000
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# List of Device Paths that support BootMonFs
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gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)"
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@ -235,7 +246,24 @@
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MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
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MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
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# Required by PCI
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UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
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#
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# PCI Support
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#
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MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
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ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
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#
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# SATA Controller
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#
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MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
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EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
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#
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# Networking stack
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#
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EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
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#
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
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# Copyright (c) 2013-2015, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -142,6 +142,9 @@ READ_LOCK_STATUS = TRUE
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INF FatBinPkg/EnhancedFatDxe/Fat.inf
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INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
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# Required by PCI
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INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
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# FV FileSystem
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INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
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@ -154,6 +157,18 @@ READ_LOCK_STATUS = TRUE
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INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
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INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
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#
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# PCI Support
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#
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INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
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INF ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
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#
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# SATA Controller
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#
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INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
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INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
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#
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# Networking stack
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#
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@ -16,7 +16,9 @@
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#include <ArmPlatform.h>
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#include <Protocol/DevicePathFromText.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Guid/EventGroup.h>
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#include <Guid/GlobalVariable.h>
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#include <Library/ArmShellCmdLib.h>
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@ -54,6 +56,28 @@ STATIC EFI_STATUS SetJunoR1DefaultBootEntries (
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// This GUID must match the FILE_GUID in ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf
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STATIC CONST EFI_GUID mJunoAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } };
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typedef struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
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STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mPciRootComplexDevicePath = {
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{
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{ ACPI_DEVICE_PATH,
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ACPI_DP,
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{ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
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(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) }
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},
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EISA_PNP_ID (0x0A03),
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0
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{ END_DEVICE_PATH_LENGTH, 0 }
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}
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};
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/**
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* Build and Set UEFI Variable Boot####
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*
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@ -123,6 +147,46 @@ BootOptionCreate (
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);
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}
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/**
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Notification function of the event defined as belonging to the
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EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in
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the entry point of the driver.
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This function is called when an event belonging to the
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EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an
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event is signalled once at the end of the dispatching of all
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drivers (end of the so called DXE phase).
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@param[in] Event Event declared in the entry point of the driver whose
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notification function is being invoked.
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@param[in] Context NULL
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**/
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STATIC
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VOID
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OnEndOfDxe (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_DEVICE_PATH_PROTOCOL* PciRootComplexDevicePath;
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EFI_HANDLE Handle;
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EFI_STATUS Status;
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//
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// PCI Root Complex initialization
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// At the end of the DXE phase, we should get all the driver dispatched.
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// Force the PCI Root Complex to be initialized. It allows the OS to skip
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// this step.
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//
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PciRootComplexDevicePath = (EFI_DEVICE_PATH_PROTOCOL*) &mPciRootComplexDevicePath;
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Status = gBS->LocateDevicePath (&gEfiPciRootBridgeIoProtocolGuid,
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&PciRootComplexDevicePath,
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&Handle);
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Status = gBS->ConnectController (Handle, NULL, PciRootComplexDevicePath, FALSE);
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ASSERT_EFI_ERROR (Status);
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}
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EFI_STATUS
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EFIAPI
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ArmJunoEntryPoint (
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@ -183,6 +247,22 @@ ArmJunoEntryPoint (
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}
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}
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//
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// Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group.
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// The "OnEndOfDxe()" function is declared as the call back function.
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// It will be called at the end of the DXE phase when an event of the
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// same group is signalled to inform about the end of the DXE phase.
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// Install the INSTALL_FDT_PROTOCOL protocol.
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//
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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OnEndOfDxe,
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NULL,
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&gEfiEndOfDxeEventGroupGuid,
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&EndOfDxeEvent
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);
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// Install dynamic Shell command to run baremetal binaries.
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Status = ShellDynCmdRunAxfInstall (ImageHandle);
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if (EFI_ERROR (Status)) {
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@ -57,6 +57,7 @@
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gEfiBlockIoProtocolGuid
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gEfiDevicePathFromTextProtocolGuid
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gEfiPciIoProtocolGuid
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gEfiPciRootBridgeIoProtocolGuid
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gEfiSimpleFileSystemProtocolGuid
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[FixedPcd]
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@ -40,6 +40,9 @@
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#define ARM_JUNO_PERIPHERALS_BASE 0x20000000
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#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
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#define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000
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#define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB
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// On-Chip non-secure SRAM
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#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
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#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB
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#
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# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
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# Copyright (c) 2013-2015, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -52,3 +52,13 @@
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gArmTokenSpaceGuid.PcdFvBaseAddress
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress
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gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
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gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize
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[Pcd]
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Base
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gArmPlatformTokenSpaceGuid.PcdPciMmio32Size
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Base
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gArmPlatformTokenSpaceGuid.PcdPciMmio64Size
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
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* Copyright (c) 2013-2015, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -22,7 +22,7 @@
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#include <ArmPlatform.h>
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// The total number of descriptors, including the final "end-of-table" descriptor.
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_SRAM_SZ;
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VirtualMemoryTable[Index].Attributes = CacheAttributes;
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// PCI Root Complex
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPcieControlBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPcieControlBaseAddress);
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VirtualMemoryTable[Index].Length = SIZE_128KB;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// PCI Configuration Space
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//
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigurationSpaceSize);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// PCI Memory Space
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//
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
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VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// 64-bit PCI Memory Space
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//
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
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VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
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VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// Juno SOC peripherals
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VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
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VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
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