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ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> reg 

According to ARM Generic Interrupt Controller Architecture
Specification, GIC architecture version 3.0 and version 4.0,
GICD_IROUTER<n> is a 64-bit register.

Fixed code to use 64 bit MMIO write operations so that the
Aff3 value (bits [39:32]) is written to GICD_IROUTER<n>.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reported-by: Carl van Schaik <carl@cog.systems>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Sami Mujawar 2019-02-22 19:43:28 +00:00 committed by Ard Biesheuvel
parent 1342d7679e
commit 1bb76029ef
1 changed files with 2 additions and 2 deletions
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4
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * Copyright (c) 2011-2018, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -467,7 +467,7 @@ GicV3DxeInitialize (
// Route the SPIs to the primary CPU. SPIs start at the INTID 32 // Route the SPIs to the primary CPU. SPIs start at the INTID 32
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
MmioWrite32 ( MmioWrite64 (
mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
CpuTarget CpuTarget
); );