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	OvmfPkg: report support for the PIIX3 reset register in the FADT
The value to be written corresponds to hard reset, which is what the ACPI spec prescribes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14156 6f19259b-4bc3-4df7-8a09-765794883524
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				| @ -65,8 +65,8 @@ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = { | |||||||
|   0x0000,           // Boot architecture flag (16-bit) |   0x0000,           // Boot architecture flag (16-bit) | ||||||
|   RESERVED,         // reserved |   RESERVED,         // reserved | ||||||
|   FLAG,             // Fixed feature flags |   FLAG,             // Fixed feature flags | ||||||
|   { 0 },            // Address of the Reset Register |   GAS2_IO(RESET_REG, 1), // Extended address of the Reset Register | ||||||
|   0,                // Value for the Reset Register to reset the system |   RESET_VALUE,           // Value for the Reset Register to reset the system | ||||||
|   { RESERVED },     // reserved[3] |   { RESERVED },     // reserved[3] | ||||||
|   0,                // 64-bit physical addesss of FACS, set at installation |   0,                // 64-bit physical addesss of FACS, set at installation | ||||||
|   0,                // 64-bit physical addesss of DSDT, set at installation |   0,                // 64-bit physical addesss of DSDT, set at installation | ||||||
|  | |||||||
| @ -54,7 +54,10 @@ | |||||||
| #define FLAG            (EFI_ACPI_2_0_WBINVD | \ | #define FLAG            (EFI_ACPI_2_0_WBINVD | \ | ||||||
|                          EFI_ACPI_2_0_PROC_C1 | \ |                          EFI_ACPI_2_0_PROC_C1 | \ | ||||||
|                          EFI_ACPI_2_0_SLP_BUTTON | \ |                          EFI_ACPI_2_0_SLP_BUTTON | \ | ||||||
|                          EFI_ACPI_2_0_RTC_S4) |                          EFI_ACPI_2_0_RTC_S4 | \ | ||||||
|  |                          EFI_ACPI_2_0_RESET_REG_SUP) | ||||||
|  | #define RESET_REG       0xCF9 | ||||||
|  | #define RESET_VALUE     (BIT2 | BIT1) // PIIX3 Reset CPU + System Reset
 | ||||||
| 
 | 
 | ||||||
| //
 | //
 | ||||||
| // Byte-aligned IO port register block initializer for
 | // Byte-aligned IO port register block initializer for
 | ||||||
|  | |||||||
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