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ArmPkg: Fix ARM builds for XCode32 

- Build BeagleBoardPkg, ArmRealViewEb-A8, ArmRealView-A9x2 and ArmVExpress-CTA9x4




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12055 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-07-28 14:58:52 +00:00
parent 38d6bb9e71
commit 1d36ec02a5
9 changed files with 110 additions and 119 deletions
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211
ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.S
View File

@ -12,12 +12,12 @@
#
#------------------------------------------------------------------------------
.text
.align 2
GCC_ASM_EXPORT(__aeabi_uidiv)
GCC_ASM_EXPORT(__aeabi_uidivmod)
GCC_ASM_EXPORT(__aeabi_idiv)
GCC_ASM_EXPORT(__aeabi_idivmod)
.text
.align 2
GCC_ASM_EXPORT(__aeabi_uidiv)
GCC_ASM_EXPORT(__aeabi_uidivmod)
GCC_ASM_EXPORT(__aeabi_idiv)
GCC_ASM_EXPORT(__aeabi_idivmod)
# AREA Math, CODE, READONLY
@ -32,13 +32,13 @@
ASM_PFX(__aeabi_uidiv):
ASM_PFX(__aeabi_uidivmod):
RSBS r12, r1, r0, LSR #4
MOV r2, #0
BCC ASM_PFX(__arm_div4)
RSBS r12, r1, r0, LSR #8
BCC ASM_PFX(__arm_div8)
MOV r3, #0
B ASM_PFX(__arm_div_large)
rsbs r12, r1, r0, LSR #4
mov r2, #0
bcc ASM_PFX(__arm_div4)
rsbs r12, r1, r0, LSR #8
bcc ASM_PFX(__arm_div8)
mov r3, #0
b ASM_PFX(__arm_div_large)
#
#INT32
@ -50,107 +50,104 @@ ASM_PFX(__aeabi_uidivmod):
#
ASM_PFX(__aeabi_idiv):
ASM_PFX(__aeabi_idivmod):
ORRS r12, r0, r1
BMI ASM_PFX(__arm_div_negative)
RSBS r12, r1, r0, LSR #1
MOV r2, #0
BCC ASM_PFX(__arm_div1)
RSBS r12, r1, r0, LSR #4
BCC ASM_PFX(__arm_div4)
RSBS r12, r1, r0, LSR #8
BCC ASM_PFX(__arm_div8)
MOV r3, #0
B ASM_PFX(__arm_div_large)
orrs r12, r0, r1
bmi ASM_PFX(__arm_div_negative)
rsbs r12, r1, r0, LSR #1
mov r2, #0
bcc ASM_PFX(__arm_div1)
rsbs r12, r1, r0, LSR #4
bcc ASM_PFX(__arm_div4)
rsbs r12, r1, r0, LSR #8
bcc ASM_PFX(__arm_div8)
mov r3, #0
b ASM_PFX(__arm_div_large)
ASM_PFX(__arm_div8):
RSBS r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7
ADC r2, r2, r2
RSBS r12, r1, r0,LSR #6
SUBCS r0, r0, r1, LSL #6
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4
ADC r2, r2, r2
rsbs r12, r1, r0, LSR #7
subcs r0, r0, r1, LSL #7
adc r2, r2, r2
rsbs r12, r1, r0,LSR #6
subcs r0, r0, r1, LSL #6
adc r2, r2, r2
rsbs r12, r1, r0, LSR #5
subcs r0, r0, r1, LSL #5
adc r2, r2, r2
rsbs r12, r1, r0, LSR #4
subcs r0, r0, r1, LSL #4
adc r2, r2, r2
ASM_PFX(__arm_div4):
RSBS r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2
ADCS r2, r2, r2
RSBS r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1
ADC r2, r2, r2
rsbs r12, r1, r0, LSR #3
subcs r0, r0, r1, LSL #3
adc r2, r2, r2
rsbs r12, r1, r0, LSR #2
subcs r0, r0, r1, LSL #2
adcs r2, r2, r2
rsbs r12, r1, r0, LSR #1
subcs r0, r0, r1, LSL #1
adc r2, r2, r2
ASM_PFX(__arm_div1):
SUBS r1, r0, r1
MOVCC r1, r0
ADC r0, r2, r2
BX r14
subs r1, r0, r1
movcc r1, r0
adc r0, r2, r2
bx r14
ASM_PFX(__arm_div_negative):
ANDS r2, r1, #0x80000000
RSBMI r1, r1, #0
EORS r3, r2, r0, ASR #32
RSBCS r0, r0, #0
RSBS r12, r1, r0, LSR #4
BCC label1
RSBS r12, r1, r0, LSR #8
BCC label2
ands r2, r1, #0x80000000
rsbmi r1, r1, #0
eors r3, r2, r0, ASR #32
rsbcs r0, r0, #0
rsbs r12, r1, r0, LSR #4
bcc label1
rsbs r12, r1, r0, LSR #8
bcc label2
ASM_PFX(__arm_div_large):
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000000
BCC label2
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0x3f00000
BCC label2
LSL r1, r1, #6
RSBS r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000
ORRCS r2, r2, #0x3f00
LSLCS r1, r1, #6
RSBS r12, r1, #0
BCS ASM_PFX(__aeabi_idiv0)
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0xfc000000
bcc label2
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0x3f00000
bcc label2
lsl r1, r1, #6
rsbs r12, r1, r0, LSR #8
orr r2, r2, #0xfc000
orrcs r2, r2, #0x3f00
lslcs r1, r1, #6
rsbs r12, r1, #0
bcs ASM_PFX(__aeabi_idiv0)
label3:
LSRCS r1, r1, #6
lsrcs r1, r1, #6
label2:
RSBS r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #6
SUBCS r0, r0, r1, LSL #6
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4
ADC r2, r2, r2
rsbs r12, r1, r0, LSR #7
subcs r0, r0, r1, LSL #7
adc r2, r2, r2
rsbs r12, r1, r0, LSR #6
subcs r0, r0, r1, LSL #6
adc r2, r2, r2
rsbs r12, r1, r0, LSR #5
subcs r0, r0, r1, LSL #5
adc r2, r2, r2
rsbs r12, r1, r0, LSR #4
subcs r0, r0, r1, LSL #4
adc r2, r2, r2
label1:
RSBS r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3
ADC r2, r2, r2
RSBS r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2
ADCS r2, r2, r2
BCS label3
RSBS r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1
ADC r2, r2, r2
SUBS r1, r0, r1
MOVCC r1, r0
ADC r0, r2, r2
ASRS r3, r3, #31
RSBMI r0, r0, #0
RSBCS r1, r1, #0
BX r14
rsbs r12, r1, r0, LSR #3
subcs r0, r0, r1, LSL #3
adc r2, r2, r2
rsbs r12, r1, r0, LSR #2
subcs r0, r0, r1, LSL #2
adcs r2, r2, r2
bcs label3
rsbs r12, r1, r0, LSR #1
subcs r0, r0, r1, LSL #1
adc r2, r2, r2
subs r1, r0, r1
movcc r1, r0
adc r0, r2, r2
asrs r3, r3, #31
rsbmi r0, r0, #0
rsbcs r1, r1, #0
bx r14
@ What to do about division by zero? For now, just return.
@ What to do about division by zero? For now, just return.
ASM_PFX(__aeabi_idiv0):
BX r14
.end
bx r14

2
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.S
View File

@ -42,5 +42,3 @@ ASM_PFX(__aeabi_lmul):
mla r1, r2, r1, ip
mla r1, r3, lr, r1
ldmia sp!, {pc}
.end

1
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
View File

@ -90,7 +90,6 @@
Arm/switch32.S | GCC
Arm/sourcery.S | GCC
Arm/uldivmod.c | GCC
Arm/uldiv.S | GCC
Arm/ldivmod.S | GCC

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
View File

@ -237,7 +237,6 @@
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
View File

@ -240,7 +240,6 @@
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
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@ -250,6 +250,7 @@
ARMGCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
ARMGCC:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
################################################################################
#

6
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.S
View File

@ -76,8 +76,8 @@ ASM_PFX(ArmPlatformInitializeBootMemory):
// Initialize PL354 SMC
//
LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
ldr r2, =VersatileExpressSmcConfiguration
ldr r3, =VersatileExpressSmcConfigurationEnd
LoadConstantToReg (VersatileExpressSmcConfiguration, r2)
LoadConstantToReg (VersatileExpressSmcConfigurationEnd, r3)
blx ASM_PFX(PL35xSmcInitialize)
//
@ -97,7 +97,7 @@ ASM_PFX(ArmPlatformInitializeBootMemory):
ldr r0, [r2, #0]
ldr r0, = 0x00000000
str r0, [r2, #0]
ldr r0, = 0x00900090
LoadConstantToReg (0x00900090, r0)
str r0, [r2, #0]
// Confirm page mode enabled

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
View File

@ -67,5 +67,3 @@ _PrepareArguments:
# r0 = core_id
# r1 = pei_core_address
blx r2
.end

4
ArmPlatformPkg/Sec/SecEntryPoint.S
View File

@ -87,10 +87,10 @@ _InitMem:
_SetupStack:
# Setup Stack for the 4 CPU cores
#Read Stack Base address from PCD
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase) ,r1)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
#read Stack size from PCD
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize) ,r2)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
#calcuate Stack Pointer reg value using Stack size and CPU ID.
mov r3,r5 @ r3 = core_id