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ArmPkg: Fix ARM builds for XCode32 

- Build BeagleBoardPkg, ArmRealViewEb-A8, ArmRealView-A9x2 and ArmVExpress-CTA9x4




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12055 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-07-28 14:58:52 +00:00
parent 38d6bb9e71
commit 1d36ec02a5
9 changed files with 110 additions and 119 deletions
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209
ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.S
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@ -12,12 +12,12 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
.text .text
.align 2 .align 2
GCC_ASM_EXPORT(__aeabi_uidiv) GCC_ASM_EXPORT(__aeabi_uidiv)
GCC_ASM_EXPORT(__aeabi_uidivmod) GCC_ASM_EXPORT(__aeabi_uidivmod)
GCC_ASM_EXPORT(__aeabi_idiv) GCC_ASM_EXPORT(__aeabi_idiv)
GCC_ASM_EXPORT(__aeabi_idivmod) GCC_ASM_EXPORT(__aeabi_idivmod)
# AREA Math, CODE, READONLY # AREA Math, CODE, READONLY
@ -32,13 +32,13 @@
ASM_PFX(__aeabi_uidiv): ASM_PFX(__aeabi_uidiv):
ASM_PFX(__aeabi_uidivmod): ASM_PFX(__aeabi_uidivmod):
RSBS r12, r1, r0, LSR #4 rsbs r12, r1, r0, LSR #4
MOV r2, #0 mov r2, #0
BCC ASM_PFX(__arm_div4) bcc ASM_PFX(__arm_div4)
RSBS r12, r1, r0, LSR #8 rsbs r12, r1, r0, LSR #8
BCC ASM_PFX(__arm_div8) bcc ASM_PFX(__arm_div8)
MOV r3, #0 mov r3, #0
B ASM_PFX(__arm_div_large) b ASM_PFX(__arm_div_large)
# #
#INT32 #INT32
@ -50,107 +50,104 @@ ASM_PFX(__aeabi_uidivmod):
# #
ASM_PFX(__aeabi_idiv): ASM_PFX(__aeabi_idiv):
ASM_PFX(__aeabi_idivmod): ASM_PFX(__aeabi_idivmod):
ORRS r12, r0, r1 orrs r12, r0, r1
BMI ASM_PFX(__arm_div_negative) bmi ASM_PFX(__arm_div_negative)
RSBS r12, r1, r0, LSR #1 rsbs r12, r1, r0, LSR #1
MOV r2, #0 mov r2, #0
BCC ASM_PFX(__arm_div1) bcc ASM_PFX(__arm_div1)
RSBS r12, r1, r0, LSR #4 rsbs r12, r1, r0, LSR #4
BCC ASM_PFX(__arm_div4) bcc ASM_PFX(__arm_div4)
RSBS r12, r1, r0, LSR #8 rsbs r12, r1, r0, LSR #8
BCC ASM_PFX(__arm_div8) bcc ASM_PFX(__arm_div8)
MOV r3, #0 mov r3, #0
B ASM_PFX(__arm_div_large) b ASM_PFX(__arm_div_large)
ASM_PFX(__arm_div8): ASM_PFX(__arm_div8):
RSBS r12, r1, r0, LSR #7 rsbs r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7 subcs r0, r0, r1, LSL #7
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0,LSR #6 rsbs r12, r1, r0,LSR #6
SUBCS r0, r0, r1, LSL #6 subcs r0, r0, r1, LSL #6
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #5 rsbs r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5 subcs r0, r0, r1, LSL #5
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #4 rsbs r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4 subcs r0, r0, r1, LSL #4
ADC r2, r2, r2 adc r2, r2, r2
ASM_PFX(__arm_div4): ASM_PFX(__arm_div4):
RSBS r12, r1, r0, LSR #3 rsbs r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3 subcs r0, r0, r1, LSL #3
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #2 rsbs r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2 subcs r0, r0, r1, LSL #2
ADCS r2, r2, r2 adcs r2, r2, r2
RSBS r12, r1, r0, LSR #1 rsbs r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1 subcs r0, r0, r1, LSL #1
ADC r2, r2, r2 adc r2, r2, r2
ASM_PFX(__arm_div1): ASM_PFX(__arm_div1):
SUBS r1, r0, r1 subs r1, r0, r1
MOVCC r1, r0 movcc r1, r0
ADC r0, r2, r2 adc r0, r2, r2
BX r14 bx r14
ASM_PFX(__arm_div_negative): ASM_PFX(__arm_div_negative):
ANDS r2, r1, #0x80000000 ands r2, r1, #0x80000000
RSBMI r1, r1, #0 rsbmi r1, r1, #0
EORS r3, r2, r0, ASR #32 eors r3, r2, r0, ASR #32
RSBCS r0, r0, #0 rsbcs r0, r0, #0
RSBS r12, r1, r0, LSR #4 rsbs r12, r1, r0, LSR #4
BCC label1 bcc label1
RSBS r12, r1, r0, LSR #8 rsbs r12, r1, r0, LSR #8
BCC label2 bcc label2
ASM_PFX(__arm_div_large): ASM_PFX(__arm_div_large):
LSL r1, r1, #6 lsl r1, r1, #6
RSBS r12, r1, r0, LSR #8 rsbs r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000000 orr r2, r2, #0xfc000000
BCC label2 bcc label2
LSL r1, r1, #6 lsl r1, r1, #6
RSBS r12, r1, r0, LSR #8 rsbs r12, r1, r0, LSR #8
ORR r2, r2, #0x3f00000 orr r2, r2, #0x3f00000
BCC label2 bcc label2
LSL r1, r1, #6 lsl r1, r1, #6
RSBS r12, r1, r0, LSR #8 rsbs r12, r1, r0, LSR #8
ORR r2, r2, #0xfc000 orr r2, r2, #0xfc000
ORRCS r2, r2, #0x3f00 orrcs r2, r2, #0x3f00
LSLCS r1, r1, #6 lslcs r1, r1, #6
RSBS r12, r1, #0 rsbs r12, r1, #0
BCS ASM_PFX(__aeabi_idiv0) bcs ASM_PFX(__aeabi_idiv0)
label3: label3:
LSRCS r1, r1, #6 lsrcs r1, r1, #6
label2: label2:
RSBS r12, r1, r0, LSR #7 rsbs r12, r1, r0, LSR #7
SUBCS r0, r0, r1, LSL #7 subcs r0, r0, r1, LSL #7
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #6 rsbs r12, r1, r0, LSR #6
SUBCS r0, r0, r1, LSL #6 subcs r0, r0, r1, LSL #6
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #5 rsbs r12, r1, r0, LSR #5
SUBCS r0, r0, r1, LSL #5 subcs r0, r0, r1, LSL #5
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #4 rsbs r12, r1, r0, LSR #4
SUBCS r0, r0, r1, LSL #4 subcs r0, r0, r1, LSL #4
ADC r2, r2, r2 adc r2, r2, r2
label1: label1:
RSBS r12, r1, r0, LSR #3 rsbs r12, r1, r0, LSR #3
SUBCS r0, r0, r1, LSL #3 subcs r0, r0, r1, LSL #3
ADC r2, r2, r2 adc r2, r2, r2
RSBS r12, r1, r0, LSR #2 rsbs r12, r1, r0, LSR #2
SUBCS r0, r0, r1, LSL #2 subcs r0, r0, r1, LSL #2
ADCS r2, r2, r2 adcs r2, r2, r2
BCS label3 bcs label3
RSBS r12, r1, r0, LSR #1 rsbs r12, r1, r0, LSR #1
SUBCS r0, r0, r1, LSL #1 subcs r0, r0, r1, LSL #1
ADC r2, r2, r2 adc r2, r2, r2
SUBS r1, r0, r1 subs r1, r0, r1
MOVCC r1, r0 movcc r1, r0
ADC r0, r2, r2 adc r0, r2, r2
ASRS r3, r3, #31 asrs r3, r3, #31
RSBMI r0, r0, #0 rsbmi r0, r0, #0
RSBCS r1, r1, #0 rsbcs r1, r1, #0
BX r14 bx r14
@ What to do about division by zero? For now, just return. @ What to do about division by zero? For now, just return.
ASM_PFX(__aeabi_idiv0): ASM_PFX(__aeabi_idiv0):
BX r14 bx r14
.end

2
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.S
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@ -42,5 +42,3 @@ ASM_PFX(__aeabi_lmul):
mla r1, r2, r1, ip mla r1, r2, r1, ip
mla r1, r3, lr, r1 mla r1, r3, lr, r1
ldmia sp!, {pc} ldmia sp!, {pc}
.end

1
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
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@ -90,7 +90,6 @@
Arm/switch32.S | GCC Arm/switch32.S | GCC
Arm/sourcery.S | GCC Arm/sourcery.S | GCC
Arm/uldivmod.c | GCC
Arm/uldiv.S | GCC Arm/uldiv.S | GCC
Arm/ldivmod.S | GCC Arm/ldivmod.S | GCC

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
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@ -237,7 +237,6 @@
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
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@ -240,7 +240,6 @@
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
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@ -250,6 +250,7 @@
ARMGCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG ARMGCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
ARMGCC:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4 ARMGCC:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
################################################################################ ################################################################################
# #

6
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.S
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@ -76,8 +76,8 @@ ASM_PFX(ArmPlatformInitializeBootMemory):
// Initialize PL354 SMC // Initialize PL354 SMC
// //
LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
ldr r2, =VersatileExpressSmcConfiguration LoadConstantToReg (VersatileExpressSmcConfiguration, r2)
ldr r3, =VersatileExpressSmcConfigurationEnd LoadConstantToReg (VersatileExpressSmcConfigurationEnd, r3)
blx ASM_PFX(PL35xSmcInitialize) blx ASM_PFX(PL35xSmcInitialize)
// //
@ -97,7 +97,7 @@ ASM_PFX(ArmPlatformInitializeBootMemory):
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, = 0x00000000 ldr r0, = 0x00000000
str r0, [r2, #0] str r0, [r2, #0]
ldr r0, = 0x00900090 LoadConstantToReg (0x00900090, r0)
str r0, [r2, #0] str r0, [r2, #0]
// Confirm page mode enabled // Confirm page mode enabled

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
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@ -67,5 +67,3 @@ _PrepareArguments:
# r0 = core_id # r0 = core_id
# r1 = pei_core_address # r1 = pei_core_address
blx r2 blx r2
.end

4
ArmPlatformPkg/Sec/SecEntryPoint.S
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@ -87,10 +87,10 @@ _InitMem:
_SetupStack: _SetupStack:
# Setup Stack for the 4 CPU cores # Setup Stack for the 4 CPU cores
#Read Stack Base address from PCD #Read Stack Base address from PCD
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase) ,r1) LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
#read Stack size from PCD #read Stack size from PCD
LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize) ,r2) LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)
#calcuate Stack Pointer reg value using Stack size and CPU ID. #calcuate Stack Pointer reg value using Stack size and CPU ID.
mov r3,r5 @ r3 = core_id mov r3,r5 @ r3 = core_id