mirror of
https://github.com/acidanthera/audk.git
synced 2025-04-07 19:45:07 +02:00
Enable Idebus to use the Atapi.h defined in MdePkg/Include/IndustryStandard
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3220 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
qwang12
parent
8bdadcc8c0
commit
1e23bd8d8a
@ -72,7 +72,7 @@ ATAIdentify (
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IdeDev,
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(VOID *) AtaIdentifyPointer,
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sizeof (EFI_IDENTIFY_DATA),
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IDENTIFY_DRIVE_CMD,
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ATA_CMD_IDENTIFY_DRIVE,
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DeviceSelect,
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0,
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0,
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@ -191,7 +191,7 @@ AtaAtapi6Identify (
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Atapi6IdentifyStruct = IdeDev->pIdData;
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if ((Atapi6IdentifyStruct->AtapiData.cmd_set_support_83 & bit10) == 0) {
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if ((Atapi6IdentifyStruct->AtapiData.cmd_set_support_83 & BIT10) == 0) {
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//
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// The device dosn't support 48 bit addressing
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//
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@ -347,7 +347,7 @@ AtaPioDataIn (
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return EFI_DEVICE_ERROR;
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}
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if (AtaCommand == SET_FEATURES_CMD) {
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if (AtaCommand == ATA_CMD_SET_FEATURES) {
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x03);
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}
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@ -599,7 +599,7 @@ CheckErrorStatus (
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DEBUG_CODE_BEGIN ();
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if (StatusRegister & DWF) {
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if (StatusRegister & ATA_STSREG_DWF) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Write Fault\n",
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@ -607,7 +607,7 @@ CheckErrorStatus (
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);
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}
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if (StatusRegister & CORR) {
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if (StatusRegister & ATA_STSREG_CORR) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Corrected Data\n",
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@ -615,10 +615,10 @@ CheckErrorStatus (
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);
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}
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if (StatusRegister & ERR) {
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if (StatusRegister & ATA_STSREG_ERR) {
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ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
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if (ErrorRegister & BBK_ERR) {
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if (ErrorRegister & ATA_ERRREG_BBK) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Bad Block Detected\n",
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@ -626,7 +626,7 @@ CheckErrorStatus (
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);
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}
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if (ErrorRegister & UNC_ERR) {
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if (ErrorRegister & ATA_ERRREG_UNC) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Uncorrectable Data\n",
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@ -634,7 +634,7 @@ CheckErrorStatus (
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);
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}
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if (ErrorRegister & MC_ERR) {
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if (ErrorRegister & ATA_ERRREG_MC) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Media Change\n",
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@ -642,7 +642,7 @@ CheckErrorStatus (
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);
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}
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if (ErrorRegister & ABRT_ERR) {
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if (ErrorRegister & ATA_ERRREG_ABRT) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Abort\n",
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@ -650,7 +650,7 @@ CheckErrorStatus (
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);
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}
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if (ErrorRegister & TK0NF_ERR) {
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if (ErrorRegister & ATA_ERRREG_TK0NF) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Track 0 Not Found\n",
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@ -658,7 +658,7 @@ CheckErrorStatus (
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);
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}
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if (ErrorRegister & AMNF_ERR) {
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if (ErrorRegister & ATA_ERRREG_AMNF) {
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DEBUG (
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(EFI_D_BLKIO,
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"CheckErrorStatus()-- %02x : Error : Address Mark Not Found\n",
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@ -669,7 +669,7 @@ CheckErrorStatus (
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DEBUG_CODE_END ();
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if ((StatusRegister & (ERR | DWF | CORR)) == 0) {
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if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
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return EFI_SUCCESS;
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}
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@ -725,7 +725,7 @@ AtaReadSectors (
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//
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// Using ATA Read Sector(s) command (opcode=0x20) with PIO DATA IN protocol
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//
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AtaCommand = READ_SECTORS_CMD;
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AtaCommand = ATA_CMD_READ_SECTORS;
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BlocksRemaining = NumberOfBlocks;
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@ -843,7 +843,7 @@ AtaWriteSectors (
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//
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// Using Write Sector(s) command (opcode=0x30) with PIO DATA OUT protocol
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//
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AtaCommand = WRITE_SECTORS_CMD;
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AtaCommand = ATA_CMD_WRITE_SECTORS;
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BlocksRemaining = NumberOfBlocks;
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@ -936,12 +936,12 @@ AtaSoftReset (
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//
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// set SRST bit to initiate soft reset
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//
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DeviceControl |= SRST;
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DeviceControl |= ATA_CTLREG_SRST;
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//
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// disable Interrupt
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//
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DeviceControl |= bit1;
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DeviceControl |= BIT1;
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
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@ -1259,7 +1259,7 @@ AtaReadSectorsExt (
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//
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// Using ATA "Read Sectors Ext" command(opcode=0x24) with PIO DATA IN protocol
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//
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AtaCommand = READ_SECTORS_EXT_CMD;
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AtaCommand = ATA_CMD_READ_SECTORS_EXT;
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Buffer = DataBuffer;
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BlocksRemaining = NumberOfBlocks;
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Lba64 = StartLba;
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@ -1347,7 +1347,7 @@ AtaWriteSectorsExt (
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//
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// Using ATA "Write Sectors Ext" cmd(opcode=0x24) with PIO DATA OUT protocol
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//
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AtaCommand = WRITE_SECTORS_EXT_CMD;
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AtaCommand = ATA_CMD_WRITE_SECTORS_EXT;
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Lba64 = StartLba;
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Buffer = DataBuffer;
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BlocksRemaining = NumberOfBlocks;
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@ -1471,7 +1471,7 @@ AtaPioDataInExt (
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//
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// Fill feature register if needed
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//
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if (AtaCommand == SET_FEATURES_CMD) {
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if (AtaCommand == ATA_CMD_SET_FEATURES) {
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x03);
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}
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@ -1633,7 +1633,7 @@ AtaPioDataOutExt (
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//
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// Fill feature register if needed
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//
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if (AtaCommand == SET_FEATURES_CMD) {
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if (AtaCommand == ATA_CMD_SET_FEATURES) {
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x03);
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}
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@ -1781,7 +1781,7 @@ AtaSMARTSupport (
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Device = (UINT8) ((IdeDev->Device << 4) | 0xe0);
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Status = AtaNonDataCommandIn (
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IdeDev,
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ATA_SMART_CMD,
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ATA_CMD_SMART,
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Device,
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ATA_SMART_ENABLE_OPERATION,
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0,
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@ -1799,7 +1799,7 @@ AtaSMARTSupport (
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IdeDev,
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(VOID *) TmpAtaIdentifyPointer,
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sizeof (EFI_IDENTIFY_DATA),
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IDENTIFY_DRIVE_CMD,
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ATA_CMD_IDENTIFY_DRIVE,
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DeviceSelect,
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0,
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0,
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@ -1820,7 +1820,7 @@ AtaSMARTSupport (
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//
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AtaNonDataCommandIn (
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IdeDev,
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ATA_SMART_CMD,
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ATA_CMD_SMART,
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Device,
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ATA_SMART_RETURN_STATUS,
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0,
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@ -2273,24 +2273,24 @@ DoAtaUdma (
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switch (UdmaOp) {
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case AtaUdmaReadOp:
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MaxDmaCommandSectors = MAX_DMA_COMMAND_SECTORS;
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MaxDmaCommandSectors = ATAPI_MAX_DMA_CMD_SECTORS;
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PciIoProtocolOp = EfiPciIoOperationBusMasterWrite;
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AtaCommand = READ_DMA_CMD;
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AtaCommand = ATA_CMD_READ_DMA;
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break;
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case AtaUdmaReadExtOp:
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MaxDmaCommandSectors = MAX_DMA_EXT_COMMAND_SECTORS;
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MaxDmaCommandSectors = ATAPI_MAX_DMA_EXT_CMD_SECTORS;
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PciIoProtocolOp = EfiPciIoOperationBusMasterWrite;
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AtaCommand = READ_DMA_EXT_CMD;
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AtaCommand = ATA_CMD_READ_DMA_EXT;
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break;
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case AtaUdmaWriteOp:
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MaxDmaCommandSectors = MAX_DMA_COMMAND_SECTORS;
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MaxDmaCommandSectors = ATAPI_MAX_DMA_CMD_SECTORS;
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PciIoProtocolOp = EfiPciIoOperationBusMasterRead;
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AtaCommand = WRITE_DMA_CMD;
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AtaCommand = ATA_CMD_WRITE_DMA;
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break;
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case AtaUdmaWriteExtOp:
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MaxDmaCommandSectors = MAX_DMA_EXT_COMMAND_SECTORS;
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MaxDmaCommandSectors = ATAPI_MAX_DMA_EXT_CMD_SECTORS;
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PciIoProtocolOp = EfiPciIoOperationBusMasterRead;
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AtaCommand = WRITE_DMA_EXT_CMD;
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AtaCommand = ATA_CMD_WRITE_DMA_EXT;
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break;
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default:
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return EFI_UNSUPPORTED;
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@ -2617,7 +2617,7 @@ DoAtaUdma (
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// Disable interrupt of Select device
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//
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IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl);
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DeviceControl |= IEN_L;
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DeviceControl |= ATA_CTLREG_IEN_L;
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DeviceControl);
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return EFI_SUCCESS;
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@ -91,11 +91,11 @@ LS120GetMediaStatus (
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//
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StatusValue = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
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if (StatusValue & bit1) {
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if (StatusValue & BIT1) {
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return EFI_NO_MEDIA;
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}
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if (StatusValue & bit6) {
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if (StatusValue & BIT6) {
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return EFI_WRITE_PROTECTED;
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} else {
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return EFI_SUCCESS;
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@ -248,7 +248,7 @@ ATAPIIdentify (
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IdeDev,
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(VOID *) AtapiIdentifyPointer,
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sizeof (EFI_IDENTIFY_DATA),
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ATAPI_IDENTIFY_DEVICE_CMD,
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ATA_CMD_IDENTIFY_DEVICE,
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DeviceSelect,
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0,
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0,
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@ -355,7 +355,7 @@ ATAPIIdentify (
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//
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IdeDev->SenseDataNumber = 20;
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IdeDev->SenseData = AllocatePool (IdeDev->SenseDataNumber * sizeof (REQUEST_SENSE_DATA));
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IdeDev->SenseData = AllocatePool (IdeDev->SenseDataNumber * sizeof (ATAPI_REQUEST_SENSE_DATA));
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if (IdeDev->SenseData == NULL) {
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gBS->FreePool (IdeDev->pIdData);
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gBS->FreePool (IdeDev->pInquiryData);
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@ -395,17 +395,17 @@ AtapiInquiry (
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{
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ATAPI_PACKET_COMMAND Packet;
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EFI_STATUS Status;
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INQUIRY_DATA *InquiryData;
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ATAPI_INQUIRY_DATA *InquiryData;
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//
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// prepare command packet for the ATAPI Inquiry Packet Command.
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//
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ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
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Packet.Inquiry.opcode = INQUIRY;
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Packet.Inquiry.opcode = ATA_CMD_INQUIRY;
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Packet.Inquiry.page_code = 0;
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Packet.Inquiry.allocation_length = sizeof (INQUIRY_DATA);
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Packet.Inquiry.allocation_length = sizeof (ATAPI_INQUIRY_DATA);
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InquiryData = AllocatePool (sizeof (INQUIRY_DATA));
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InquiryData = AllocatePool (sizeof (ATAPI_INQUIRY_DATA));
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if (InquiryData == NULL) {
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return EFI_DEVICE_ERROR;
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}
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@ -417,7 +417,7 @@ AtapiInquiry (
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IdeDev,
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&Packet,
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(UINT16 *) InquiryData,
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sizeof (INQUIRY_DATA),
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sizeof (ATAPI_INQUIRY_DATA),
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ATAPITIMEOUT
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);
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if (EFI_ERROR (Status)) {
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@ -488,7 +488,7 @@ AtapiPacketCommandIn (
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IDEWritePortB (
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IdeDev->PciIo,
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IdeDev->IoPort->Head,
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(UINT8) ((IdeDev->Device << 4) | DEFAULT_CMD) // DEFAULT_CMD: 0xa0 (1010,0000)
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(UINT8) ((IdeDev->Device << 4) | ATA_DEFAULT_CMD) // DEFAULT_CMD: 0xa0 (1010,0000)
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);
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//
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@ -497,31 +497,31 @@ AtapiPacketCommandIn (
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x00);
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//
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// set the transfersize to MAX_ATAPI_BYTE_COUNT to let the device
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// set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
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// determine how many data should be transferred.
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//
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IDEWritePortB (
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IdeDev->PciIo,
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IdeDev->IoPort->CylinderLsb,
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(UINT8) (MAX_ATAPI_BYTE_COUNT & 0x00ff)
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(UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff)
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);
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IDEWritePortB (
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IdeDev->PciIo,
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IdeDev->IoPort->CylinderMsb,
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(UINT8) (MAX_ATAPI_BYTE_COUNT >> 8)
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(UINT8) (ATAPI_MAX_BYTE_COUNT >> 8)
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);
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//
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// DEFAULT_CTL:0x0a (0000,1010)
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// ATA_DEFAULT_CTL:0x0a (0000,1010)
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// Disable interrupt
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//
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DEFAULT_CTL);
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, ATA_DEFAULT_CTL);
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//
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// Send Packet command to inform device
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// that the following data bytes are command packet.
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//
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, PACKET_CMD);
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, ATA_CMD_PACKET);
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Status = DRQReady (IdeDev, ATAPITIMEOUT);
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if (EFI_ERROR (Status)) {
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@ -603,7 +603,7 @@ AtapiPacketCommandOut (
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IDEWritePortB (
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IdeDev->PciIo,
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IdeDev->IoPort->Head,
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(UINT8) ((IdeDev->Device << 4) | DEFAULT_CMD) // DEFAULT_CMD: 0xa0 (1010,0000)
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(UINT8) ((IdeDev->Device << 4) | ATA_DEFAULT_CMD) // ATA_DEFAULT_CMD: 0xa0 (1010,0000)
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);
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//
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@ -612,31 +612,31 @@ AtapiPacketCommandOut (
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Feature, 0x00);
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//
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// set the transfersize to MAX_ATAPI_BYTE_COUNT to
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// set the transfersize to ATAPI_MAX_BYTE_COUNT to
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// let the device determine how many data should be transferred.
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//
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IDEWritePortB (
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IdeDev->PciIo,
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IdeDev->IoPort->CylinderLsb,
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(UINT8) (MAX_ATAPI_BYTE_COUNT & 0x00ff)
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(UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff)
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);
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IDEWritePortB (
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IdeDev->PciIo,
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IdeDev->IoPort->CylinderMsb,
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(UINT8) (MAX_ATAPI_BYTE_COUNT >> 8)
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(UINT8) (ATAPI_MAX_BYTE_COUNT >> 8)
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);
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//
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// DEFAULT_CTL:0x0a (0000,1010)
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// Disable interrupt
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//
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, DEFAULT_CTL);
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Alt.DeviceControl, ATA_DEFAULT_CTL);
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//
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// Send Packet command to inform device
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// that the following data bytes are command packet.
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//
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, PACKET_CMD);
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IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, ATA_CMD_PACKET);
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Status = DRQReady2 (IdeDev, ATAPITIMEOUT);
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if (EFI_ERROR (Status)) {
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@ -826,7 +826,7 @@ AtapiTestUnitReady (
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// fill command packet
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//
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ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
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Packet.TestUnitReady.opcode = TEST_UNIT_READY;
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Packet.TestUnitReady.opcode = ATA_CMD_TEST_UNIT_READY;
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//
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// send command packet
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@ -879,20 +879,20 @@ AtapiRequestSense (
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)
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{
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EFI_STATUS Status;
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REQUEST_SENSE_DATA *Sense;
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ATAPI_REQUEST_SENSE_DATA *Sense;
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UINT16 *Ptr;
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BOOLEAN FetchSenseData;
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ATAPI_PACKET_COMMAND Packet;
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*SenseCounts = 0;
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ZeroMem (IdeDev->SenseData, sizeof (REQUEST_SENSE_DATA) * (IdeDev->SenseDataNumber));
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ZeroMem (IdeDev->SenseData, sizeof (ATAPI_REQUEST_SENSE_DATA) * (IdeDev->SenseDataNumber));
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//
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// fill command packet for Request Sense Packet Command
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//
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ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
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Packet.RequestSence.opcode = REQUEST_SENSE;
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Packet.RequestSence.allocation_length = sizeof (REQUEST_SENSE_DATA);
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||||
Packet.RequestSence.opcode = ATA_CMD_REQUEST_SENSE;
|
||||
Packet.RequestSence.allocation_length = sizeof (ATAPI_REQUEST_SENSE_DATA);
|
||||
|
||||
//
|
||||
// initialize pointer
|
||||
@ -904,7 +904,7 @@ AtapiRequestSense (
|
||||
//
|
||||
for (FetchSenseData = TRUE; FetchSenseData;) {
|
||||
|
||||
Sense = (REQUEST_SENSE_DATA *) Ptr;
|
||||
Sense = (ATAPI_REQUEST_SENSE_DATA *) Ptr;
|
||||
|
||||
//
|
||||
// send out Request Sense Packet Command and get one Sense data form device
|
||||
@ -913,7 +913,7 @@ AtapiRequestSense (
|
||||
IdeDev,
|
||||
&Packet,
|
||||
Ptr,
|
||||
sizeof (REQUEST_SENSE_DATA),
|
||||
sizeof (ATAPI_REQUEST_SENSE_DATA),
|
||||
ATAPITIMEOUT
|
||||
);
|
||||
//
|
||||
@ -934,11 +934,11 @@ AtapiRequestSense (
|
||||
// In this case, dead loop occurs if we don't have a gatekeeper. 20 is
|
||||
// supposed to be large enough for any ATAPI device.
|
||||
//
|
||||
if ((Sense->sense_key != SK_NO_SENSE) && ((*SenseCounts) < 20)) {
|
||||
if ((Sense->sense_key != ATA_SK_NO_SENSE) && ((*SenseCounts) < 20)) {
|
||||
//
|
||||
// Ptr is word-based pointer
|
||||
//
|
||||
Ptr += (sizeof (REQUEST_SENSE_DATA) + 1) >> 1;
|
||||
Ptr += (sizeof (ATAPI_REQUEST_SENSE_DATA) + 1) >> 1;
|
||||
|
||||
} else {
|
||||
//
|
||||
@ -989,8 +989,8 @@ AtapiReadCapacity (
|
||||
//
|
||||
// used for capacity data returned from ATAPI device
|
||||
//
|
||||
READ_CAPACITY_DATA Data;
|
||||
READ_FORMAT_CAPACITY_DATA FormatData;
|
||||
ATAPI_READ_CAPACITY_DATA Data;
|
||||
ATAPI_READ_FORMAT_CAPACITY_DATA FormatData;
|
||||
|
||||
*SenseCount = 0;
|
||||
|
||||
@ -1000,12 +1000,12 @@ AtapiReadCapacity (
|
||||
if (IdeDev->Type == IdeCdRom) {
|
||||
|
||||
ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
|
||||
Packet.Inquiry.opcode = READ_CAPACITY;
|
||||
Packet.Inquiry.opcode = ATA_CMD_READ_CAPACITY;
|
||||
Status = AtapiPacketCommandIn (
|
||||
IdeDev,
|
||||
&Packet,
|
||||
(UINT16 *) &Data,
|
||||
sizeof (READ_CAPACITY_DATA),
|
||||
sizeof (ATAPI_READ_CAPACITY_DATA),
|
||||
ATAPITIMEOUT
|
||||
);
|
||||
|
||||
@ -1014,13 +1014,13 @@ AtapiReadCapacity (
|
||||
// Type == IdeMagnetic
|
||||
//
|
||||
ZeroMem (&Packet, sizeof (ATAPI_PACKET_COMMAND));
|
||||
Packet.ReadFormatCapacity.opcode = READ_FORMAT_CAPACITY;
|
||||
Packet.ReadFormatCapacity.opcode = ATA_CMD_READ_FORMAT_CAPACITY;
|
||||
Packet.ReadFormatCapacity.allocation_length_lo = 12;
|
||||
Status = AtapiPacketCommandIn (
|
||||
IdeDev,
|
||||
&Packet,
|
||||
(UINT16 *) &FormatData,
|
||||
sizeof (READ_FORMAT_CAPACITY_DATA),
|
||||
sizeof (ATAPI_READ_FORMAT_CAPACITY_DATA),
|
||||
ATAPITIMEOUT
|
||||
);
|
||||
}
|
||||
@ -1408,7 +1408,7 @@ AtapiReadSectors (
|
||||
{
|
||||
|
||||
ATAPI_PACKET_COMMAND Packet;
|
||||
READ10_CMD *Read10Packet;
|
||||
ATAPI_READ10_CMD *Read10Packet;
|
||||
EFI_STATUS Status;
|
||||
UINTN BlocksRemaining;
|
||||
UINT32 Lba32;
|
||||
@ -1451,7 +1451,7 @@ AtapiReadSectors (
|
||||
// fill the Packet data structure
|
||||
//
|
||||
|
||||
Read10Packet->opcode = READ_10;
|
||||
Read10Packet->opcode = ATA_CMD_READ_10;
|
||||
|
||||
//
|
||||
// Lba0 ~ Lba3 specify the start logical block address of the data transfer.
|
||||
@ -1533,7 +1533,7 @@ AtapiWriteSectors (
|
||||
{
|
||||
|
||||
ATAPI_PACKET_COMMAND Packet;
|
||||
READ10_CMD *Read10Packet;
|
||||
ATAPI_READ10_CMD *Read10Packet;
|
||||
|
||||
EFI_STATUS Status;
|
||||
UINTN BlocksRemaining;
|
||||
@ -1578,7 +1578,7 @@ AtapiWriteSectors (
|
||||
//
|
||||
// Command code is WRITE_10.
|
||||
//
|
||||
Read10Packet->opcode = WRITE_10;
|
||||
Read10Packet->opcode = ATA_CMD_WRITE_10;
|
||||
|
||||
//
|
||||
// Lba0 ~ Lba3 specify the start logical block address of the data transfer.
|
||||
@ -1653,10 +1653,10 @@ AtapiSoftReset (
|
||||
// for ATAPI device, no need to wait DRDY ready after device selecting.
|
||||
// (bit7 and bit5 are both set to 1 for backward compatibility)
|
||||
//
|
||||
DeviceSelect = (UINT8) (((bit7 | bit5) | (IdeDev->Device << 4)));
|
||||
DeviceSelect = (UINT8) (((BIT7 | BIT5) | (IdeDev->Device << 4)));
|
||||
IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Head, DeviceSelect);
|
||||
|
||||
Command = ATAPI_SOFT_RESET_CMD;
|
||||
Command = ATA_CMD_SOFT_RESET;
|
||||
IDEWritePortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Command, Command);
|
||||
|
||||
//
|
||||
@ -1998,7 +1998,7 @@ ParseSenseData (
|
||||
OUT SENSE_RESULT *Result
|
||||
)
|
||||
{
|
||||
REQUEST_SENSE_DATA *SenseData;
|
||||
ATAPI_REQUEST_SENSE_DATA *SenseData;
|
||||
|
||||
if (SenseCount == 0) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
@ -2011,19 +2011,19 @@ ParseSenseData (
|
||||
*Result = SenseOtherSense;
|
||||
|
||||
switch (SenseData->sense_key) {
|
||||
case SK_NO_SENSE:
|
||||
case ATA_SK_NO_SENSE:
|
||||
*Result = SenseNoSenseKey;
|
||||
break;
|
||||
case SK_NOT_READY:
|
||||
case ATA_SK_NOT_READY:
|
||||
switch (SenseData->addnl_sense_code) {
|
||||
case ASC_NO_MEDIA:
|
||||
case ATA_ASC_NO_MEDIA:
|
||||
*Result = SenseNoMedia;
|
||||
break;
|
||||
case ASC_MEDIA_UPSIDE_DOWN:
|
||||
case ATA_ASC_MEDIA_UPSIDE_DOWN:
|
||||
*Result = SenseMediaError;
|
||||
break;
|
||||
case ASC_NOT_READY:
|
||||
if (SenseData->addnl_sense_code_qualifier == ASCQ_IN_PROGRESS) {
|
||||
case ATA_ASC_NOT_READY:
|
||||
if (SenseData->addnl_sense_code_qualifier == ATA_ASCQ_IN_PROGRESS) {
|
||||
*Result = SenseDeviceNotReadyNeedRetry;
|
||||
} else {
|
||||
*Result = SenseDeviceNotReadyNoRetry;
|
||||
@ -2031,17 +2031,17 @@ ParseSenseData (
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case SK_UNIT_ATTENTION:
|
||||
if (SenseData->addnl_sense_code == ASC_MEDIA_CHANGE) {
|
||||
case ATA_SK_UNIT_ATTENTION:
|
||||
if (SenseData->addnl_sense_code == ATA_ASC_MEDIA_CHANGE) {
|
||||
*Result = SenseMediaChange;
|
||||
}
|
||||
break;
|
||||
case SK_MEDIUM_ERROR:
|
||||
case ATA_SK_MEDIUM_ERROR:
|
||||
switch (SenseData->addnl_sense_code) {
|
||||
case ASC_MEDIA_ERR1:
|
||||
case ASC_MEDIA_ERR2:
|
||||
case ASC_MEDIA_ERR3:
|
||||
case ASC_MEDIA_ERR4:
|
||||
case ATA_ASC_MEDIA_ERR1:
|
||||
case ATA_ASC_MEDIA_ERR2:
|
||||
case ATA_ASC_MEDIA_ERR3:
|
||||
case ATA_ASC_MEDIA_ERR4:
|
||||
*Result = SenseMediaError;
|
||||
break;
|
||||
}
|
||||
@ -2071,12 +2071,12 @@ AtapiReadPendingData (
|
||||
UINT16 TempWordBuffer;
|
||||
|
||||
AltRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus);
|
||||
if ((AltRegister & BSY) == BSY) {
|
||||
if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {
|
||||
return EFI_NOT_READY;
|
||||
}
|
||||
if ((AltRegister & (BSY | DRQ)) == DRQ) {
|
||||
if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
|
||||
TempWordBuffer = IDEReadPortB (IdeDev->PciIo,IdeDev->IoPort->Alt.AltStatus);
|
||||
while ((TempWordBuffer & (BSY | DRQ)) == DRQ) {
|
||||
while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
|
||||
IDEReadPortWMultiple (
|
||||
IdeDev->PciIo,
|
||||
IdeDev->IoPort->Data,
|
||||
|
||||
@ -315,8 +315,8 @@ GetIdeRegistersBaseAddr (
|
||||
//
|
||||
// The BARs should be of IO type
|
||||
//
|
||||
if ((PciData.Device.Bar[0] & bit0) == 0 ||
|
||||
(PciData.Device.Bar[1] & bit0) == 0) {
|
||||
if ((PciData.Device.Bar[0] & BIT0) == 0 ||
|
||||
(PciData.Device.Bar[1] & BIT0) == 0) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
@ -337,8 +337,8 @@ GetIdeRegistersBaseAddr (
|
||||
//
|
||||
// The BARs should be of IO type
|
||||
//
|
||||
if ((PciData.Device.Bar[2] & bit0) == 0 ||
|
||||
(PciData.Device.Bar[3] & bit0) == 0) {
|
||||
if ((PciData.Device.Bar[2] & BIT0) == 0 ||
|
||||
(PciData.Device.Bar[3] & BIT0) == 0) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
@ -709,8 +709,8 @@ DetectIDEController (
|
||||
// NOTE: This workaround doesn't apply to ATAPI.
|
||||
//
|
||||
if (MasterDeviceExist && SlaveDeviceExist &&
|
||||
(StatusReg & DRDY) == 0 &&
|
||||
(InitStatusReg & DRDY) == 0 &&
|
||||
(StatusReg & ATA_STSREG_DRDY) == 0 &&
|
||||
(InitStatusReg & ATA_STSREG_DRDY) == 0 &&
|
||||
MasterDeviceType == SlaveDeviceType &&
|
||||
SlaveDeviceType != ATAPI_DEVICE_TYPE) {
|
||||
SlaveDeviceExist = FALSE;
|
||||
@ -768,14 +768,14 @@ DRQClear (
|
||||
//
|
||||
// wait for BSY == 0 and DRQ == 0
|
||||
//
|
||||
if ((StatusRegister & (DRQ | BSY)) == 0) {
|
||||
if ((StatusRegister & (ATA_STSREG_DRQ | ATA_STSREG_BSY)) == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((StatusRegister & (BSY | ERR)) == ERR) {
|
||||
if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
|
||||
|
||||
ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
|
||||
if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
}
|
||||
@ -842,14 +842,14 @@ DRQClear2 (
|
||||
//
|
||||
// wait for BSY == 0 and DRQ == 0
|
||||
//
|
||||
if ((AltRegister & (DRQ | BSY)) == 0) {
|
||||
if ((AltRegister & (ATA_STSREG_DRQ | ATA_STSREG_BSY)) == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((AltRegister & (BSY | ERR)) == ERR) {
|
||||
if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
|
||||
|
||||
ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
|
||||
if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
}
|
||||
@ -921,14 +921,14 @@ DRQReady (
|
||||
//
|
||||
// BSY==0,DRQ==1
|
||||
//
|
||||
if ((StatusRegister & (BSY | DRQ)) == DRQ) {
|
||||
if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((StatusRegister & (BSY | ERR)) == ERR) {
|
||||
if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
|
||||
|
||||
ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
|
||||
if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
}
|
||||
@ -998,14 +998,14 @@ DRQReady2 (
|
||||
//
|
||||
// BSY == 0 , DRQ == 1
|
||||
//
|
||||
if ((AltRegister & (BSY | DRQ)) == DRQ) {
|
||||
if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((AltRegister & (BSY | ERR)) == ERR) {
|
||||
if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
|
||||
|
||||
ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
|
||||
if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
}
|
||||
@ -1064,7 +1064,7 @@ WaitForBSYClear (
|
||||
do {
|
||||
|
||||
StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);
|
||||
if ((StatusRegister & BSY) == 0x00) {
|
||||
if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1124,7 +1124,7 @@ WaitForBSYClear2 (
|
||||
Delay = (UINT32) (((TimeoutInMilliSeconds * STALL_1_MILLI_SECOND) / 30) + 1);
|
||||
do {
|
||||
AltRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Alt.AltStatus);
|
||||
if ((AltRegister & BSY) == 0x00) {
|
||||
if ((AltRegister & ATA_STSREG_BSY) == 0x00) {
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1188,14 +1188,14 @@ DRDYReady (
|
||||
//
|
||||
// BSY == 0 , DRDY == 1
|
||||
//
|
||||
if ((StatusRegister & (DRDY | BSY)) == DRDY) {
|
||||
if ((StatusRegister & (ATA_STSREG_DRDY | ATA_STSREG_BSY)) == ATA_STSREG_DRDY) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((StatusRegister & (BSY | ERR)) == ERR) {
|
||||
if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
|
||||
|
||||
ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
|
||||
if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
}
|
||||
@ -1259,14 +1259,14 @@ DRDYReady2 (
|
||||
//
|
||||
// BSY == 0 , DRDY == 1
|
||||
//
|
||||
if ((AltRegister & (DRDY | BSY)) == DRDY) {
|
||||
if ((AltRegister & (ATA_STSREG_DRDY | ATA_STSREG_BSY)) == ATA_STSREG_DRDY) {
|
||||
break;
|
||||
}
|
||||
|
||||
if ((AltRegister & (BSY | ERR)) == ERR) {
|
||||
if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
|
||||
|
||||
ErrorRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg1.Error);
|
||||
if ((ErrorRegister & ABRT_ERR) == ABRT_ERR) {
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
}
|
||||
@ -1293,7 +1293,7 @@ DRDYReady2 (
|
||||
name by sending ATA command called ATA Identify Command or ATAPI
|
||||
Identify Command to the specified IDE device. The module name returned
|
||||
is a string of ASCII characters: the first character is bit8--bit15
|
||||
of the first word, the second character is bit0--bit7 of the first word
|
||||
of the first word, the second character is BIT0--bit7 of the first word
|
||||
and so on. Thus the string can not be print directly before it is
|
||||
preprocessed by this func to change the order of characters in
|
||||
each word in the string.
|
||||
@ -1424,7 +1424,7 @@ SetDeviceTransferMode (
|
||||
//
|
||||
Status = AtaNonDataCommandIn (
|
||||
IdeDev,
|
||||
SET_FEATURES_CMD,
|
||||
ATA_CMD_SET_FEATURES,
|
||||
DeviceSelect,
|
||||
0x03,
|
||||
SectorCount,
|
||||
@ -1507,10 +1507,10 @@ AtaNonDataCommandIn (
|
||||
|
||||
//
|
||||
// Wait for command completion
|
||||
// For ATA_SMART_CMD, we may need more timeout to let device
|
||||
// For ATAPI_SMART_CMD, we may need more timeout to let device
|
||||
// adjust internal states.
|
||||
//
|
||||
if (AtaCommand == ATA_SMART_CMD) {
|
||||
if (AtaCommand == ATA_CMD_SMART) {
|
||||
Status = WaitForBSYClear (IdeDev, ATASMARTTIMEOUT);
|
||||
} else {
|
||||
Status = WaitForBSYClear (IdeDev, ATATIMEOUT);
|
||||
@ -1520,7 +1520,7 @@ AtaNonDataCommandIn (
|
||||
}
|
||||
|
||||
StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);
|
||||
if ((StatusRegister & ERR) == ERR) {
|
||||
if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
|
||||
//
|
||||
// Failed to execute command, abort operation
|
||||
//
|
||||
@ -1639,7 +1639,7 @@ AtaNonDataCommandInExt (
|
||||
}
|
||||
|
||||
StatusRegister = IDEReadPortB (IdeDev->PciIo, IdeDev->IoPort->Reg.Status);
|
||||
if ((StatusRegister & ERR) == ERR) {
|
||||
if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
|
||||
//
|
||||
// Failed to execute command, abort operation
|
||||
//
|
||||
@ -1678,7 +1678,7 @@ SetDriveParameters (
|
||||
//
|
||||
Status = AtaNonDataCommandIn (
|
||||
IdeDev,
|
||||
INIT_DRIVE_PARAM_CMD,
|
||||
ATA_CMD_INIT_DRIVE_PARAM,
|
||||
(UINT8) (DeviceSelect + DriveParameters->Heads),
|
||||
0,
|
||||
DriveParameters->Sector,
|
||||
@ -1692,7 +1692,7 @@ SetDriveParameters (
|
||||
//
|
||||
Status = AtaNonDataCommandIn (
|
||||
IdeDev,
|
||||
SET_MULTIPLE_MODE_CMD,
|
||||
ATA_CMD_SET_MULTIPLE_MODE,
|
||||
DeviceSelect,
|
||||
0,
|
||||
DriveParameters->MultipleSector,
|
||||
|
||||
@ -1264,8 +1264,8 @@ IDEDiskInfoInquiry (
|
||||
|
||||
IdeBlkIoDevice = IDE_BLOCK_IO_DEV_FROM_DISK_INFO_THIS (This);
|
||||
|
||||
if (*InquiryDataSize < sizeof (INQUIRY_DATA)) {
|
||||
*InquiryDataSize = sizeof (INQUIRY_DATA);
|
||||
if (*InquiryDataSize < sizeof (ATAPI_INQUIRY_DATA)) {
|
||||
*InquiryDataSize = sizeof (ATAPI_INQUIRY_DATA);
|
||||
return EFI_BUFFER_TOO_SMALL;
|
||||
}
|
||||
|
||||
@ -1273,8 +1273,8 @@ IDEDiskInfoInquiry (
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
gBS->CopyMem (InquiryData, IdeBlkIoDevice->pInquiryData, sizeof (INQUIRY_DATA));
|
||||
*InquiryDataSize = sizeof (INQUIRY_DATA);
|
||||
gBS->CopyMem (InquiryData, IdeBlkIoDevice->pInquiryData, sizeof (ATAPI_INQUIRY_DATA));
|
||||
*InquiryDataSize = sizeof (ATAPI_INQUIRY_DATA);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
@ -89,12 +89,12 @@ typedef struct {
|
||||
IDE_BASE_REGISTERS *IoPort;
|
||||
UINT16 AtapiError;
|
||||
|
||||
INQUIRY_DATA *pInquiryData;
|
||||
ATAPI_INQUIRY_DATA *pInquiryData;
|
||||
EFI_IDENTIFY_DATA *pIdData;
|
||||
ATA_PIO_MODE PioMode;
|
||||
EFI_ATA_MODE UdmaMode;
|
||||
CHAR8 ModelName[41];
|
||||
REQUEST_SENSE_DATA *SenseData;
|
||||
ATAPI_REQUEST_SENSE_DATA *SenseData;
|
||||
UINT8 SenseDataNumber;
|
||||
UINT8 *Cache;
|
||||
|
||||
|
||||
@ -15,41 +15,7 @@
|
||||
#ifndef _IDE_DATA_H
|
||||
#define _IDE_DATA_H
|
||||
|
||||
//
|
||||
// bit definition
|
||||
//
|
||||
#define bit0 (1 << 0)
|
||||
#define bit1 (1 << 1)
|
||||
#define bit2 (1 << 2)
|
||||
#define bit3 (1 << 3)
|
||||
#define bit4 (1 << 4)
|
||||
#define bit5 (1 << 5)
|
||||
#define bit6 (1 << 6)
|
||||
#define bit7 (1 << 7)
|
||||
#define bit8 (1 << 8)
|
||||
#define bit9 (1 << 9)
|
||||
#define bit10 (1 << 10)
|
||||
#define bit11 (1 << 11)
|
||||
#define bit12 (1 << 12)
|
||||
#define bit13 (1 << 13)
|
||||
#define bit14 (1 << 14)
|
||||
#define bit15 (1 << 15)
|
||||
#define bit16 (1 << 16)
|
||||
#define bit17 (1 << 17)
|
||||
#define bit18 (1 << 18)
|
||||
#define bit19 (1 << 19)
|
||||
#define bit20 (1 << 20)
|
||||
#define bit21 (1 << 21)
|
||||
#define bit22 (1 << 22)
|
||||
#define bit23 (1 << 23)
|
||||
#define bit24 (1 << 24)
|
||||
#define bit25 (1 << 25)
|
||||
#define bit26 (1 << 26)
|
||||
#define bit27 (1 << 27)
|
||||
#define bit28 (1 << 28)
|
||||
#define bit29 (1 << 29)
|
||||
#define bit30 (1 << 30)
|
||||
#define bit31 (1 << 31)
|
||||
#include <IndustryStandard/Atapi.h>
|
||||
|
||||
//
|
||||
// common constants
|
||||
@ -144,67 +110,19 @@ typedef struct {
|
||||
// Bit definitions in Programming Interface byte of the Class Code field
|
||||
// in PCI IDE controller's Configuration Space
|
||||
//
|
||||
#define IDE_PRIMARY_OPERATING_MODE bit0
|
||||
#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1
|
||||
#define IDE_SECONDARY_OPERATING_MODE bit2
|
||||
#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3
|
||||
#define IDE_PRIMARY_OPERATING_MODE BIT0
|
||||
#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
|
||||
#define IDE_SECONDARY_OPERATING_MODE BIT2
|
||||
#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
|
||||
|
||||
//
|
||||
// IDE registers bit definitions
|
||||
//
|
||||
|
||||
//
|
||||
// Err Reg
|
||||
//
|
||||
#define BBK_ERR bit7 /* Bad block detected */
|
||||
#define UNC_ERR bit6 /* Uncorrectable Data */
|
||||
#define MC_ERR bit5 /* Media Change */
|
||||
#define IDNF_ERR bit4 /* ID Not Found */
|
||||
#define MCR_ERR bit3 /* Media Change Requested */
|
||||
#define ABRT_ERR bit2 /* Aborted Command */
|
||||
#define TK0NF_ERR bit1 /* Track 0 Not Found */
|
||||
#define AMNF_ERR bit0 /* Address Mark Not Found */
|
||||
|
||||
//
|
||||
// Device/Head Reg
|
||||
//
|
||||
#define LBA_MODE bit6
|
||||
#define DEV bit4
|
||||
#define HS3 bit3
|
||||
#define HS2 bit2
|
||||
#define HS1 bit1
|
||||
#define HS0 bit0
|
||||
#define CHS_MODE (0)
|
||||
#define DRV0 (0)
|
||||
#define DRV1 (1)
|
||||
#define MST_DRV DRV0
|
||||
#define SLV_DRV DRV1
|
||||
|
||||
//
|
||||
// Status Reg
|
||||
//
|
||||
#define BSY bit7 /* Controller Busy */
|
||||
#define DRDY bit6 /* Drive Ready */
|
||||
#define DWF bit5 /* Drive Write Fault */
|
||||
#define DSC bit4 /* Disk Seek Complete */
|
||||
#define DRQ bit3 /* Data Request */
|
||||
#define CORR bit2 /* Corrected Data */
|
||||
#define IDX bit1 /* Index */
|
||||
#define ERR bit0 /* Error */
|
||||
|
||||
//
|
||||
// Device Control Reg
|
||||
//
|
||||
#define SRST bit2 /* Software Reset */
|
||||
#define IEN_L bit1 /* Interrupt Enable #*/
|
||||
|
||||
//
|
||||
// Bus Master Reg
|
||||
//
|
||||
#define BMIC_nREAD bit3
|
||||
#define BMIC_START bit0
|
||||
#define BMIS_INTERRUPT bit2
|
||||
#define BMIS_ERROR bit1
|
||||
#define BMIC_nREAD BIT3
|
||||
#define BMIC_START BIT0
|
||||
#define BMIS_INTERRUPT BIT2
|
||||
#define BMIS_ERROR BIT1
|
||||
|
||||
#define BMICP_OFFSET 0x00
|
||||
#define BMISP_OFFSET 0x02
|
||||
@ -256,205 +174,6 @@ typedef struct {
|
||||
//
|
||||
#define ATASMARTTIMEOUT 10000
|
||||
|
||||
//
|
||||
// ATA Commands Code
|
||||
//
|
||||
#define ATA_INITIALIZE_DEVICE 0x91
|
||||
|
||||
//
|
||||
// Class 1
|
||||
//
|
||||
#define IDENTIFY_DRIVE_CMD 0xec
|
||||
#define READ_BUFFER_CMD 0xe4
|
||||
#define READ_SECTORS_CMD 0x20
|
||||
#define READ_SECTORS_WITH_RETRY_CMD 0x21
|
||||
#define READ_LONG_CMD 0x22
|
||||
#define READ_LONG_WITH_RETRY_CMD 0x23
|
||||
//
|
||||
// Class 1 - Atapi6 enhanced commands
|
||||
//
|
||||
#define READ_SECTORS_EXT_CMD 0x24
|
||||
|
||||
//
|
||||
// Class 2
|
||||
//
|
||||
#define FORMAT_TRACK_CMD 0x50
|
||||
#define WRITE_BUFFER_CMD 0xe8
|
||||
#define WRITE_SECTORS_CMD 0x30
|
||||
#define WRITE_SECTORS_WITH_RETRY_CMD 0x31
|
||||
#define WRITE_LONG_CMD 0x32
|
||||
#define WRITE_LONG_WITH_RETRY_CMD 0x33
|
||||
#define WRITE_VERIFY_CMD 0x3c
|
||||
//
|
||||
// Class 2 - Atapi6 enhanced commands
|
||||
//
|
||||
#define WRITE_SECTORS_EXT_CMD 0x34
|
||||
|
||||
//
|
||||
// Class 3
|
||||
//
|
||||
#define ACK_MEDIA_CHANGE_CMD 0xdb
|
||||
#define BOOT_POST_BOOT_CMD 0xdc
|
||||
#define BOOT_PRE_BOOT_CMD 0xdd
|
||||
#define CHECK_POWER_MODE_CMD 0x98
|
||||
#define CHECK_POWER_MODE_CMD_ALIAS 0xe5
|
||||
#define DOOR_LOCK_CMD 0xde
|
||||
#define DOOR_UNLOCK_CMD 0xdf
|
||||
#define EXEC_DRIVE_DIAG_CMD 0x90
|
||||
#define IDLE_CMD_ALIAS 0x97
|
||||
#define IDLE_CMD 0xe3
|
||||
#define IDLE_IMMEDIATE_CMD 0x95
|
||||
#define IDLE_IMMEDIATE_CMD_ALIAS 0xe1
|
||||
#define INIT_DRIVE_PARAM_CMD 0x91
|
||||
#define RECALIBRATE_CMD 0x10 /* aliased to 1x */
|
||||
#define READ_DRIVE_STATE_CMD 0xe9
|
||||
#define SET_MULTIPLE_MODE_CMD 0xC6
|
||||
#define READ_DRIVE_STATE_CMD 0xe9
|
||||
#define READ_VERIFY_CMD 0x40
|
||||
#define READ_VERIFY_WITH_RETRY_CMD 0x41
|
||||
#define SEEK_CMD 0x70 /* aliased to 7x */
|
||||
#define SET_FEATURES_CMD 0xef
|
||||
#define STANDBY_CMD 0x96
|
||||
#define STANDBY_CMD_ALIAS 0xe2
|
||||
#define STANDBY_IMMEDIATE_CMD 0x94
|
||||
#define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0
|
||||
|
||||
//
|
||||
// Class 4
|
||||
//
|
||||
#define READ_DMA_CMD 0xc8
|
||||
#define READ_DMA_WITH_RETRY_CMD 0xc9
|
||||
#define READ_DMA_EXT_CMD 0x25
|
||||
#define WRITE_DMA_CMD 0xca
|
||||
#define WRITE_DMA_WITH_RETRY_CMD 0xcb
|
||||
#define WRITE_DMA_EXT_CMD 0x35
|
||||
|
||||
//
|
||||
// Class 5
|
||||
//
|
||||
#define READ_MULTIPLE_CMD 0xc4
|
||||
#define REST_CMD 0xe7
|
||||
#define RESTORE_DRIVE_STATE_CMD 0xea
|
||||
#define SET_SLEEP_MODE_CMD 0x99
|
||||
#define SET_SLEEP_MODE_CMD_ALIAS 0xe6
|
||||
#define WRITE_MULTIPLE_CMD 0xc5
|
||||
#define WRITE_SAME_CMD 0xe9
|
||||
|
||||
//
|
||||
// Class 6 - Host protected area access feature set
|
||||
//
|
||||
#define READ_NATIVE_MAX_ADDRESS_CMD 0xf8
|
||||
#define SET_MAX_ADDRESS_CMD 0xf9
|
||||
|
||||
//
|
||||
// Class 6 - ATA/ATAPI-6 enhanced commands
|
||||
//
|
||||
#define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27
|
||||
#define SET_MAX_ADDRESS_CMD_EXT 0x37
|
||||
|
||||
//
|
||||
// Class 6 - SET_MAX related sub command (in feature register)
|
||||
//
|
||||
#define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00
|
||||
#define PARTIES_SET_PASSWORD_SUB_CMD 0x01
|
||||
#define PARTIES_LOCK_SUB_CMD 0x02
|
||||
#define PARTIES_UNLOCK_SUB_CMD 0x03
|
||||
#define PARTIES_FREEZE_SUB_CMD 0x04
|
||||
|
||||
//
|
||||
// S.M.A.R.T
|
||||
//
|
||||
#define ATA_SMART_CMD 0xb0
|
||||
#define ATA_CONSTANT_C2 0xc2
|
||||
#define ATA_CONSTANT_4F 0x4f
|
||||
#define ATA_SMART_ENABLE_OPERATION 0xd8
|
||||
#define ATA_SMART_RETURN_STATUS 0xda
|
||||
|
||||
//
|
||||
// Error codes for Exec Drive Diag
|
||||
//
|
||||
#define DRIV_DIAG_NO_ERROR (0x01)
|
||||
#define DRIV_DIAG_FORMATTER_ERROR (0x02)
|
||||
#define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)
|
||||
#define DRIV_DIAG_ECC_CKT_ERRROR (0x04)
|
||||
#define DRIV_DIAG_UP_ERROR (0x05)
|
||||
#define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */
|
||||
|
||||
//
|
||||
// Codes for Format Track
|
||||
//
|
||||
#define FORMAT_GOOD_SECTOR (0x00)
|
||||
#define FORMAT_SUSPEND_ALLOC (0x01)
|
||||
#define FORMAT_REALLOC_SECTOR (0x02)
|
||||
#define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)
|
||||
|
||||
//
|
||||
// IDE_IDENTIFY bits
|
||||
// config bits :
|
||||
//
|
||||
#define ID_CONFIG_RESERVED0 bit0
|
||||
#define ID_CONFIG_HARD_SECTORED_DRIVE bit1
|
||||
#define ID_CONFIG_SOFT_SECTORED_DRIVE bit2
|
||||
#define ID_CONFIG_NON_MFM bit3
|
||||
#define ID_CONFIG_15uS_HEAD_SWITCHING bit4
|
||||
#define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5
|
||||
#define ID_CONFIG_HARD_DRIVE bit6
|
||||
#define ID_CONFIG_CHANGEABLE_MEDIUM bit7
|
||||
#define ID_CONFIG_DATA_RATE_TO_5MHZ bit8
|
||||
#define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9
|
||||
#define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10
|
||||
#define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11
|
||||
#define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12
|
||||
#define ID_CONFIG_TRACK_OFFSET_AVAIL bit13
|
||||
#define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14
|
||||
#define ID_CONFIG_RESERVED1 bit15
|
||||
|
||||
#define ID_DOUBLE_WORD_IO_POSSIBLE bit01
|
||||
#define ID_LBA_SUPPORTED bit9
|
||||
#define ID_DMA_SUPPORTED bit8
|
||||
|
||||
#define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)
|
||||
#define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)
|
||||
#define SET_FEATURE_TRANSFER_MODE (0x03)
|
||||
#define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)
|
||||
#define SET_FEATURE_DISABLE_RETRIES (0x33)
|
||||
//
|
||||
// for Read & Write Longs
|
||||
//
|
||||
#define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)
|
||||
#define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)
|
||||
#define SET_FEATURE_DISABLE_READ_AHEAD (0x55)
|
||||
#define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)
|
||||
#define SET_FEATURE_DISABLE_ECC (0x77)
|
||||
#define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)
|
||||
#define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)
|
||||
#define SET_FEATURE_ENABLE_ECC (0x88)
|
||||
#define SET_FEATURE_ENABLE_RETRIES (0x99)
|
||||
#define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)
|
||||
#define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)
|
||||
#define SET_FEATURE_ALLOW_REST_MODE (0xac)
|
||||
//
|
||||
// for Read & Write Longs
|
||||
//
|
||||
#define SET_FEATURE_4BYTE_ECC (0xbb)
|
||||
#define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)
|
||||
#define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)
|
||||
|
||||
#define BLOCK_TRANSFER_MODE (0x00)
|
||||
#define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)
|
||||
#define MULTI_WORD_DMA_TRANSFER_MODE (0x20)
|
||||
#define TRANSFER_MODE_MASK (0x07) // 3 LSBs
|
||||
|
||||
//
|
||||
// Drive 0 - Head 0
|
||||
//
|
||||
#define DEFAULT_DRIVE (0x00)
|
||||
#define DEFAULT_CMD (0xa0)
|
||||
//
|
||||
// default content of device control register, disable INT
|
||||
//
|
||||
#define DEFAULT_CTL (0x0a)
|
||||
#define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)
|
||||
|
||||
//
|
||||
// ATAPI6 related data structure definition
|
||||
@ -465,320 +184,19 @@ typedef struct {
|
||||
//
|
||||
#define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
|
||||
|
||||
//
|
||||
// Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
|
||||
//
|
||||
|
||||
//
|
||||
// ATAPI Command
|
||||
//
|
||||
#define ATAPI_SOFT_RESET_CMD 0x08
|
||||
#define ATAPI_PACKET_CMD 0xA0
|
||||
#define PACKET_CMD 0xA0
|
||||
#define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
|
||||
#define ATAPI_SERVICE_CMD 0xA2
|
||||
|
||||
//
|
||||
// ATAPI Packet Command
|
||||
//
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1;
|
||||
UINT8 reserved_2;
|
||||
UINT8 reserved_3;
|
||||
UINT8 reserved_4;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 reserved_8;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} TEST_UNIT_READY_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 4;
|
||||
UINT8 lun : 4;
|
||||
UINT8 page_code;
|
||||
UINT8 reserved_3;
|
||||
UINT8 allocation_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 reserved_8;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} INQUIRY_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 4;
|
||||
UINT8 lun : 4;
|
||||
UINT8 reserved_2;
|
||||
UINT8 reserved_3;
|
||||
UINT8 allocation_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 reserved_8;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} REQUEST_SENSE_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 4;
|
||||
UINT8 lun : 4;
|
||||
UINT8 page_code : 4;
|
||||
UINT8 page_control : 4;
|
||||
UINT8 reserved_3;
|
||||
UINT8 reserved_4;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 parameter_list_length_hi;
|
||||
UINT8 parameter_list_length_lo;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} MODE_SENSE_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1 : 5;
|
||||
UINT8 lun : 3;
|
||||
UINT8 Lba0;
|
||||
UINT8 Lba1;
|
||||
UINT8 Lba2;
|
||||
UINT8 Lba3;
|
||||
UINT8 reserved_6;
|
||||
UINT8 TranLen0;
|
||||
UINT8 TranLen1;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} READ10_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 opcode;
|
||||
UINT8 reserved_1;
|
||||
UINT8 reserved_2;
|
||||
UINT8 reserved_3;
|
||||
UINT8 reserved_4;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 allocation_length_hi;
|
||||
UINT8 allocation_length_lo;
|
||||
UINT8 reserved_9;
|
||||
UINT8 reserved_10;
|
||||
UINT8 reserved_11;
|
||||
} READ_FORMAT_CAP_CMD;
|
||||
|
||||
typedef union {
|
||||
UINT16 Data16[6];
|
||||
TEST_UNIT_READY_CMD TestUnitReady;
|
||||
READ10_CMD Read10;
|
||||
REQUEST_SENSE_CMD RequestSence;
|
||||
INQUIRY_CMD Inquiry;
|
||||
MODE_SENSE_CMD ModeSense;
|
||||
READ_FORMAT_CAP_CMD ReadFormatCapacity;
|
||||
} ATAPI_PACKET_COMMAND;
|
||||
|
||||
typedef struct {
|
||||
UINT32 RegionBaseAddr;
|
||||
UINT16 ByteCount;
|
||||
UINT16 EndOfTable;
|
||||
} IDE_DMA_PRD;
|
||||
|
||||
#define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
|
||||
#define MAX_DMA_COMMAND_SECTORS 0x100
|
||||
|
||||
#pragma pack()
|
||||
|
||||
//
|
||||
// Packet Command Code
|
||||
//
|
||||
#define TEST_UNIT_READY 0x00
|
||||
#define REZERO 0x01
|
||||
#define REQUEST_SENSE 0x03
|
||||
#define FORMAT_UNIT 0x04
|
||||
#define REASSIGN_BLOCKS 0x07
|
||||
#define INQUIRY 0x12
|
||||
#define START_STOP_UNIT 0x1B
|
||||
#define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
|
||||
#define READ_FORMAT_CAPACITY 0x23
|
||||
#define OLD_FORMAT_UNIT 0x24
|
||||
#define READ_CAPACITY 0x25
|
||||
#define READ_10 0x28
|
||||
#define WRITE_10 0x2A
|
||||
#define SEEK 0x2B
|
||||
#define SEND_DIAGNOSTICS 0x3D
|
||||
#define WRITE_VERIFY 0x2E
|
||||
#define VERIFY 0x2F
|
||||
#define READ_DEFECT_DATA 0x37
|
||||
#define WRITE_BUFFER 0x38
|
||||
#define READ_BUFFER 0x3C
|
||||
#define READ_LONG 0x3E
|
||||
#define WRITE_LONG 0x3F
|
||||
#define MODE_SELECT 0x55
|
||||
#define MODE_SENSE 0x5A
|
||||
#define READ_12 0xA8
|
||||
#define WRITE_12 0xAA
|
||||
#define MAX_ATAPI_BYTE_COUNT (0xfffe)
|
||||
|
||||
//
|
||||
// Sense Key
|
||||
//
|
||||
#define REQUEST_SENSE_ERROR (0x70)
|
||||
#define SK_NO_SENSE (0x0)
|
||||
#define SK_RECOVERY_ERROR (0x1)
|
||||
#define SK_NOT_READY (0x2)
|
||||
#define SK_MEDIUM_ERROR (0x3)
|
||||
#define SK_HARDWARE_ERROR (0x4)
|
||||
#define SK_ILLEGAL_REQUEST (0x5)
|
||||
#define SK_UNIT_ATTENTION (0x6)
|
||||
#define SK_DATA_PROTECT (0x7)
|
||||
#define SK_BLANK_CHECK (0x8)
|
||||
#define SK_VENDOR_SPECIFIC (0x9)
|
||||
#define SK_RESERVED_A (0xA)
|
||||
#define SK_ABORT (0xB)
|
||||
#define SK_RESERVED_C (0xC)
|
||||
#define SK_OVERFLOW (0xD)
|
||||
#define SK_MISCOMPARE (0xE)
|
||||
#define SK_RESERVED_F (0xF)
|
||||
|
||||
//
|
||||
// Additional Sense Codes
|
||||
//
|
||||
#define ASC_NOT_READY (0x04)
|
||||
#define ASC_MEDIA_ERR1 (0x10)
|
||||
#define ASC_MEDIA_ERR2 (0x11)
|
||||
#define ASC_MEDIA_ERR3 (0x14)
|
||||
#define ASC_MEDIA_ERR4 (0x30)
|
||||
#define ASC_MEDIA_UPSIDE_DOWN (0x06)
|
||||
#define ASC_INVALID_CMD (0x20)
|
||||
#define ASC_LBA_OUT_OF_RANGE (0x21)
|
||||
#define ASC_INVALID_FIELD (0x24)
|
||||
#define ASC_WRITE_PROTECTED (0x27)
|
||||
#define ASC_MEDIA_CHANGE (0x28)
|
||||
#define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
|
||||
#define ASC_ILLEGAL_FIELD (0x26)
|
||||
#define ASC_NO_MEDIA (0x3A)
|
||||
#define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
|
||||
|
||||
//
|
||||
// Additional Sense Code Qualifier
|
||||
//
|
||||
#define ASCQ_IN_PROGRESS (0x01)
|
||||
|
||||
#define SETFEATURE TRUE
|
||||
#define CLEARFEATURE FALSE
|
||||
|
||||
//
|
||||
// ATAPI Data structure
|
||||
//
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT8 peripheral_type;
|
||||
UINT8 RMB;
|
||||
UINT8 version;
|
||||
UINT8 response_data_format;
|
||||
UINT8 addnl_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 vendor_info[8];
|
||||
UINT8 product_id[12];
|
||||
UINT8 eeprom_product_code[4];
|
||||
UINT8 firmware_rev_level[4];
|
||||
UINT8 firmware_sub_rev_level[1];
|
||||
UINT8 reserved_37;
|
||||
UINT8 reserved_38;
|
||||
UINT8 reserved_39;
|
||||
UINT8 max_capacity_hi;
|
||||
UINT8 max_capacity_mid;
|
||||
UINT8 max_capacity_lo;
|
||||
UINT8 reserved_43_95[95 - 43 + 1];
|
||||
} INQUIRY_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 peripheral_type;
|
||||
UINT8 RMB;
|
||||
UINT8 version;
|
||||
UINT8 response_data_format;
|
||||
UINT8 addnl_length;
|
||||
UINT8 reserved_5;
|
||||
UINT8 reserved_6;
|
||||
UINT8 reserved_7;
|
||||
UINT8 vendor_info[8];
|
||||
UINT8 product_id[16];
|
||||
UINT8 product_revision_level[4];
|
||||
UINT8 vendor_specific[20];
|
||||
UINT8 reserved_56_95[40];
|
||||
} CDROM_INQUIRY_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 error_code : 7;
|
||||
UINT8 valid : 1;
|
||||
UINT8 reserved_1;
|
||||
UINT8 sense_key : 4;
|
||||
UINT8 reserved_21 : 1;
|
||||
UINT8 ILI : 1;
|
||||
UINT8 reserved_22 : 2;
|
||||
UINT8 vendor_specific_3;
|
||||
UINT8 vendor_specific_4;
|
||||
UINT8 vendor_specific_5;
|
||||
UINT8 vendor_specific_6;
|
||||
UINT8 addnl_sense_length; // n - 7
|
||||
UINT8 vendor_specific_8;
|
||||
UINT8 vendor_specific_9;
|
||||
UINT8 vendor_specific_10;
|
||||
UINT8 vendor_specific_11;
|
||||
UINT8 addnl_sense_code; // mandatory
|
||||
UINT8 addnl_sense_code_qualifier; // mandatory
|
||||
UINT8 field_replaceable_unit_code; // optional
|
||||
UINT8 reserved_15;
|
||||
UINT8 reserved_16;
|
||||
UINT8 reserved_17;
|
||||
//
|
||||
// Followed by additional sense bytes : FIXME
|
||||
//
|
||||
} REQUEST_SENSE_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 LastLba3;
|
||||
UINT8 LastLba2;
|
||||
UINT8 LastLba1;
|
||||
UINT8 LastLba0;
|
||||
UINT8 BlockSize3;
|
||||
UINT8 BlockSize2;
|
||||
UINT8 BlockSize1;
|
||||
UINT8 BlockSize0;
|
||||
} READ_CAPACITY_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT8 reserved_0;
|
||||
UINT8 reserved_1;
|
||||
UINT8 reserved_2;
|
||||
UINT8 Capacity_Length;
|
||||
UINT8 LastLba3;
|
||||
UINT8 LastLba2;
|
||||
UINT8 LastLba1;
|
||||
UINT8 LastLba0;
|
||||
UINT8 DesCode : 2;
|
||||
UINT8 reserved_9 : 6;
|
||||
UINT8 BlockSize2;
|
||||
UINT8 BlockSize1;
|
||||
UINT8 BlockSize0;
|
||||
} READ_FORMAT_CAPACITY_DATA;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
//
|
||||
// PIO mode definition
|
||||
//
|
||||
@ -848,46 +266,46 @@ typedef struct {
|
||||
//
|
||||
// Slave IDE Timing Register Enable
|
||||
//
|
||||
#define SITRE bit14
|
||||
#define SITRE BIT14
|
||||
|
||||
//
|
||||
// DMA Timing Enable Only Select 1
|
||||
//
|
||||
#define DTE1 bit7
|
||||
#define DTE1 BIT7
|
||||
|
||||
//
|
||||
// Pre-fetch and Posting Enable Select 1
|
||||
//
|
||||
#define PPE1 bit6
|
||||
#define PPE1 BIT6
|
||||
|
||||
//
|
||||
// IORDY Sample Point Enable Select 1
|
||||
//
|
||||
#define IE1 bit5
|
||||
#define IE1 BIT5
|
||||
|
||||
//
|
||||
// Fast Timing Bank Drive Select 1
|
||||
//
|
||||
#define TIME1 bit4
|
||||
#define TIME1 BIT4
|
||||
|
||||
//
|
||||
// DMA Timing Enable Only Select 0
|
||||
//
|
||||
#define DTE0 bit3
|
||||
#define DTE0 BIT3
|
||||
|
||||
//
|
||||
// Pre-fetch and Posting Enable Select 0
|
||||
//
|
||||
#define PPE0 bit2
|
||||
#define PPE0 BIT2
|
||||
|
||||
//
|
||||
// IOREY Sample Point Enable Select 0
|
||||
//
|
||||
#define IE0 bit1
|
||||
#define IE0 BIT1
|
||||
|
||||
//
|
||||
// Fast Timing Bank Drive Select 0
|
||||
//
|
||||
#define TIME0 bit0
|
||||
#define TIME0 BIT0
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user