mirror of https://github.com/acidanthera/audk.git
OvmfPkg/IntelTdx: Add Sec to bring up both Legacy and Tdx guest
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 OvmfPkg/IntelTdx/Sec is a simplied version of OvmfPkg/Sec. There are below differences between these 2 Sec - IntelTdx/Sec only supports Legacy guest and Tdx guest in X64. - IntelTdx/Sec calls PeilessStartup () to jump from SEC to DXE directly. - IntelTdx/Sec uses MemoryAllocationLib / HobLib / PrePiLib in EmbeddedPkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
This commit is contained in:
Min Xu
mergify[bot]
parent
4fe2678411
commit
1f29de4d20
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/** @file
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Main SEC phase code. Transitions to PEI.
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Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
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Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/PeimEntryPoint.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiCpuLib.h>
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#include <Library/DebugAgentLib.h>
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#include <Library/IoLib.h>
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#include <Library/PeCoffLib.h>
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#include <Library/PeCoffGetEntryPointLib.h>
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#include <Library/LocalApicLib.h>
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#include <Library/CpuExceptionHandlerLib.h>
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#include <IndustryStandard/Tdx.h>
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#include <Library/PlatformInitLib.h>
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#include <Library/PeilessStartupLib.h>
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#define SEC_IDT_ENTRY_COUNT 34
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typedef struct _SEC_IDT_TABLE {
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EFI_PEI_SERVICES *PeiService;
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IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT];
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} SEC_IDT_TABLE;
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//
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// Template of an IDT entry pointing to 10:FFFFFFE4h.
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//
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IA32_IDT_GATE_DESCRIPTOR mIdtEntryTemplate = {
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{ // Bits
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0xffe4, // OffsetLow
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0x10, // Selector
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0x0, // Reserved_0
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IA32_IDT_GATE_TYPE_INTERRUPT_32, // GateType
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0xffff // OffsetHigh
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}
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};
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VOID
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EFIAPI
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SecCoreStartupWithStack (
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IN EFI_FIRMWARE_VOLUME_HEADER *BootFv,
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IN VOID *TopOfCurrentStack
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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SEC_IDT_TABLE IdtTableInStack;
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IA32_DESCRIPTOR IdtDescriptor;
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UINT32 Index;
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volatile UINT8 *Table;
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if (TdIsEnabled ()) {
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//
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// For Td guests, the memory map info is in TdHobLib. It should be processed
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// first so that the memory is accepted. Otherwise access to the unaccepted
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// memory will trigger tripple fault.
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//
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if (ProcessTdxHobList () != EFI_SUCCESS) {
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CpuDeadLoop ();
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}
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}
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//
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// To ensure SMM can't be compromised on S3 resume, we must force re-init of
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// the BaseExtractGuidedSectionLib. Since this is before library contructors
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// are called, we must use a loop rather than SetMem.
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//
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Table = (UINT8 *)(UINTN)FixedPcdGet64 (PcdGuidedExtractHandlerTableAddress);
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for (Index = 0;
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Index < FixedPcdGet32 (PcdGuidedExtractHandlerTableSize);
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++Index)
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{
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Table[Index] = 0;
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}
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//
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// Initialize IDT - Since this is before library constructors are called,
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// we use a loop rather than CopyMem.
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//
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IdtTableInStack.PeiService = NULL;
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for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {
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//
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// Declare the local variables that actually move the data elements as
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// volatile to prevent the optimizer from replacing this function with
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// the intrinsic memcpy()
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//
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CONST UINT8 *Src;
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volatile UINT8 *Dst;
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UINTN Byte;
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Src = (CONST UINT8 *)&mIdtEntryTemplate;
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Dst = (volatile UINT8 *)&IdtTableInStack.IdtTable[Index];
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for (Byte = 0; Byte < sizeof (mIdtEntryTemplate); Byte++) {
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Dst[Byte] = Src[Byte];
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}
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}
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IdtDescriptor.Base = (UINTN)&IdtTableInStack.IdtTable;
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IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
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ProcessLibraryConstructorList (NULL, NULL);
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//
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// Load the IDTR.
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//
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AsmWriteIdtr (&IdtDescriptor);
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if (TdIsEnabled ()) {
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//
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// InitializeCpuExceptionHandlers () should be called in Td guests so that
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// #VE exceptions can be handled correctly.
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//
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InitializeCpuExceptionHandlers (NULL);
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}
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DEBUG ((
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DEBUG_INFO,
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"SecCoreStartupWithStack(0x%x, 0x%x)\n",
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(UINT32)(UINTN)BootFv,
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(UINT32)(UINTN)TopOfCurrentStack
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));
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//
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// Initialize floating point operating environment
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// to be compliant with UEFI spec.
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//
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InitializeFloatingPointUnits ();
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//
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// ASSERT that the Page Tables were set by the reset vector code to
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// the address we expect.
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//
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ASSERT (AsmReadCr3 () == (UINTN)PcdGet32 (PcdOvmfSecPageTablesBase));
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//
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// |-------------| <-- TopOfCurrentStack
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// | Stack | 32k
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// |-------------|
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// | Heap | 32k
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// |-------------| <-- SecCoreData.TemporaryRamBase
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//
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ASSERT (
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(UINTN)(PcdGet32 (PcdOvmfSecPeiTempRamBase) +
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PcdGet32 (PcdOvmfSecPeiTempRamSize)) ==
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(UINTN)TopOfCurrentStack
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);
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//
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// Initialize SEC hand-off state
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//
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SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
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SecCoreData.TemporaryRamSize = (UINTN)PcdGet32 (PcdOvmfSecPeiTempRamSize);
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SecCoreData.TemporaryRamBase = (VOID *)((UINT8 *)TopOfCurrentStack - SecCoreData.TemporaryRamSize);
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SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;
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SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;
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SecCoreData.BootFirmwareVolumeBase = BootFv;
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SecCoreData.BootFirmwareVolumeSize = (UINTN)BootFv->FvLength;
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//
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// Make sure the 8259 is masked before initializing the Debug Agent and the debug timer is enabled
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//
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IoWrite8 (0x21, 0xff);
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IoWrite8 (0xA1, 0xff);
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//
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// Initialize Local APIC Timer hardware and disable Local APIC Timer
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// interrupts before initializing the Debug Agent and the debug timer is
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// enabled.
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//
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InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
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DisableApicTimerInterrupt ();
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PeilessStartup (&SecCoreData);
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ASSERT (FALSE);
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CpuDeadLoop ();
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}
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@ -0,0 +1,61 @@
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## @file
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# SEC Driver
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#
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# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = SecMain
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FILE_GUID = 69d96630-eb64-4b33-8491-13a5cf023dcf
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MODULE_TYPE = SEC
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VERSION_STRING = 1.0
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ENTRY_POINT = SecMain
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = X64
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#
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[Sources]
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SecMain.c
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X64/SecEntry.nasm
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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OvmfPkg/OvmfPkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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[LibraryClasses]
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BaseLib
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DebugLib
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BaseMemoryLib
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PcdLib
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UefiCpuLib
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DebugAgentLib
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IoLib
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PeCoffLib
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PeCoffGetEntryPointLib
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PeCoffExtraActionLib
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ExtractGuidedSectionLib
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LocalApicLib
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MemEncryptSevLib
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CpuExceptionHandlerLib
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PeilessStartupLib
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PlatformInitLib
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[Pcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
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gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
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gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
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gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase
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@ -0,0 +1,151 @@
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;------------------------------------------------------------------------------
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;*
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;* Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
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;* SPDX-License-Identifier: BSD-2-Clause-Patent
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;*
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;* CpuAsm.asm
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;*
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;* Abstract:
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;*
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;------------------------------------------------------------------------------
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#include <Base.h>
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%include "TdxCommondefs.inc"
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DEFAULT REL
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SECTION .text
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extern ASM_PFX(SecCoreStartupWithStack)
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%macro tdcall 0
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db 0x66, 0x0f, 0x01, 0xcc
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%endmacro
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;
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; SecCore Entry Point
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;
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; Processor is in flat protected mode
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;
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; @param[in] RAX Initial value of the EAX register (BIST: Built-in Self Test)
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; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor
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; @param[in] RBP Pointer to the start of the Boot Firmware Volume
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; @param[in] DS Selector allowing flat access to all addresses
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; @param[in] ES Selector allowing flat access to all addresses
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; @param[in] FS Selector allowing flat access to all addresses
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; @param[in] GS Selector allowing flat access to all addresses
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; @param[in] SS Selector allowing flat access to all addresses
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;
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; @return None This routine does not return
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;
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global ASM_PFX(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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;
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; Guest type is stored in OVMF_WORK_AREA
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;
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%define OVMF_WORK_AREA FixedPcdGet32 (PcdOvmfWorkAreaBase)
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%define VM_GUEST_TYPE_TDX 2
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mov eax, OVMF_WORK_AREA
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cmp byte[eax], VM_GUEST_TYPE_TDX
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jne InitStack
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mov rax, TDCALL_TDINFO
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tdcall
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;
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; R8 [31:0] NUM_VCPUS
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; [63:32] MAX_VCPUS
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; R9 [31:0] VCPU_INDEX
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; Td Guest set the VCPU0 as the BSP, others are the APs
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; APs jump to spinloop and get released by DXE's MpInitLib
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;
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mov rax, r9
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and rax, 0xffff
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test rax, rax
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jne ParkAp
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InitStack:
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;
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; Fill the temporary RAM with the initial stack value.
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; The loop below will seed the heap as well, but that's harmless.
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;
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mov rax, (FixedPcdGet32 (PcdInitValueInTempStack) << 32) | FixedPcdGet32 (PcdInitValueInTempStack)
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; qword to store
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mov rdi, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) ; base address,
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; relative to
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; ES
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mov rcx, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) / 8 ; qword count
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cld ; store from base
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; up
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rep stosq
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;
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; Load temporary RAM stack based on PCDs
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;
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%define SEC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + \
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FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
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mov rsp, SEC_TOP_OF_STACK
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nop
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;
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; Setup parameters and call SecCoreStartupWithStack
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; rcx: BootFirmwareVolumePtr
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; rdx: TopOfCurrentStack
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;
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mov rcx, rbp
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mov rdx, rsp
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sub rsp, 0x20
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call ASM_PFX(SecCoreStartupWithStack)
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;
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; Note: BSP never gets here. APs will be unblocked by DXE
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;
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; R8 [31:0] NUM_VCPUS
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; [63:32] MAX_VCPUS
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; R9 [31:0] VCPU_INDEX
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;
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ParkAp:
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mov rbp, r9
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.do_wait_loop:
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mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase)
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;
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; register itself in [rsp + CpuArrivalOffset]
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;
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mov rax, 1
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lock xadd dword [rsp + CpuArrivalOffset], eax
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inc eax
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.check_arrival_cnt:
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cmp eax, r8d
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je .check_command
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mov eax, dword[rsp + CpuArrivalOffset]
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jmp .check_arrival_cnt
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.check_command:
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mov eax, dword[rsp + CommandOffset]
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cmp eax, MpProtectedModeWakeupCommandNoop
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je .check_command
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cmp eax, MpProtectedModeWakeupCommandWakeup
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je .do_wakeup
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; Don't support this command, so ignore
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jmp .check_command
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.do_wakeup:
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;
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; BSP sets these variables before unblocking APs
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; RAX: WakeupVectorOffset
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; RBX: Relocated mailbox address
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; RBP: vCpuId
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;
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mov rax, 0
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mov eax, dword[rsp + WakeupVectorOffset]
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mov rbx, [rsp + WakeupArgsRelocatedMailBox]
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nop
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jmp rax
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jmp $
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