mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmMmuLib ARM: drop memory type check for page tables
We already expect normal memory to be mapped writeback cacheable if EDK2 itself is to make use of it, so doing an early sanity check on the memory type of the allocation that the page tables happened to land in isn't very useful. So let's drop it. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
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@ -328,7 +328,6 @@ ArmConfigureMmu (
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)
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{
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VOID *TranslationTable;
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ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;
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UINT32 TTBRAttributes;
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TranslationTable = AllocateAlignedPages (
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@ -353,28 +352,13 @@ ArmConfigureMmu (
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InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
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ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
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// By default, mark the translation table as belonging to a uncached region
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TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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while (MemoryTable->Length != 0) {
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// Find the memory attribute for the Translation Table
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if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
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TranslationTableAttribute = MemoryTable->Attributes;
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}
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FillTranslationTable (TranslationTable, MemoryTable);
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MemoryTable++;
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}
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// Translate the Memory Attributes into Translation Table Register Attributes
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if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
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(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
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TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;
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} else {
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// Page tables must reside in memory mapped as write-back cacheable
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ASSERT (0);
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return RETURN_UNSUPPORTED;
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}
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TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC
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: TTBR_WRITE_BACK_ALLOC;
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if (TTBRAttributes & TTBR_SHAREABLE) {
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if (PreferNonshareableMemory ()) {
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TTBRAttributes ^= TTBR_SHAREABLE;
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