mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/AtaAtapiPassThru: don't write read-only AHCI MMIO register
Per AHCI 1.1 spec, AE bit of GHC register is read-only if CAP.SAM is 1 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16321 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1440,8 +1440,19 @@ AhciReset (
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{
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UINT64 Delay;
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UINT32 Value;
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UINT32 Capability;
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AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
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//
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// Collect AHCI controller information
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//
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Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
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//
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// Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set
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//
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if ((Capability & EFI_AHCI_CAP_SAM) == 0) {
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AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
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}
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AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
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@ -2244,16 +2255,18 @@ AhciModeInitialization (
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return EFI_DEVICE_ERROR;
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}
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//
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// Enable AE before accessing any AHCI registers
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//
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AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
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//
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// Collect AHCI controller information
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//
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Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
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Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
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//
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// Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set
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//
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if ((Capability & EFI_AHCI_CAP_SAM) == 0) {
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AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
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}
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//
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// Get the number of command slots per port supported by this HBA.
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//
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@ -1,7 +1,7 @@
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/** @file
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Header file for AHCI mode of ATA host controller.
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Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -17,6 +17,7 @@
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#define EFI_AHCI_BAR_INDEX 0x05
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#define EFI_AHCI_CAPABILITY_OFFSET 0x0000
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#define EFI_AHCI_CAP_SAM BIT18
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#define EFI_AHCI_CAP_SSS BIT27
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#define EFI_AHCI_CAP_S64A BIT31
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#define EFI_AHCI_GHC_OFFSET 0x0004
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