mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformInitLib: allow switching to 4-level paging
There are a number of mostly older guests such as RHEL-7 which do not support 5-level paging. This patch adds support for switching from 5-level paging mode back to 4-level paging mode. This is done in PEI, after inspecting the address space needed (installed memory and reservations configured via fw_cfg). By default small guests (which need less than 1 TB) will use 4-level paging mode. There is a fw_cfg override though, so it is possible to force the one or the other this way: qemu-system-x86_64 -fw_cfg name=opt/org.tianocode/PagingLevel,string=5 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Gerd Hoffmann
mergify[bot]
parent
f6092b5e2b
commit
2069a63a8e
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@ -898,6 +898,111 @@ PlatformScanHostProvided64BitPciMmioEnd (
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return EFI_NOT_FOUND;
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}
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VOID
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EFIAPI
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Switch4Level (
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VOID
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);
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/**
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Configure x64 paging levels.
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The OVMF ResetVector code will enter long mode with 5-level paging if the
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following conditions are true:
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(1) OVMF has been built with PcdUse5LevelPageTable = TRUE, and
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(2) the CPU supports 5-level paging (aka la57), and
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(3) the CPU supports gigabyte pages, and
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(4) the VM is not running in SEV mode.
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Condition (4) is a temporary stopgap for BaseMemEncryptSevLib not supporting
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5-level paging yet.
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This function looks at the virtual machine configuration, then decides
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whenever it will continue to use 5-level paging or downgrade to 4-level
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paging for better compatibility with older guest OS versions.
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There is a fw_cfg config option to explicitly request 4 or 5-level paging
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using 'qemu -fw_cfg name=opt/org.tianocode/PagingLevel,string=4|5'. If the
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option is present the requested paging level will be used.
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Should that not be the case the function checks the size of the address space
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needed, which is the RAM installed plus fw_cfg reservations. The downgrade
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to 4-level paging will happen for small guests where the address space needed
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is lower than 1TB.
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This function will also log the paging level used and the reason for that.
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**/
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STATIC
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VOID
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PlatformSetupPagingLevel (
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IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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#ifdef MDE_CPU_X64
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UINT32 PagingLevel;
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EFI_STATUS Status;
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IA32_CR4 Cr4;
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Cr4.UintN = AsmReadCr4 ();
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if (!Cr4.Bits.LA57) {
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/* The OvmfPkg ResetVector has NOT turned on 5-level paging, log the reason. */
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if (!PcdGetBool (PcdUse5LevelPageTable)) {
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DEBUG ((DEBUG_INFO, "%a: using 4-level paging (PcdUse5LevelPageTable disabled)\n", __func__));
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} else {
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DEBUG ((DEBUG_INFO, "%a: using 4-level paging (la57 not supported by cpu)\n", __func__));
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}
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return;
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}
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Status = QemuFwCfgParseUint32 (
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"opt/org.tianocode/PagingLevel",
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FALSE,
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&PagingLevel
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);
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switch (Status) {
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case EFI_NOT_FOUND:
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if (PlatformInfoHob->FirstNonAddress < (1ll << 40)) {
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//
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// If the highest address actually used is below 1TB switch back into
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// 4-level paging mode for better compatibility with older guests.
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//
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DEBUG ((DEBUG_INFO, "%a: using 4-level paging (default for small guest)\n", __func__));
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PagingLevel = 4;
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} else {
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DEBUG ((DEBUG_INFO, "%a: using 5-level paging (default for large guest)\n", __func__));
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PagingLevel = 5;
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}
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break;
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case EFI_SUCCESS:
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if ((PagingLevel != 4) && (PagingLevel != 5)) {
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DEBUG ((DEBUG_INFO, "%a: invalid paging level in fw_cfg: %d\n", __func__, PagingLevel));
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return;
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}
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DEBUG ((DEBUG_INFO, "%a: using %d-level paging (fw_cfg override)\n", __func__, PagingLevel));
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break;
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default:
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DEBUG ((DEBUG_WARN, "%a: QemuFwCfgParseUint32: %r\n", __func__, Status));
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return;
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}
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if (PagingLevel == 4) {
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Switch4Level ();
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}
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if (PagingLevel == 5) {
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/* The OvmfPkg ResetVector has turned on 5-level paging, nothing to do here. */
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}
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#endif
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}
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/**
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Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.
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**/
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@ -946,6 +1051,8 @@ PlatformAddressWidthInitialization (
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PlatformGetFirstNonAddress (PlatformInfoHob);
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}
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PlatformSetupPagingLevel (PlatformInfoHob);
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PlatformAddressWidthFromCpuid (PlatformInfoHob, TRUE);
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if (PlatformInfoHob->PhysMemAddressWidth != 0) {
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// physical address width is known
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@ -32,6 +32,7 @@
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[Sources.X64]
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IntelTdx.c
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X64/Paging.nasm
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[Packages]
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EmbeddedPkg/EmbeddedPkg.dec
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@ -63,6 +64,7 @@
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[Pcd]
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable
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[FixedPcd]
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase
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@ -0,0 +1,76 @@
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;------------------------------------------------------------------------------
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; @file
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;
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; Switch from 5-level paging mode to 4-level paging mode.
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;
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; This assumes everything (code, stack, page tables) is in 32-bit
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; address space. Which is true for PEI phase even in X64 builds
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; because low memory is used for early firmware setup.
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;
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; This also assumes the standard ResetVector GDT is active.
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;------------------------------------------------------------------------------
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SECTION .text
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BITS 64
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global ASM_PFX(Switch4Level)
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ASM_PFX(Switch4Level):
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; save regs
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push rax
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push rbx
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push rcx
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push rdx
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; cs:ip for long mode
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lea rax, [rel Switch4Level64]
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mov rbx, 0x3800000000 ; LINEAR_CODE64_SEL << 32
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or rax, rbx
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push rax
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; cs:ip for 32-bit mode
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lea rax, [rel Switch4Level32]
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mov rbx, 0x1000000000 ; LINEAR_CODE_SEL << 32
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or rax, rbx
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push rax
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; enter 32-bit mode
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retf
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Switch4Level64:
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; restore regs
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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BITS 32
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Switch4Level32:
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; disable paging
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mov eax, cr0
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btc eax, 31 ; clear PG
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mov cr0, eax
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; disable 5-level paging
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mov eax, cr4
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btc eax, 12 ; clear la57
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mov cr4, eax
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; fixup cr3 (dereference 5th level)
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mov eax, cr3
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mov eax, [ eax ]
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and eax, 0xfffff000
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mov cr3, eax
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; enable paging
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mov eax, cr0
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bts eax, 31 ; set PG
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mov cr0, eax
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; back to long mode
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retf
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