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Fix build break when doing 32-bit build with some certain C compiler option combinations. 

Use the library functions for shift operations in BaseLib for a 64-bit integer where the code is shared for 32-bit and 64-bit.
Defining bitfields in structures with > 32 bits will cause these types of issues on IA32 builds. So the largest bitfield should be type UINT32 with a max size of :32.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10983 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
rsun3 2010-10-28 02:01:43 +00:00
parent c52acd89e8
commit 23394428fd
2 changed files with 8 additions and 7 deletions
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13
UefiCpuPkg/Include/Register/LocalApic.h
View File

@ -62,12 +62,13 @@
typedef union {
struct {
UINT64 Reserved0:8; ///< Reserved.
UINT64 Bsp:1; ///< Processor is BSP.
UINT64 Reserved1:1; ///< Reserved.
UINT64 Extd:1; ///< Enable x2APIC mode.
UINT64 En:1; ///< xAPIC global enable/disable.
UINT64 ApicBase:52; ///< APIC Base physical address. The actual field width depends on physical address width.
UINT32 Reserved0:8; ///< Reserved.
UINT32 Bsp:1; ///< Processor is BSP.
UINT32 Reserved1:1; ///< Reserved.
UINT32 Extd:1; ///< Enable x2APIC mode.
UINT32 En:1; ///< xAPIC global enable/disable.
UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual field width depends on physical address width.
UINT32 ApicBaseHigh:32;
} Bits;
UINT64 Uint64;
} MSR_IA32_APIC_BASE;

2
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@ -151,7 +151,7 @@ SendIpi (
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// interrupt in x2APIC mode.
//
MsrValue = (((UINT64)ApicId) << 32) | IcrLow;
MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
}
}