tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ArmPlatformPkg/SP804Timer: Remove the SP810 System Controller dependency 

The SP804 drivers must not consider the presence of the SP810 System Controller
on the platform. The SP810 was used to enable the SP804 Dual Timers on ArmVExpress.
It is the role of the Platform specific driver to enable to the SP804 dual timers
if required.

The former SP810 initialization code has moved to ArmPlatformLib for ArmRealViewEb
and ArmVersatileExpress.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11744 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-06-03 09:32:39 +00:00
parent 9dcfb8e5c8
commit 23792dea0c
4 changed files with 55 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c
View File

@ -16,7 +16,9 @@
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Drivers/PL341Dmc.h>
#include <Drivers/SP804Timer.h>
/**
Return if Trustzone is supported by your platform
@ -109,7 +111,14 @@ ArmPlatformNormalInitialize (
VOID
)
{
// Nothing to do here
// Configure periodic timer (TIMER0) for 1MHz operation
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
// Configure 1MHz clock
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
// configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
// Configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
}
/**

13
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
View File

@ -17,10 +17,12 @@
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/SerialPortLib.h>
#include <Drivers/PL341Dmc.h>
#include <Drivers/PL301Axi.h>
#include <Drivers/PL310L2Cache.h>
#include <Library/SerialPortLib.h>
#include <Drivers/SP804Timer.h>
#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
@ -212,7 +214,14 @@ ArmPlatformNormalInitialize (
VOID
)
{
// Nothing to do here
// Configure periodic timer (TIMER0) for 1MHz operation
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
// Configure 1MHz clock
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
// configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
// Configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
}
/**

16
ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c
View File

@ -211,9 +211,9 @@ TimerDriverSetTimerPeriod (
MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
if (TimerPeriod == 0) {
// leave timer disabled from above, and...
// Leave timer disabled from above, and...
// disable timer 0/1 interrupt for a TimerPeriod of 0
// Disable timer 0/1 interrupt for a TimerPeriod of 0
Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector);
} else {
// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10)
@ -364,16 +364,13 @@ TimerInitialize (
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
// Configure 1MHz clock
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
// configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled
// Configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled
MmioWrite32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// enable the free running timer
// Enable the free running timer
MmioOr32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
// record free running tick value (should be close to 0xffffffff)
// Record free running tick value (should be close to 0xffffffff)
mLastTickCount = MmioRead32 (SP804_TIMER1_BASE + SP804_TIMER_CURRENT_REG);
// Disable the timer
@ -385,9 +382,6 @@ TimerInitialize (
Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// configure periodic timer (TIMER0) for 1MHz operation
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
// configure timer 0 for periodic operation, 32 bits, no prescaler, and interrupt enabled
MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE);

65
ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c
View File

@ -30,38 +30,32 @@ TimerConstructor (
VOID
)
{
// Check if Timer 2 is already initialized
if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
return RETURN_SUCCESS;
} else {
// configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
// configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// preload the timer count register
MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);
// enable the timer
MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
}
// Check if Timer 3 is already initialized
if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
return RETURN_SUCCESS;
} else {
// configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
// configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled
MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// enable the timer
MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
}
// Check if Timer 2 is already initialized
if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
return RETURN_SUCCESS;
} else {
// Configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// Preload the timer count register
MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);
// Enable the timer
MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
}
// Check if Timer 3 is already initialized
if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
return RETURN_SUCCESS;
} else {
// Configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled
MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
// Enable the timer
MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
}
return RETURN_SUCCESS;
}
/**
@ -141,11 +135,10 @@ GetPerformanceCounter (
{
// Free running 64-bit/32-bit counter is needed here.
// Don't think we need this to boot, just to do performance profile
// ASSERT (FALSE);
UINT32 val = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG);
ASSERT(val > 0);
return (UINT64)val;
UINT64 Value;
Value = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG);
ASSERT(Value > 0);
return Value;
}