mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/SP804Timer: Remove the SP810 System Controller dependency
The SP804 drivers must not consider the presence of the SP810 System Controller on the platform. The SP810 was used to enable the SP804 Dual Timers on ArmVExpress. It is the role of the Platform specific driver to enable to the SP804 dual timers if required. The former SP810 initialization code has moved to ArmPlatformLib for ArmRealViewEb and ArmVersatileExpress. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11744 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
9dcfb8e5c8
commit
23792dea0c
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@ -16,7 +16,9 @@
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/SP804Timer.h>
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/**
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Return if Trustzone is supported by your platform
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@ -109,7 +111,14 @@ ArmPlatformNormalInitialize (
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VOID
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)
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{
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// Nothing to do here
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// Configure periodic timer (TIMER0) for 1MHz operation
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
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// Configure 1MHz clock
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
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// configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// Configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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}
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/**
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@ -17,10 +17,12 @@
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SerialPortLib.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/PL301Axi.h>
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#include <Drivers/PL310L2Cache.h>
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#include <Library/SerialPortLib.h>
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#include <Drivers/SP804Timer.h>
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#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
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@ -212,7 +214,14 @@ ArmPlatformNormalInitialize (
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VOID
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)
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{
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// Nothing to do here
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// Configure periodic timer (TIMER0) for 1MHz operation
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
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// Configure 1MHz clock
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
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// configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// Configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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}
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/**
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@ -211,9 +211,9 @@ TimerDriverSetTimerPeriod (
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MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
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if (TimerPeriod == 0) {
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// leave timer disabled from above, and...
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// Leave timer disabled from above, and...
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// disable timer 0/1 interrupt for a TimerPeriod of 0
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// Disable timer 0/1 interrupt for a TimerPeriod of 0
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Status = gInterrupt->DisableInterruptSource (gInterrupt, gVector);
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} else {
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// Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10)
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@ -364,16 +364,13 @@ TimerInitialize (
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Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
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ASSERT_EFI_ERROR (Status);
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// Configure 1MHz clock
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
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// configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled
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// Configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled
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MmioWrite32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
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// enable the free running timer
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// Enable the free running timer
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MmioOr32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
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// record free running tick value (should be close to 0xffffffff)
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// Record free running tick value (should be close to 0xffffffff)
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mLastTickCount = MmioRead32 (SP804_TIMER1_BASE + SP804_TIMER_CURRENT_REG);
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// Disable the timer
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@ -385,9 +382,6 @@ TimerInitialize (
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Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
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ASSERT_EFI_ERROR (Status);
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// configure periodic timer (TIMER0) for 1MHz operation
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
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// configure timer 0 for periodic operation, 32 bits, no prescaler, and interrupt enabled
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MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE);
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@ -34,16 +34,13 @@ TimerConstructor (
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if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
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return RETURN_SUCCESS;
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} else {
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// configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
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// Configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled
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MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
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// preload the timer count register
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// Preload the timer count register
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MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1);
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// enable the timer
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// Enable the timer
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MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
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}
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@ -51,13 +48,10 @@ TimerConstructor (
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if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) {
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return RETURN_SUCCESS;
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} else {
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// configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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// configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled
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// Configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled
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MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1);
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// enable the timer
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// Enable the timer
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MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE);
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}
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@ -141,11 +135,10 @@ GetPerformanceCounter (
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{
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// Free running 64-bit/32-bit counter is needed here.
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// Don't think we need this to boot, just to do performance profile
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// ASSERT (FALSE);
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UINT32 val = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG);
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ASSERT(val > 0);
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return (UINT64)val;
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UINT64 Value;
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Value = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG);
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ASSERT(Value > 0);
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return Value;
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}
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