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UefiCpuPkg/PiSmmCpuDxeSmm: Avoid use global variable in InitSmmS3Cr3

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This patch is to avoid use global variable in InitSmmS3Cr3. No
function impact.

Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
This commit is contained in:
Jiaxin Wu 2024-08-01 16:59:28 +08:00 committed by mergify[bot]
parent 8f3e132512
commit 24a375fcdd
6 changed files with 29 additions and 20 deletions
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3
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@ -243,8 +243,9 @@ InitSmmS3ResumeState (
//
// Patch SmmS3ResumeState->SmmS3Cr3
// The SmmS3Cr3 is only used by S3Resume PEIM to switch CPU from 32bit to 64bit
//
InitSmmS3Cr3 ();
InitSmmS3Cr3 ((UINTN *)&SmmS3ResumeState->SmmS3Cr3);
}
}

10
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
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@ -1,7 +1,7 @@
/** @file
IA-32 processor specific functions to enable SMM profile.
Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -12,13 +12,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/**
Create SMM page table for S3 path.
@param[out] Cr3 The base address of the page tables.
**/
VOID
InitSmmS3Cr3 (
VOID
OUT UINTN *Cr3
)
{
mSmmS3ResumeState->SmmS3Cr3 = GenSmmPageTable (PagingPae, mPhysicalAddressBits);
ASSERT (Cr3 != NULL);
*Cr3 = GenSmmPageTable (PagingPae, mPhysicalAddressBits);
return;
}

6
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
View File

@ -1,7 +1,7 @@
/** @file
IA-32 processor specific header file to enable SMM profile.
Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -73,10 +73,12 @@ RestorePageTableAbove4G (
/**
Create SMM page table for S3 path.
@param[out] Cr3 The base address of the page tables.
**/
VOID
InitSmmS3Cr3 (
VOID
OUT UINTN *Cr3
);
/**

11
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
View File

@ -96,12 +96,11 @@ typedef struct {
UINT64 SmiCmd;
} SMM_PROFILE_ENTRY;
extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
extern UINTN gSmiExceptionHandlers[];
extern BOOLEAN mXdSupported;
X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;
X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;
extern UINTN *mPFEntryCount;
extern UINTN gSmiExceptionHandlers[];
extern BOOLEAN mXdSupported;
X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;
X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;
extern UINTN *mPFEntryCount;
extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];

13
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
View File

@ -1,7 +1,7 @@
/** @file
X64 processor specific functions to enable SMM profile.
Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2024, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@ -29,20 +29,21 @@ UINT64 *mPFPageUplink[MAX_PF_PAGE_COUNT];
/**
Create SMM page table for S3 path.
@param[out] Cr3 The base address of the page tables.
**/
VOID
InitSmmS3Cr3 (
VOID
OUT UINTN *Cr3
)
{
ASSERT (Cr3 != NULL);
//
// Generate level4 page table for the first 4GB memory space
// Return the address of PML4 (to set CR3)
//
//
// The SmmS3Cr3 is only used by S3Resume PEIM to switch CPU from 32bit to 64bit
//
mSmmS3ResumeState->SmmS3Cr3 = (UINT32)GenSmmPageTable (Paging4Level, 32);
*Cr3 = GenSmmPageTable (Paging4Level, 32);
return;
}

6
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h
View File

@ -1,7 +1,7 @@
/** @file
X64 processor specific header file to enable SMM profile.
Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2012 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -81,10 +81,12 @@ RestorePageTableAbove4G (
/**
Create SMM page table for S3 path.
@param[out] Cr3 The base address of the page tables.
**/
VOID
InitSmmS3Cr3 (
VOID
OUT UINTN *Cr3
);
/**