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IntelFsp2WrapperPkg: Support 64bit FspResetType for X64 build.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999 FspResetType will be either 32bit or 64 bit basing on the build type. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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@ -97,7 +97,7 @@ OnPciEnumerationComplete (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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if (Status != EFI_SUCCESS) {
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@ -140,7 +140,7 @@ OnReadyToBoot (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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if (Status != EFI_SUCCESS) {
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@ -184,7 +184,7 @@ OnEndOfFirmware (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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if (Status != EFI_SUCCESS) {
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@ -43,16 +43,15 @@ extern EFI_GUID gFspHobGuid;
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@return FSP-M UPD Data Address
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**/
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UINTN
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GetFspmUpdDataAddress (
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VOID
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)
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{
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if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
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return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
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return (UINTN)PcdGet64 (PcdFspmUpdDataAddress64);
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} else {
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return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
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return (UINTN)PcdGet32 (PcdFspmUpdDataAddress);
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}
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}
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@ -97,7 +96,7 @@ PeiFspMemoryInit (
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//
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// External UPD is ready, get the buffer from PCD pointer.
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//
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FspmUpdDataPtr = (VOID *) GetFspmUpdDataAddress();
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FspmUpdDataPtr = (VOID *)GetFspmUpdDataAddress ();
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ASSERT (FspmUpdDataPtr != NULL);
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}
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@ -115,6 +114,7 @@ PeiFspMemoryInit (
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DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
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DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootMode));
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}
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DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", &FspHobListPtr));
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TimeStampCounterStart = AsmReadTsc ();
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@ -129,7 +129,7 @@ PeiFspMemoryInit (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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if (EFI_ERROR (Status)) {
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@ -96,7 +96,7 @@ S3EndOfPeiNotify (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
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@ -108,7 +108,7 @@ S3EndOfPeiNotify (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;
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@ -120,7 +120,7 @@ S3EndOfPeiNotify (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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return EFI_SUCCESS;
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@ -186,16 +186,15 @@ FspSiliconInitDoneGetFspHobList (
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@return FSP-S UPD Data Address
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**/
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UINTN
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GetFspsUpdDataAddress (
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VOID
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)
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{
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if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
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return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
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return (UINTN)PcdGet64 (PcdFspsUpdDataAddress64);
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} else {
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return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
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return (UINTN)PcdGet32 (PcdFspsUpdDataAddress);
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}
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}
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@ -310,7 +309,7 @@ PeiMemoryDiscoveredNotify (
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SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
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CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
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} else {
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FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress();
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FspsUpdDataPtr = (FSPS_UPD_COMMON *)GetFspsUpdDataAddress ();
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ASSERT (FspsUpdDataPtr != NULL);
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}
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@ -327,7 +326,7 @@ PeiMemoryDiscoveredNotify (
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//
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if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
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DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));
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CallFspWrapperResetSystem ((UINT32)Status);
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CallFspWrapperResetSystem (Status);
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}
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if (EFI_ERROR (Status)) {
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@ -74,7 +74,7 @@ GetS3MemoryInfo (
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VOID
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EFIAPI
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CallFspWrapperResetSystem (
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IN UINT32 FspStatusResetType
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IN EFI_STATUS FspStatusResetType
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);
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#endif
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@ -121,6 +121,10 @@ Execute32BitCode (
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//
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AsmReadIdtr (&Idtr);
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Status = AsmExecute32BitCode (Function, Param1, Param2, &mGdt);
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//
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// Convert FSP Status code from 32bit to 64bit to match caller expectation.
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//
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Status = (Status & ~(BIT31 + BIT30)) | LShiftU64 (Status & (BIT31 + BIT30), 32);
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AsmWriteIdtr (&Idtr);
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return Status;
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@ -150,4 +154,3 @@ Execute64BitCode (
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return Status;
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}
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@ -86,7 +86,7 @@ GetS3MemoryInfo (
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VOID
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EFIAPI
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CallFspWrapperResetSystem (
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IN UINT32 FspStatusResetType
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IN EFI_STATUS FspStatusResetType
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)
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{
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//
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