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IntelFsp2WrapperPkg: Support 64bit FspResetType for X64 build.

Browse Source 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999
FspResetType will be either 32bit or 64 bit basing on
the build type.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu 2022-07-18 21:08:31 -07:00 committed by mergify[bot]
parent 140446cd59
commit 24eac4caf3
6 changed files with 21 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.c
View File

@ -97,7 +97,7 @@ OnPciEnumerationComplete (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {
@ -140,7 +140,7 @@ OnReadyToBoot (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {
@ -184,7 +184,7 @@ OnEndOfFirmware (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (Status != EFI_SUCCESS) { if (Status != EFI_SUCCESS) {

10
IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
View File

@ -43,16 +43,15 @@ extern EFI_GUID gFspHobGuid;
@return FSP-M UPD Data Address @return FSP-M UPD Data Address
**/ **/
UINTN UINTN
GetFspmUpdDataAddress ( GetFspmUpdDataAddress (
VOID VOID
) )
{ {
if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) { if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64); return (UINTN)PcdGet64 (PcdFspmUpdDataAddress64);
} else { } else {
return (UINTN) PcdGet32 (PcdFspmUpdDataAddress); return (UINTN)PcdGet32 (PcdFspmUpdDataAddress);
} }
} }
@ -97,7 +96,7 @@ PeiFspMemoryInit (
// //
// External UPD is ready, get the buffer from PCD pointer. // External UPD is ready, get the buffer from PCD pointer.
// //
FspmUpdDataPtr = (VOID *) GetFspmUpdDataAddress(); FspmUpdDataPtr = (VOID *)GetFspmUpdDataAddress ();
ASSERT (FspmUpdDataPtr != NULL); ASSERT (FspmUpdDataPtr != NULL);
} }
@ -115,6 +114,7 @@ PeiFspMemoryInit (
DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize)); DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootMode)); DEBUG ((DEBUG_INFO, " BootMode - 0x%x\n", ((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.BootMode));
} }
DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", &FspHobListPtr)); DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", &FspHobListPtr));
TimeStampCounterStart = AsmReadTsc (); TimeStampCounterStart = AsmReadTsc ();
@ -129,7 +129,7 @@ PeiFspMemoryInit (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

15
IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
View File

@ -96,7 +96,7 @@ S3EndOfPeiNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase AfterPciEnumeration requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot; NotifyPhaseParams.Phase = EnumInitPhaseReadyToBoot;
@ -108,7 +108,7 @@ S3EndOfPeiNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase ReadyToBoot requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware; NotifyPhaseParams.Phase = EnumInitPhaseEndOfFirmware;
@ -120,7 +120,7 @@ S3EndOfPeiNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FSP S3NotifyPhase EndOfFirmware requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@ -186,16 +186,15 @@ FspSiliconInitDoneGetFspHobList (
@return FSP-S UPD Data Address @return FSP-S UPD Data Address
**/ **/
UINTN UINTN
GetFspsUpdDataAddress ( GetFspsUpdDataAddress (
VOID VOID
) )
{ {
if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) { if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64); return (UINTN)PcdGet64 (PcdFspsUpdDataAddress64);
} else { } else {
return (UINTN) PcdGet32 (PcdFspsUpdDataAddress); return (UINTN)PcdGet32 (PcdFspsUpdDataAddress);
} }
} }
@ -310,7 +309,7 @@ PeiMemoryDiscoveredNotify (
SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset); SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize); CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
} else { } else {
FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress(); FspsUpdDataPtr = (FSPS_UPD_COMMON *)GetFspsUpdDataAddress ();
ASSERT (FspsUpdDataPtr != NULL); ASSERT (FspsUpdDataPtr != NULL);
} }
@ -327,7 +326,7 @@ PeiMemoryDiscoveredNotify (
// //
if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) { if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= FSP_STATUS_RESET_REQUIRED_8)) {
DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status)); DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));
CallFspWrapperResetSystem ((UINT32)Status); CallFspWrapperResetSystem (Status);
} }
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {

2
IntelFsp2WrapperPkg/Include/Library/FspWrapperPlatformLib.h
View File

@ -74,7 +74,7 @@ GetS3MemoryInfo (
VOID VOID
EFIAPI EFIAPI
CallFspWrapperResetSystem ( CallFspWrapperResetSystem (
IN UINT32 FspStatusResetType IN EFI_STATUS FspStatusResetType
); );
#endif #endif

5
IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c
View File

@ -121,6 +121,10 @@ Execute32BitCode (
// //
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
Status = AsmExecute32BitCode (Function, Param1, Param2, &mGdt); Status = AsmExecute32BitCode (Function, Param1, Param2, &mGdt);
//
// Convert FSP Status code from 32bit to 64bit to match caller expectation.
//
Status = (Status & ~(BIT31 + BIT30)) | LShiftU64 (Status & (BIT31 + BIT30), 32);
AsmWriteIdtr (&Idtr); AsmWriteIdtr (&Idtr);
return Status; return Status;
@ -150,4 +154,3 @@ Execute64BitCode (
return Status; return Status;
} }

2
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/FspWrapperPlatformLibSample.c
View File

@ -86,7 +86,7 @@ GetS3MemoryInfo (
VOID VOID
EFIAPI EFIAPI
CallFspWrapperResetSystem ( CallFspWrapperResetSystem (
IN UINT32 FspStatusResetType IN EFI_STATUS FspStatusResetType
) )
{ {
// //