mirror of https://github.com/acidanthera/audk.git
ArmPkg: Fixed RVCT compiler warnings
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13490 6f19259b-4bc3-4df7-8a09-765794883524
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@ -95,12 +95,12 @@ typedef enum {
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//
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// ARM Cpu IDs
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//
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#define ARM_CPU_IMPLEMENTER_MASK (0xFF << 24)
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#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41 << 24)
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#define ARM_CPU_IMPLEMENTER_DEC (0x44 << 24)
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#define ARM_CPU_IMPLEMENTER_MOT (0x4D << 24)
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#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51 << 24)
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#define ARM_CPU_IMPLEMENTER_MARVELL (0x56 << 24)
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#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
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#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
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#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
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#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
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#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
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#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
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#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
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#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
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@ -97,4 +97,4 @@ ReadCLIDR
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mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
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bx lr
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END
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END
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@ -80,4 +80,3 @@ L43
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ldmfd sp!, {r4-r11, pc}
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END
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@ -55,3 +55,5 @@ __aeabi_memclr4
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mov r2, r1
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mov r1, #0
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b __aeabi_memset
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END
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@ -104,9 +104,9 @@
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// L2x0 Cache Controller Base Address
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//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
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#define ARM_EB_SYS_PROC_ID_MASK (0xFF << 24)
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#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (0x0E << 24)
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#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)
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#define ARM_EB_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
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#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (UINT32)(0x0EU << 24)
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#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
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/*******************************************
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// System Configuration Control
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@ -54,3 +54,5 @@ ArmPlatformSecBootAction
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ArmPlatformSecBootMemoryInit
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// The SMC does not need to be initialized for RTSM
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bx lr
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END
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@ -48,11 +48,11 @@
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// VRAM offset for the PL111 Colour LCD Controller on the motherboard
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#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
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#define ARM_VE_SYS_PROC_ID_MASK (0xFF << 24)
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#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (0xFF << 24)
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#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)
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#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (0x12 << 24)
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#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (0x14 << 24)
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#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
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#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)
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#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
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#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)
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#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)
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//
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// Sites where the peripheral is fitted
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@ -123,3 +123,5 @@ ArmPlatformSecBootMemoryInit
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ldr r0, [r2, #0]
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bx r5
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END
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@ -50,3 +50,5 @@ ArmPlatformSecBootAction
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ArmPlatformSecBootMemoryInit
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// The SMC does not need to be initialized for RTSM
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bx lr
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END
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@ -58,3 +58,5 @@ PL35xSmcSetRefresh
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str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
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str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
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blx lr
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END
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@ -45,3 +45,5 @@ ArmPlatformSecBootAction
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ArmPlatformSecBootMemoryInit
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// The SMC does not need to be initialized for RTSM
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bx lr
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END
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@ -16,6 +16,7 @@
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#include <Library/ArmLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmPlatformSecLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PrintLib.h>
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@ -36,7 +36,7 @@ _ModuleEntryPoint
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_SetSVCMode
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// Enter SVC mode, Disable FIQ and IRQ
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mov r1, #0x13|0x80|0x40
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mov r1, #0x13 :OR: 0x80 :OR: 0x40
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msr CPSR_c, r1
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// Check if we can install the stack at the top of the System Memory or if we need
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