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ArmPkg: Fixed RVCT compiler warnings

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Signed-off-by: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13490 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-07-04 20:06:23 +00:00
parent 9736c29721
commit 2575b72620
13 changed files with 29 additions and 17 deletions
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12
ArmPkg/Include/Library/ArmLib.h
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@ -95,12 +95,12 @@ typedef enum {
// //
// ARM Cpu IDs // ARM Cpu IDs
// //
#define ARM_CPU_IMPLEMENTER_MASK (0xFF << 24) #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41 << 24) #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
#define ARM_CPU_IMPLEMENTER_DEC (0x44 << 24) #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
#define ARM_CPU_IMPLEMENTER_MOT (0x4D << 24) #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51 << 24) #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
#define ARM_CPU_IMPLEMENTER_MARVELL (0x56 << 24) #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4) #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4) #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)

2
ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
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@ -97,4 +97,4 @@ ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr bx lr
END END

1
ArmPkg/Library/BaseMemoryLibStm/Arm/SetMem.asm
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@ -80,4 +80,3 @@ L43
ldmfd sp!, {r4-r11, pc} ldmfd sp!, {r4-r11, pc}
END END

2
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.asm
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@ -55,3 +55,5 @@ __aeabi_memclr4
mov r2, r1 mov r2, r1
mov r1, #0 mov r1, #0
b __aeabi_memset b __aeabi_memset
END

6
ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h
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@ -104,9 +104,9 @@
// L2x0 Cache Controller Base Address // L2x0 Cache Controller Base Address
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/ //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
#define ARM_EB_SYS_PROC_ID_MASK (0xFF << 24) #define ARM_EB_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (0x0E << 24) #define ARM_EB_SYS_PROC_ID_CORTEX_A8 (UINT32)(0x0EU << 24)
#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (0x0C << 24) #define ARM_EB_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
/******************************************* /*******************************************
// System Configuration Control // System Configuration Control

2
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbSecLibRTSM/ArmRealViewEbBoot.asm
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@ -54,3 +54,5 @@ ArmPlatformSecBootAction
ArmPlatformSecBootMemoryInit ArmPlatformSecBootMemoryInit
// The SMC does not need to be initialized for RTSM // The SMC does not need to be initialized for RTSM
bx lr bx lr
END

10
ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h
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@ -48,11 +48,11 @@
// VRAM offset for the PL111 Colour LCD Controller on the motherboard // VRAM offset for the PL111 Colour LCD Controller on the motherboard
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) #define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
#define ARM_VE_SYS_PROC_ID_MASK (0xFF << 24) #define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (0xFF << 24) #define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)
#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (0x0C << 24) #define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (0x12 << 24) #define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)
#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (0x14 << 24) #define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)
// //
// Sites where the peripheral is fitted // Sites where the peripheral is fitted

2
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Boot.asm
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@ -123,3 +123,5 @@ ArmPlatformSecBootMemoryInit
ldr r0, [r2, #0] ldr r0, [r2, #0]
bx r5 bx r5
END

2
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMBoot.asm
View File

@ -50,3 +50,5 @@ ArmPlatformSecBootAction
ArmPlatformSecBootMemoryInit ArmPlatformSecBootMemoryInit
// The SMC does not need to be initialized for RTSM // The SMC does not need to be initialized for RTSM
bx lr bx lr
END

2
ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm
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@ -58,3 +58,5 @@ PL35xSmcSetRefresh
str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET] str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET] str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
blx lr blx lr
END

2
ArmPlatformPkg/Library/ArmPlatformSecLibNull/ArmPlatformLibNullBoot.asm
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@ -45,3 +45,5 @@ ArmPlatformSecBootAction
ArmPlatformSecBootMemoryInit ArmPlatformSecBootMemoryInit
// The SMC does not need to be initialized for RTSM // The SMC does not need to be initialized for RTSM
bx lr bx lr
END

1
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
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@ -16,6 +16,7 @@
#include <Library/ArmLib.h> #include <Library/ArmLib.h>
#include <Library/ArmGicLib.h> #include <Library/ArmGicLib.h>
#include <Library/ArmPlatformSecLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/PrintLib.h> #include <Library/PrintLib.h>

2
ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
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@ -36,7 +36,7 @@ _ModuleEntryPoint
_SetSVCMode _SetSVCMode
// Enter SVC mode, Disable FIQ and IRQ // Enter SVC mode, Disable FIQ and IRQ
mov r1, #0x13|0x80|0x40 mov r1, #0x13 :OR: 0x80 :OR: 0x40
msr CPSR_c, r1 msr CPSR_c, r1
// Check if we can install the stack at the top of the System Memory or if we need // Check if we can install the stack at the top of the System Memory or if we need