mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmJunoPkg/AcpiTables: Updated with new ACPI 5.1 Tables & Definitions
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16654 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
7c1712f05a
commit
2596e61a9b
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@ -46,3 +46,6 @@
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
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gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
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gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
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gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
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gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
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@ -1,7 +1,7 @@
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/** @file
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Differentiated System Description Table Fields (DSDT)
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Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -19,27 +19,27 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
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//
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// A57x2-A53x4 Processor declaration
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//
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Device(CPU0) { // A57-0: Cluster 0, Cpu 0
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Device(CPU0) { // A53-0: Cluster 1, Cpu 0
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Name(_HID, "ACPI0007")
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Name(_UID, 0)
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}
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Device(CPU1) { // A57-1: Cluster 0, Cpu 1
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Device(CPU1) { // A53-1: Cluster 1, Cpu 1
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Name(_HID, "ACPI0007")
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Name(_UID, 1)
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}
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Device(CPU2) { // A53-0: Cluster 1, Cpu 0
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Device(CPU2) { // A53-2: Cluster 1, Cpu 2
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Name(_HID, "ACPI0007")
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Name(_UID, 2)
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}
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Device(CPU3) { // A53-1: Cluster 1, Cpu 1
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Device(CPU3) { // A53-3: Cluster 1, Cpu 3
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Name(_HID, "ACPI0007")
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Name(_UID, 3)
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}
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Device(CPU4) { // A53-2: Cluster 1, Cpu 2
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Device(CPU4) { // A57-0: Cluster 0, Cpu 0
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Name(_HID, "ACPI0007")
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Name(_UID, 4)
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}
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Device(CPU5) { // A53-3: Cluster 1, Cpu 3
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Device(CPU5) { // A57-1: Cluster 0, Cpu 1
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Name(_HID, "ACPI0007")
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Name(_UID, 5)
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}
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@ -63,12 +63,24 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
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//
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Device(ETH0) {
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Name(_HID, "ARMH9118")
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Name(_UID, Zero)
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Name(_CRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, 0x1A000000, 0x1000)
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Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 }
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})
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}
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// UART PL011
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Device(COM0) {
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Name(_HID, "ARMH0011")
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Name(_CID, "PL011")
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Name(_UID, Zero)
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Name(_CRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000)
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Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 }
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})
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}
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//
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// USB Host Controller
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//
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@ -17,12 +17,21 @@
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#include <Library/AcpiLib.h>
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#include <IndustryStandard/Acpi.h>
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#ifdef ARM_JUNO_ACPI_5_0
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EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
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ARM_ACPI_HEADER (
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EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE,
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EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
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),
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#else
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EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
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ARM_ACPI_HEADER (
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EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
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EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
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),
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#endif
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0, // UINT32 FirmwareCtrl
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0, // UINT32 Dsdt
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EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
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@ -63,7 +72,12 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
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EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
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NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
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0, // UINT8 ResetValue
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#if ARM_JUNO_ACPI_5_0
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{EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved2[3]
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#else
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EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
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EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
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#endif
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0, // UINT64 XFirmwareCtrl
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0, // UINT64 XDsdt
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NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
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@ -28,34 +28,73 @@
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#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
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#else
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#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
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#define SYSTEM_TIMER_BASE_ADDRESS 0
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#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
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#endif
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#define GTDT_TIMER_EDGE_TRIGGERED (1 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE)
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#define GTDT_TIMER_LEVEL_TRIGGERED (0 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE)
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#define GTDT_TIMER_ACTIVE_LOW (1 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY)
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#define GTDT_TIMER_ACTIVE_HIGH (0 << EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY)
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#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
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#define GTDT_TIMER_LEVEL_TRIGGERED 0
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#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
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#define GTDT_TIMER_ACTIVE_HIGH 0
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#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
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EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
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#ifdef ARM_JUNO_ACPI_5_0
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EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
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ARM_ACPI_HEADER(
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EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE,
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EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
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),
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SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
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GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags
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FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
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FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
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FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
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FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
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GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags
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};
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SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
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GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags
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FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
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FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
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FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
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FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
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GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags
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};
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#else
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
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EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT];
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} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
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#pragma pack ()
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
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{
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ARM_ACPI_HEADER(
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE,
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EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
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),
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SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
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0, // UINT32 Reserved
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FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
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FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
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FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
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FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
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GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
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0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
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JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
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sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
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},
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{
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EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
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FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
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EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
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FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
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}
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};
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#endif
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VOID*
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ReferenceAcpiTable (
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@ -1,7 +1,7 @@
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/** @file
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* Multiple APIC Description Table (MADT)
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*
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* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
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* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -15,53 +15,111 @@
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#include "ArmPlatform.h"
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#include <Library/AcpiLib.h>
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#include <Library/ArmLib.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/Acpi.h>
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
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#pragma pack ()
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//
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// Multiple APIC Description Table
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//
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_1_0_APIC_SIGNATURE,
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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),
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//
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// MADT specific fields
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//
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0, // LocalApicAddress
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0, // Flags
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},
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{
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// Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)
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// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of
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// ACPI v5.0).
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// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
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// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
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// For now we leave CPU2 (A53-0) at the first position.
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// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
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// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 2, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 3, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 4, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 5, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 0, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 1, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1
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},
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
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};
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#ifdef ARM_JUNO_ACPI_5_0
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
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EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
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#pragma pack ()
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_1_0_APIC_SIGNATURE,
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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),
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//
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// MADT specific fields
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//
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0, // LocalApicAddress
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0, // Flags
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},
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{
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// Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)
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// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of
|
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// ACPI v5.0).
|
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// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
|
||||
// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
|
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// For now we leave CPU2 (A53-0) at the first position.
|
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// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
|
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// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0
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EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1
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},
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
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};
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#else
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#pragma pack (1)
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typedef struct {
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
|
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EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
|
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EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
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} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
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#pragma pack ()
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
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{
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ARM_ACPI_HEADER (
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EFI_ACPI_1_0_APIC_SIGNATURE,
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
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EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
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),
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//
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// MADT specific fields
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||||
//
|
||||
0, // LocalApicAddress
|
||||
0, // Flags
|
||||
},
|
||||
{
|
||||
// Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
|
||||
// GsivId, GicRBase, Mpidr)
|
||||
// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
|
||||
// ACPI v5.1).
|
||||
// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
|
||||
// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
|
||||
// For now we leave CPU2 (A53-0) at the first position.
|
||||
// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
|
||||
// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
|
||||
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
|
||||
2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
|
||||
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
|
||||
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
|
||||
3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
|
||||
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
|
||||
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2
|
||||
4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
|
||||
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
|
||||
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3
|
||||
5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
|
||||
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
|
||||
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0
|
||||
0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
|
||||
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
|
||||
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1
|
||||
1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
|
||||
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
|
||||
},
|
||||
EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)
|
||||
};
|
||||
#endif
|
||||
|
||||
VOID*
|
||||
ReferenceAcpiTable (
|
||||
|
|
|
|||
|
|
@ -75,4 +75,9 @@
|
|||
EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
|
||||
}
|
||||
|
||||
#define JUNO_WATCHDOG_COUNT 2
|
||||
|
||||
// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
|
||||
//#define ARM_JUNO_ACPI_5_0
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue