mirror of https://github.com/acidanthera/audk.git
DynamicTablesPkg: Arm NameSpace Objects
The dynamic tables frameworks core communicates with the platform specific implementation using the configuration manager protocol interface. The dynamic tables framework core uses this interface to retrieve information required for generating the firmware tables. This information is represented in the form of objects, which are classified as standard namespace objects, Arm namespace objects or as Custom/OEM namespace objects. This patch introduces the definitions for the Arm namespace objects. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <alexei.fedorov@arm.com>
This commit is contained in:
Sami Mujawar
parent
6872900e12
commit
26147c7702
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/** @file
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Copyright (c) 2017 - 2018, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@par Glossary:
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- Cm or CM - Configuration Manager
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- Obj or OBJ - Object
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- Std or STD - Standard
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**/
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#ifndef ARM_NAMESPACE_OBJECTS_H_
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#define ARM_NAMESPACE_OBJECTS_H_
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#include <StandardNameSpaceObjects.h>
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#pragma pack(1)
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/** The EARM_OBJECT_ID enum describes the Object IDs
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in the ARM Namespace
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*/
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typedef enum ArmObjectID {
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EArmObjReserved, ///< 0 - Reserved
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EArmObjBootArchInfo, ///< 1 - Boot Architecture Info
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EArmObjCpuInfo, ///< 2 - CPU Info
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EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info
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EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info
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EArmObjGicDInfo, ///< 5 - GIC Distributor Info
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EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info
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EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info
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EArmObjGicItsInfo, ///< 8 - GIC ITS Info
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EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info
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EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info
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EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info
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EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info
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EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info
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EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
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EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info
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EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id
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EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT
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EArmObjItsGroup, ///< 18 - ITS Group
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EArmObjNamedComponent, ///< 19 - Named Component
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EArmObjRootComplex, ///< 20 - Root Complex
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EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2
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EArmObjSmmuV3, ///< 22 - SMMUv3
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EArmObjPmcg, ///< 23 - PMCG
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EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array
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EArmObjIdMapping, ///< 25 - ID Mapping
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EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array
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EArmObjMax
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} EARM_OBJECT_ID;
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/** A structure that describes the
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ARM Boot Architecture flags.
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*/
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typedef struct CmArmBootArchInfo {
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/** This is the ARM_BOOT_ARCH flags field of the FADT Table
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described in the ACPI Table Specification.
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*/
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UINT32 BootArchFlags;
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} CM_ARM_BOOT_ARCH_INFO;
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typedef struct CmArmCpuInfo {
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// Reserved for use when SMBIOS tables are implemented
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} CM_ARM_CPU_INFO;
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typedef struct CmArmCpuInfoList {
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UINT32 CpuCount;
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CM_ARM_CPU_INFO * CpuInfo;
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} CM_ARM_CPU_INFO_LIST;
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/** A structure that describes the
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Power Management Profile Information for the Platform.
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*/
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typedef struct CmArmPowerManagementProfileInfo {
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/** This is the Preferred_PM_Profile field of the FADT Table
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described in the ACPI Specification
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*/
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UINT8 PowerManagementProfile;
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} CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
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/** A structure that describes the
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GIC CPU Interface for the Platform.
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*/
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typedef struct CmArmGicCInfo {
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/// The GIC CPU Interface number.
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UINT32 CPUInterfaceNumber;
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/** The ACPI Processor UID. This must match the
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_UID of the CPU Device object information described
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in the DSDT/SSDT for the CPU.
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*/
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UINT32 AcpiProcessorUid;
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/** The flags field as described by the GICC structure
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in the ACPI Specification.
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*/
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UINT32 Flags;
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/** The parking protocol version field as described by
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the GICC structure in the ACPI Specification.
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*/
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UINT32 ParkingProtocolVersion;
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/** The Performance Interrupt field as described by
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the GICC structure in the ACPI Specification.
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*/
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UINT32 PerformanceInterruptGsiv;
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/** The CPU Parked address field as described by
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the GICC structure in the ACPI Specification.
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*/
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UINT64 ParkedAddress;
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/** The base address for the GIC CPU Interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 PhysicalBaseAddress;
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/** The base address for GICV interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 GICV;
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/** The base address for GICH interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 GICH;
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/** The GICV maintenance interrupt
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT32 VGICMaintenanceInterrupt;
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/** The base address for GICR interface
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 GICRBaseAddress;
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/** The MPIDR for the CPU
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT64 MPIDR;
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/** The Processor Power Efficiency class
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as described by the GICC structure in the
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ACPI Specification.
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*/
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UINT8 ProcessorPowerEfficiencyClass;
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} CM_ARM_GICC_INFO;
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/** A structure that describes the
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GIC Distributor information for the Platform.
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*/
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typedef struct CmArmGicDInfo {
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/// The GIC Distributor ID.
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UINT32 GicId;
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/// The Physical Base address for the GIC Distributor.
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UINT64 PhysicalBaseAddress;
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/** The global system interrupt
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number where this GIC Distributor's
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interrupt inputs start.
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*/
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UINT32 SystemVectorBase;
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/** The GIC version as described
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by the GICD structure in the
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ACPI Specification.
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*/
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UINT8 GicVersion;
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} CM_ARM_GICD_INFO;
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/** A structure that describes the
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GIC MSI Frame information for the Platform.
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*/
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typedef struct CmArmGicMsiFrameInfo {
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/// The GIC MSI Frame ID
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UINT32 GicMsiFrameId;
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/// The Physical base address for the MSI Frame
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UINT64 PhysicalBaseAddress;
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/** The GIC MSI Frame flags
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as described by the GIC MSI frame
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structure in the ACPI Specification.
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*/
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UINT32 Flags;
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/// SPI Count used by this frame
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UINT16 SPICount;
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/// SPI Base used by this frame
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UINT16 SPIBase;
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} CM_ARM_GIC_MSI_FRAME_INFO;
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/** A structure that describes the
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GIC Redistributor information for the Platform.
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*/
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typedef struct CmArmGicRedistInfo {
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/** The physical address of a page range
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containing all GIC Redistributors.
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*/
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UINT64 DiscoveryRangeBaseAddress;
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/// Length of the GIC Redistributor Discovery page range
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UINT32 DiscoveryRangeLength;
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} CM_ARM_GIC_REDIST_INFO;
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/** A structure that describes the
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GIC Interrupt Translation Service information for the Platform.
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*/
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typedef struct CmArmGicItsInfo {
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/// The GIC ITS ID
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UINT32 GicItsId;
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/// The physical address for the Interrupt Translation Service
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UINT64 PhysicalBaseAddress;
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} CM_ARM_GIC_ITS_INFO;
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/** A structure that describes the
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Serial Port information for the Platform.
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*/
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typedef struct CmArmSerialPortInfo {
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/// The physical base address for the serial port
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UINT64 BaseAddress;
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/// The serial port interrupt
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UINT32 Interrupt;
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/// The serial port baud rate
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UINT64 BaudRate;
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/// The serial port clock
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UINT32 Clock;
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/// Serial Port subtype
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UINT16 PortSubtype;
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} CM_ARM_SERIAL_PORT_INFO;
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/** A structure that describes the
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Generic Timer information for the Platform.
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*/
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typedef struct CmArmGenericTimerInfo {
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/// The physical base address for the counter control frame
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UINT64 CounterControlBaseAddress;
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/// The physical base address for the counter read frame
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UINT64 CounterReadBaseAddress;
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/// The secure PL1 timer interrupt
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UINT32 SecurePL1TimerGSIV;
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/// The secure PL1 timer flags
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UINT32 SecurePL1TimerFlags;
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/// The non-secure PL1 timer interrupt
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UINT32 NonSecurePL1TimerGSIV;
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/// The non-secure PL1 timer flags
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UINT32 NonSecurePL1TimerFlags;
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/// The virtual timer interrupt
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UINT32 VirtualTimerGSIV;
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/// The virtual timer flags
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UINT32 VirtualTimerFlags;
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/// The non-secure PL2 timer interrupt
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UINT32 NonSecurePL2TimerGSIV;
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/// The non-secure PL2 timer flags
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UINT32 NonSecurePL2TimerFlags;
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} CM_ARM_GENERIC_TIMER_INFO;
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/** A structure that describes the
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Platform Generic Block Timer Frame information for the Platform.
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*/
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typedef struct CmArmGTBlockTimerFrameInfo {
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/// The Generic Timer frame number
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UINT8 FrameNumber;
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/// The physical base address for the CntBase block
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UINT64 PhysicalAddressCntBase;
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/// The physical base address for the CntEL0Base block
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UINT64 PhysicalAddressCntEL0Base;
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/// The physical timer interrupt
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UINT32 PhysicalTimerGSIV;
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/** The physical timer flags as described by the GT Block
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Timer frame Structure in the ACPI Specification.
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*/
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UINT32 PhysicalTimerFlags;
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/// The virtual timer interrupt
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UINT32 VirtualTimerGSIV;
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/** The virtual timer flags as described by the GT Block
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Timer frame Structure in the ACPI Specification.
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*/
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UINT32 VirtualTimerFlags;
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/** The common timer flags as described by the GT Block
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Timer frame Structure in the ACPI Specification.
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*/
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UINT32 CommonFlags;
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} CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
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/** A structure that describes the
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Platform Generic Block Timer information for the Platform.
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*/
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typedef struct CmArmGTBlockInfo {
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/// The physical base address for the GT Block Timer structure
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UINT64 GTBlockPhysicalAddress;
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/// The number of timer frames implemented in the GT Block
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UINT32 GTBlockTimerFrameCount;
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/// Reference token for the GT Block timer frame list
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CM_OBJECT_TOKEN GTBlockTimerFrameToken;
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} CM_ARM_GTBLOCK_INFO;
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/** A structure that describes the
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SBSA Generic Watchdog information for the Platform.
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*/
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typedef struct CmArmGenericWatchdogInfo {
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/// The physical base address of the SBSA Watchdog control frame
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UINT64 ControlFrameAddress;
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/// The physical base address of the SBSA Watchdog refresh frame
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UINT64 RefreshFrameAddress;
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/// The watchdog interrupt
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UINT32 TimerGSIV;
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/** The flags for the watchdog as described by the SBSA watchdog
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structure in the ACPI specification.
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*/
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UINT32 Flags;
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} CM_ARM_GENERIC_WATCHDOG_INFO;
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/** A structure that describes the
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PCI Configuration Space information for the Platform.
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*/
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typedef struct CmArmPciConfigSpaceInfo {
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/// The physical base address for the PCI segment
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UINT64 BaseAddress;
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/// The PCI segment group number
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UINT16 PciSegmentGroupNumber;
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/// The start bus number
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UINT8 StartBusNumber;
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/// The end bus number
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UINT8 EndBusNumber;
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} CM_ARM_PCI_CONFIG_SPACE_INFO;
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/** A structure that describes the
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Hypervisor Vendor ID information for the Platform.
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*/
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typedef struct CmArmHypervisorVendorId {
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/// The hypervisor Vendor ID
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UINT64 HypervisorVendorId;
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} CM_ARM_HYPERVISOR_VENDOR_ID;
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/** A structure that describes the
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Fixed feature flags for the Platform.
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*/
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typedef struct CmArmFixedFeatureFlags {
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/// The Fixed feature flags
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UINT32 Flags;
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} CM_ARM_FIXED_FEATURE_FLAGS;
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/** A structure that describes the
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ITS Group node for the Platform.
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*/
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typedef struct CmArmItsGroupNode {
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/// An unique token used to ideintify this object
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CM_OBJECT_TOKEN Token;
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/// The number of ITS identifiers in the ITS node
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UINT32 ItsIdCount;
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/// Reference token for the ITS identifier array
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CM_OBJECT_TOKEN ItsIdToken;
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} CM_ARM_ITS_GROUP_NODE;
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/** A structure that describes the
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GIC ITS Identifiers for an ITS Group node.
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*/
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typedef struct CmArmGicItsIdentifier {
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/// The ITS Identifier
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UINT32 ItsId;
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} CM_ARM_ITS_IDENTIFIER;
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/** A structure that describes the
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Named component node for the Platform.
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*/
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typedef struct CmArmNamedComponentNode {
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/// An unique token used to ideintify this object
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// Flags for the named component
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UINT32 Flags;
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/// Memory access properties : Cache coherent attributes
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UINT32 CacheCoherent;
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/// Memory access properties : Allocation hints
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UINT8 AllocationHints;
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/// Memory access properties : Memory access flags
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UINT8 MemoryAccessFlags;
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/// Memory access properties : Address size limit
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UINT8 AddressSizeLimit;
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/** ASCII Null terminated string with the full path to
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the entry in the namespace for this object.
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*/
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CHAR8* ObjectName;
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} CM_ARM_NAMED_COMPONENT_NODE;
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/** A structure that describes the
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Root complex node for the Platform.
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*/
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typedef struct CmArmRootComplexNode {
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/// An unique token used to ideintify this object
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// Memory access properties : Cache coherent attributes
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UINT32 CacheCoherent;
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/// Memory access properties : Allocation hints
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UINT8 AllocationHints;
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/// Memory access properties : Memory access flags
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UINT8 MemoryAccessFlags;
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/// ATS attributes
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UINT32 AtsAttribute;
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/// PCI segment number
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UINT32 PciSegmentNumber;
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/// Memory address size limit
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UINT8 MemoryAddressSize;
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} CM_ARM_ROOT_COMPLEX_NODE;
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/** A structure that describes the
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SMMUv1 or SMMUv2 node for the Platform.
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*/
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typedef struct CmArmSmmuV1SmmuV2Node {
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/// An unique token used to ideintify this object
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// SMMU Base Address
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UINT64 BaseAddress;
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/// Length of the memory range covered by the SMMU
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UINT64 Span;
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/// SMMU Model
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UINT32 Model;
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/// SMMU flags
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UINT32 Flags;
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/// Number of context interrupts
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UINT32 ContextInterruptCount;
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/// Reference token for the context interrupt array
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CM_OBJECT_TOKEN ContextInterruptToken;
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/// Number of PMU interrupts
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UINT32 PmuInterruptCount;
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/// Reference token for the PMU interrupt array
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CM_OBJECT_TOKEN PmuInterruptToken;
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/// GSIV of the SMMU_NSgIrpt interrupt
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UINT32 SMMU_NSgIrpt;
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/// SMMU_NSgIrpt interrupt flags
|
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UINT32 SMMU_NSgIrptFlags;
|
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/// GSIV of the SMMU_NSgCfgIrpt interrupt
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UINT32 SMMU_NSgCfgIrpt;
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/// SMMU_NSgCfgIrpt interrupt flags
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UINT32 SMMU_NSgCfgIrptFlags;
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} CM_ARM_SMMUV1_SMMUV2_NODE;
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/** A structure that describes the
|
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SMMUv3 node for the Platform.
|
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*/
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typedef struct CmArmSmmuV3Node {
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/// An unique token used to ideintify this object
|
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CM_OBJECT_TOKEN Token;
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/// Number of ID mappings
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UINT32 IdMappingCount;
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/// Reference token for the ID mapping array
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CM_OBJECT_TOKEN IdMappingToken;
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/// SMMU Base Address
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UINT64 BaseAddress;
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/// SMMU flags
|
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UINT32 Flags;
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/// VATOS address
|
||||
UINT64 VatosAddress;
|
||||
/// Model
|
||||
UINT32 Model;
|
||||
/// GSIV of the Event interrupt if SPI based
|
||||
UINT32 EventInterrupt;
|
||||
/// PRI Interrupt if SPI based
|
||||
UINT32 PriInterrupt;
|
||||
/// GERR interrupt if GSIV based
|
||||
UINT32 GerrInterrupt;
|
||||
/// Sync interrupt if GSIV based
|
||||
UINT32 SyncInterrupt;
|
||||
|
||||
/// Proximity domain flag
|
||||
UINT32 ProximityDomain;
|
||||
/// Index into the array of ID mapping
|
||||
UINT32 DeviceIdMappingIndex;
|
||||
} CM_ARM_SMMUV3_NODE;
|
||||
|
||||
/** A structure that describes the
|
||||
PMCG node for the Platform.
|
||||
*/
|
||||
typedef struct CmArmPmcgNode {
|
||||
/// An unique token used to ideintify this object
|
||||
CM_OBJECT_TOKEN Token;
|
||||
/// Number of ID mappings
|
||||
UINT32 IdMappingCount;
|
||||
/// Reference token for the ID mapping array
|
||||
CM_OBJECT_TOKEN IdMappingToken;
|
||||
|
||||
/// Base Address for performance monitor counter group
|
||||
UINT64 BaseAddress;
|
||||
/// GSIV for the Overflow interrupt
|
||||
UINT32 OverflowInterrupt;
|
||||
/// Page 1 Base address
|
||||
UINT64 Page1BaseAddress;
|
||||
|
||||
/// Reference token for the IORT node associated with this node
|
||||
CM_OBJECT_TOKEN ReferenceToken;
|
||||
} CM_ARM_PMCG_NODE;
|
||||
|
||||
/** A structure that describes the
|
||||
ID Mappings for the Platform.
|
||||
*/
|
||||
typedef struct CmArmIdMapping {
|
||||
/// Input base
|
||||
UINT32 InputBase;
|
||||
/// Number of input IDs
|
||||
UINT32 NumIds;
|
||||
/// Output Base
|
||||
UINT32 OutputBase;
|
||||
/// Reference token for the output node
|
||||
CM_OBJECT_TOKEN OutputReferenceToken;
|
||||
/// Flags
|
||||
UINT32 Flags;
|
||||
} CM_ARM_ID_MAPPING;
|
||||
|
||||
/** A structure that describes the
|
||||
SMMU interrupts for the Platform.
|
||||
*/
|
||||
typedef struct CmArmSmmuInterrupt {
|
||||
/// Interrupt number
|
||||
UINT32 Interrupt;
|
||||
|
||||
/// Flags
|
||||
UINT32 Flags;
|
||||
} CM_ARM_SMMU_INTERRUPT;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif // ARM_NAMESPACE_OBJECTS_H_
|
||||
Loading…
Reference in New Issue