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OvmfPkg/QemuFwCfgLibMmio: Add RISC-V arch support 

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Abner Chang 2021-10-11 21:35:06 +08:00 committed by mergify[bot]
parent f8d0501ded
commit 26aa241d2f
2 changed files with 5 additions and 4 deletions
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7
OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.c
View File

@ -4,6 +4,7 @@
Copyright (C) 2013 - 2014, Red Hat, Inc.
Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -239,7 +240,7 @@ MmioReadBytes (
UINT8 *Ptr;
UINT8 *End;
#ifdef MDE_CPU_AARCH64
#if defined(MDE_CPU_AARCH64) || defined(MDE_CPU_RISCV64)
Left = Size & 7;
#else
Left = Size & 3;
@ -249,7 +250,7 @@ MmioReadBytes (
Ptr = Buffer;
End = Ptr + Size;
#ifdef MDE_CPU_AARCH64
#if defined(MDE_CPU_AARCH64) || defined(MDE_CPU_RISCV64)
while (Ptr < End) {
*(UINT64 *)Ptr = MmioRead64 (mFwCfgDataAddress);
Ptr += 8;
@ -322,7 +323,7 @@ DmaTransferBytes (
//
// This will fire off the transfer.
//
#ifdef MDE_CPU_AARCH64
#if defined(MDE_CPU_AARCH64) || defined(MDE_CPU_RISCV64)
MmioWrite64 (mFwCfgDmaAddress, SwapBytes64 ((UINT64)&Access));
#else
MmioWrite32 ((UINT32)(mFwCfgDmaAddress + 4), SwapBytes32 ((UINT32)&Access));

2
OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf
View File

@ -23,7 +23,7 @@
# The following information is for reference only and not required by the build
# tools.
#
# VALID_ARCHITECTURES = ARM AARCH64
# VALID_ARCHITECTURES = ARM AARCH64 RISCV64
#
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