From 26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0 Mon Sep 17 00:00:00 2001
From: Michael Kinney <michael.d.kinney@intel.com>
Date: Thu, 17 Nov 2016 20:50:27 -0800
Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure

https://bugzilla.tianocore.org/show_bug.cgi?id=277

All CPUs use the same MTRR settings.  Move MTRR settings
from a field in the PROCESSOR_SMM_DESCRIPTOR structure into
a module global variable.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c      | 18 ++++--------------
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  2 +-
 2 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index a873b68c30..01ddaee4e7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //
 // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
 //
-UINT64                                      gSmiMtrrs[MTRR_NUMBER_OF_FIXED_MTRR + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
+MTRR_SETTINGS                               gSmiMtrrs;
 UINT64                                      gPhyMask;
 SMM_DISPATCHER_MP_SYNC_DATA                 *mSmmMpSyncData = NULL;
 UINTN                                       mSmmMpSyncDataSize;
@@ -283,20 +283,12 @@ ReplaceOSMtrrs (
   IN      UINTN                     CpuIndex
   )
 {
-  PROCESSOR_SMM_DESCRIPTOR       *Psd;
-  UINT64                         *SmiMtrrs;
-  MTRR_SETTINGS                  *BiosMtrr;
-
-  Psd = (PROCESSOR_SMM_DESCRIPTOR*)(mCpuHotPlugData.SmBase[CpuIndex] + SMM_PSD_OFFSET);
-  SmiMtrrs = (UINT64*)(UINTN)Psd->MtrrBaseMaskPtr;
-
   SmmCpuFeaturesDisableSmrr ();
 
   //
   // Replace all MTRRs registers
   //
-  BiosMtrr  = (MTRR_SETTINGS*)SmiMtrrs;
-  MtrrSetAllMtrrs(BiosMtrr);
+  MtrrSetAllMtrrs (&gSmiMtrrs);
 }
 
 /**
@@ -1379,7 +1371,6 @@ InitializeMpServiceData (
 {
   UINT32                    Cr3;
   UINTN                     Index;
-  MTRR_SETTINGS             *Mtrr;
   PROCESSOR_SMM_DESCRIPTOR  *Psd;
   UINT8                     *GdtTssTables;
   UINTN                     GdtTableStepSize;
@@ -1442,9 +1433,8 @@ InitializeMpServiceData (
   //
   // Record current MTRR settings
   //
-  ZeroMem(gSmiMtrrs, sizeof (gSmiMtrrs));
-  Mtrr =  (MTRR_SETTINGS*)gSmiMtrrs;
-  MtrrGetAllMtrrs (Mtrr);
+  ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs));
+  MtrrGetAllMtrrs (&gSmiMtrrs);
 
   return Cr3;
 }
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index abe5cc612b..bd6abf28b5 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -380,7 +380,7 @@ typedef struct {
   UINT16                            Reserved11;             // Offset 0x50
   UINT16                            Reserved12;             // Offset 0x52
   UINT32                            Reserved13;             // Offset 0x54
-  UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
+  UINT64                            Reserved14;             // Offset 0x58
 } PROCESSOR_SMM_DESCRIPTOR;