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MdePkg: Move RISC-V Cache Management Declarations Into BaseLib

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The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Pedro Falcato <pedro.falcato@gmail.com>

Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Dhaval Sharma 2023-12-13 20:29:27 +05:30 committed by mergify[bot]
parent 3c66390e4a
commit 286b30f517
2 changed files with 20 additions and 20 deletions
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20
MdePkg/Include/Library/BaseLib.h
View File

@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
VOID VOID
); );
/**
RISC-V invalidate instruction cache.
**/
VOID
EFIAPI
RiscVInvalidateInstCacheAsm (
VOID
);
/**
RISC-V invalidate data cache.
**/
VOID
EFIAPI
RiscVInvalidateDataCacheAsm (
VOID
);
#endif // defined (MDE_CPU_RISCV64) #endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64) #if defined (MDE_CPU_LOONGARCH64)

20
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
View File

@ -10,26 +10,6 @@
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
/**
RISC-V invalidate instruction cache.
**/
VOID
EFIAPI
RiscVInvalidateInstCacheAsm (
VOID
);
/**
RISC-V invalidate data cache.
**/
VOID
EFIAPI
RiscVInvalidateDataCacheAsm (
VOID
);
/** /**
Invalidates the entire instruction cache in cache coherency domain of the Invalidates the entire instruction cache in cache coherency domain of the
calling CPU. calling CPU.