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Add ASSERT check for AsmFlushCacheRange(). 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8465 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
xli24 2009-06-04 14:29:12 +00:00
parent 63fffe4e72
commit 287f4f47b4
5 changed files with 103 additions and 27 deletions
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8
MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
View File

@ -1,7 +1,7 @@
/** @file
Cache Maintenance Functions.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Copyright (c) 2006 - 2009, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -64,7 +64,6 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return AsmFlushCacheRange (Address, Length);
}
@ -120,8 +119,6 @@ WriteBackInvalidateDataCacheRange (
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return AsmFlushCacheRange (Address, Length);
}
@ -176,8 +173,6 @@ WriteBackDataCacheRange (
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return AsmFlushCacheRange (Address, Length);
}
@ -239,7 +234,6 @@ InvalidateDataCacheRange (
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
//
// Invalidation of a data cache range without writing back is not supported on
// IPF architecture, so write back and invalidate operation is performed.

5
MdePkg/Library/BaseLib/BaseLib.inf
View File

@ -1,7 +1,7 @@
#/** @file
# Base Library implementation.
#
# Copyright (c) 2007 - 2008, Intel Corporation.
# Copyright (c) 2007 - 2009, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -558,7 +558,8 @@
Ipf/AccessMsr.s | INTEL
Ipf/AccessMsr.s | GCC
Ipf/AccessMsrDb.s | MSFT
Ipf/FlushCacheRange.s
Ipf/InternalFlushCacheRange.s
Ipf/FlushCacheRange.c
Ipf/InternalSwitchStack.c
Ipf/GetInterruptState.s
Ipf/CpuPause.s

34
MdePkg/Library/BaseLib/BaseLibInternals.h
View File

@ -1,7 +1,7 @@
/** @file
Declaration of internal functions in BaseLib.
Copyright (c) 2006 - 2008, Intel Corporation<BR>
Copyright (c) 2006 - 2009, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -1616,6 +1616,38 @@ AsmSwitchStackAndBackingStore (
IN VOID *NewStack,
IN VOID *NewBsp
);
/**
Internal worker function to invalidate a range of instruction cache lines
in the cache coherency domain of the calling CPU.
Internal worker function to invalidate the instruction cache lines specified
by Address and Length. If Address is not aligned on a cache line boundary,
then entire instruction cache line containing Address is invalidated. If
Address + Length is not aligned on a cache line boundary, then the entire
instruction cache line containing Address + Length -1 is invalidated. This
function may choose to invalidate the entire instruction cache if that is more
efficient than invalidating the specified range. If Length is 0, the no instruction
cache lines are invalidated. Address is returned.
This function is only available on IPF.
@param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address
**/
VOID *
EFIAPI
InternalFlushCacheRange (
IN VOID *Address,
IN UINTN Length
);
#else
#endif

51
MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c Normal file
View File

@ -0,0 +1,51 @@
/** @file
AsmFlushCacheRange() function for IPF.
Copyright (c) 2009, Intel Corporation<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Flush a range of cache lines in the cache coherency domain of the calling
CPU.
Flushes the cache lines specified by Address and Length. If Address is not aligned
on a cache line boundary, then entire cache line containing Address is flushed.
If Address + Length is not aligned on a cache line boundary, then the entire cache
line containing Address + Length - 1 is flushed. This function may choose to flush
the entire cache if that is more efficient than flushing the specified range. If
Length is 0, the no cache lines are flushed. Address is returned.
This function is only available on IPF.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache.
@return Address.
**/
VOID *
EFIAPI
AsmFlushCacheRange (
IN VOID *Address,
IN UINTN Length
)
{
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
return InternalFlushCacheRange (Address, Length);
}

32
MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s → MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
View File

@ -1,5 +1,5 @@
//++
// Copyright (c) 2006 - 2008, Intel Corporation
// Copyright (c) 2006 - 2009, Intel Corporation
// All rights reserved. This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
@ -9,7 +9,7 @@
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Module Name:
// FlushCacheRange.s
// InternalFlushCacheRange.s
//
// Abstract:
// Assemble routine to flush cache lines
@ -22,21 +22,19 @@
#include <IpfMacro.i>
//
// Invalidates a range of instruction cache lines in the cache coherency domain
// of the calling CPU.
// Internal worker function to invalidate a range of instruction cache lines
// in the cache coherency domain of the calling CPU.
//
// Invalidates the instruction cache lines specified by Address and Length. If
// Address is not aligned on a cache line boundary, then entire instruction
// cache line containing Address is invalidated. If Address + Length is not
// aligned on a cache line boundary, then the entire instruction cache line
// containing Address + Length -1 is invalidated. This function may choose to
// invalidate the entire instruction cache if that is more efficient than
// invalidating the specified range. If Length is 0, the no instruction cache
// lines are invalidated. Address is returned.
// Internal worker function to invalidate the instruction cache lines specified
// by Address and Length. If Address is not aligned on a cache line boundary,
// then entire instruction cache line containing Address is invalidated. If
// Address + Length is not aligned on a cache line boundary, then the entire
// instruction cache line containing Address + Length -1 is invalidated. This
// function may choose to invalidate the entire instruction cache if that is more
// efficient than invalidating the specified range. If Length is 0, the no instruction
// cache lines are invalidated. Address is returned.
// This function is only available on IPF.
//
// If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
//
// @param Address The base address of the instruction cache lines to
// invalidate. If the CPU is in a physical addressing mode, then
// Address is a physical address. If the CPU is in a virtual
@ -48,12 +46,12 @@
//
// VOID *
// EFIAPI
// AsmFlushCacheRange (
// InternalFlushCacheRange (
// IN VOID *Address,
// IN UINTN Length
// );
//
PROCEDURE_ENTRY (AsmFlushCacheRange)
PROCEDURE_ENTRY (InternalFlushCacheRange)
NESTED_SETUP (5,8,0,0)
@ -92,5 +90,5 @@ DoneFlushingC:
mov r8 = in0 // return *Address
NESTED_RETURN
PROCEDURE_EXIT (AsmFlushCacheRange)
PROCEDURE_EXIT (InternalFlushCacheRange)