mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiException.asm to NASM
Manually convert Ia32/SmiException.asm to Ia32/SmiException.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Liming Gao
parent
63a4f46076
commit
28ee581646
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiException.nasm
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;
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; Abstract:
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;
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; Exception handlers used in SM mode
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;
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;-------------------------------------------------------------------------------
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extern ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))
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extern ASM_PFX(gSmiMtrrs)
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extern ASM_PFX(SmiPFHandler)
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global ASM_PFX(gcSmiIdtr)
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global ASM_PFX(gcSmiGdtr)
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global ASM_PFX(gcPsd)
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SECTION .data
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NullSeg: DQ 0 ; reserved by architecture
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CodeSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeCodeSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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ProtModeSsSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x93
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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DataSeg32:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x93
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DB 0xcf ; LimitHigh
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DB 0 ; BaseHigh
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CodeSeg16:
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DW -1
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DW 0
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DB 0
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DB 0x9b
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DB 0x8f
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DB 0
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DataSeg16:
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DW -1
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DW 0
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DB 0
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DB 0x93
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DB 0x8f
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DB 0
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CodeSeg64:
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DW -1 ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x9b
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DB 0xaf ; LimitHigh
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DB 0 ; BaseHigh
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GDT_SIZE equ $ - NullSeg
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TssSeg:
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DW TSS_DESC_SIZE ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x89
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DB 0x80 ; LimitHigh
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DB 0 ; BaseHigh
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ExceptionTssSeg:
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DW TSS_DESC_SIZE ; LimitLow
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DW 0 ; BaseLow
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DB 0 ; BaseMid
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DB 0x89
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DB 0x80 ; LimitHigh
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DB 0 ; BaseHigh
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CODE_SEL equ CodeSeg32 - NullSeg
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DATA_SEL equ DataSeg32 - NullSeg
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TSS_SEL equ TssSeg - NullSeg
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EXCEPTION_TSS_SEL equ ExceptionTssSeg - NullSeg
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struc IA32_TSS
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resw 1
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resw 1
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.ESP0: resd 1
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.SS0: resw 1
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resw 1
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.ESP1: resd 1
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.SS1: resw 1
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resw 1
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.ESP2: resd 1
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.SS2: resw 1
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resw 1
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._CR3: resd 1
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.EIP: resd 1
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.EFLAGS: resd 1
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._EAX: resd 1
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._ECX: resd 1
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._EDX: resd 1
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._EBX: resd 1
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._ESP: resd 1
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._EBP: resd 1
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._ESI: resd 1
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._EDI: resd 1
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._ES: resw 1
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resw 1
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._CS: resw 1
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resw 1
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._SS: resw 1
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resw 1
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._DS: resw 1
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resw 1
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._FS: resw 1
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resw 1
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._GS: resw 1
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resw 1
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.LDT: resw 1
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resw 1
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resw 1
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resw 1
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endstruc
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; Create 2 TSS segments just after GDT
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TssDescriptor:
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DW 0 ; PreviousTaskLink
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DW 0 ; Reserved
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DD 0 ; ESP0
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DW 0 ; SS0
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DW 0 ; Reserved
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DD 0 ; ESP1
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DW 0 ; SS1
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DW 0 ; Reserved
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DD 0 ; ESP2
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DW 0 ; SS2
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DW 0 ; Reserved
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DD 0 ; CR3
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DD 0 ; EIP
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DD 0 ; EFLAGS
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DD 0 ; EAX
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DD 0 ; ECX
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DD 0 ; EDX
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DD 0 ; EBX
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DD 0 ; ESP
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DD 0 ; EBP
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DD 0 ; ESI
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DD 0 ; EDI
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DW 0 ; ES
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DW 0 ; Reserved
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DW 0 ; CS
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DW 0 ; Reserved
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DW 0 ; SS
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DW 0 ; Reserved
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DW 0 ; DS
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DW 0 ; Reserved
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DW 0 ; FS
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DW 0 ; Reserved
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DW 0 ; GS
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DW 0 ; Reserved
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DW 0 ; LDT Selector
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DW 0 ; Reserved
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DW 0 ; T
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DW 0 ; I/O Map Base
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TSS_DESC_SIZE equ $ - TssDescriptor
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ExceptionTssDescriptor:
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DW 0 ; PreviousTaskLink
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DW 0 ; Reserved
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DD 0 ; ESP0
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DW 0 ; SS0
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DW 0 ; Reserved
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DD 0 ; ESP1
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DW 0 ; SS1
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DW 0 ; Reserved
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DD 0 ; ESP2
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DW 0 ; SS2
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DW 0 ; Reserved
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DD 0 ; CR3
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DD PFHandlerEntry ; EIP
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DD 00000002 ; EFLAGS
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DD 0 ; EAX
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DD 0 ; ECX
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DD 0 ; EDX
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DD 0 ; EBX
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DD 0 ; ESP
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DD 0 ; EBP
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DD 0 ; ESI
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DD 0 ; EDI
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DW DATA_SEL ; ES
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DW 0 ; Reserved
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DW CODE_SEL ; CS
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DW 0 ; Reserved
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DW DATA_SEL ; SS
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DW 0 ; Reserved
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DW DATA_SEL ; DS
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DW 0 ; Reserved
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DW DATA_SEL ; FS
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DW 0 ; Reserved
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DW DATA_SEL ; GS
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DW 0 ; Reserved
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DW 0 ; LDT Selector
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DW 0 ; Reserved
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DW 0 ; T
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DW 0 ; I/O Map Base
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ASM_PFX(gcPsd):
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DB 'PSDSIG '
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DW PSD_SIZE
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DW 2
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DW 1 << 2
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DW CODE_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW 0
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DQ 0
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DQ 0
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DQ 0
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DD 0
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DD NullSeg
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DD GDT_SIZE
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DD 0
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times 24 DB 0
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DD 0
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DD ASM_PFX(gSmiMtrrs)
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PSD_SIZE equ $ - ASM_PFX(gcPsd)
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ASM_PFX(gcSmiGdtr):
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DW GDT_SIZE - 1
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DD NullSeg
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ASM_PFX(gcSmiIdtr):
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DW IDT_SIZE - 1
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DD _SmiIDT
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_SmiIDT:
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%rep 32
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DW 0 ; Offset 0:15
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DW CODE_SEL ; Segment selector
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DB 0 ; Unused
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DB 0x8e ; Interrupt Gate, Present
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DW 0 ; Offset 16:31
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%endrep
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IDT_SIZE equ $ - _SmiIDT
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TaskGateDescriptor:
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DW 0 ; Reserved
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DW EXCEPTION_TSS_SEL ; TSS Segment selector
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DB 0 ; Reserved
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DB 0x85 ; Task Gate, present, DPL = 0
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DW 0 ; Reserved
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SECTION .text
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;------------------------------------------------------------------------------
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; PageFaultIdtHandlerSmmProfile is the entry point page fault only
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;
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;
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; Stack:
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; +---------------------+
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; + EFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + EIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + EBP +
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; +---------------------+ <-- EBP
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;
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;
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;------------------------------------------------------------------------------
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global ASM_PFX(PageFaultIdtHandlerSmmProfile)
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ASM_PFX(PageFaultIdtHandlerSmmProfile):
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push 0xe ; Page Fault
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push ebp
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mov ebp, esp
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;
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; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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; is 16-byte aligned
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;
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and esp, 0xfffffff0
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sub esp, 12
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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push eax
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push ecx
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push edx
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push ebx
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lea ecx, [ebp + 6 * 4]
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push ecx ; ESP
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push dword [ebp] ; EBP
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push esi
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push edi
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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mov eax, ss
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push eax
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movzx eax, word [ebp + 4 * 4]
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push eax
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mov eax, ds
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push eax
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mov eax, es
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push eax
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mov eax, fs
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push eax
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mov eax, gs
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push eax
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;; UINT32 Eip;
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mov eax, [ebp + 3 * 4]
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push eax
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;; UINT32 Gdtr[2], Idtr[2];
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sub esp, 8
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sidt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
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mov [esp+4], eax
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sub esp, 8
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sgdt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
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mov [esp+4], eax
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;; UINT32 Ldtr, Tr;
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xor eax, eax
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str ax
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push eax
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sldt ax
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push eax
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;; UINT32 EFlags;
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mov eax, [ebp + 5 * 4]
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push eax
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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mov eax, cr4
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or eax, 0x208
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mov cr4, eax
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push eax
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mov eax, cr3
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push eax
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mov eax, cr2
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push eax
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xor eax, eax
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push eax
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mov eax, cr0
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push eax
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov eax, dr7
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push eax
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mov eax, dr6
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push eax
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mov eax, dr3
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push eax
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mov eax, dr2
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push eax
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mov eax, dr1
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push eax
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mov eax, dr0
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push eax
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;; FX_SAVE_STATE_IA32 FxSaveState;
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sub esp, 512
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mov edi, esp
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db 0xf, 0xae, 0x7 ;fxsave [edi]
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; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT32 ExceptionData;
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push dword [ebp + 2 * 4]
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;; call into exception handler
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;; Prepare parameter and call
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mov edx, esp
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push edx
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mov edx, dword [ebp + 1 * 4]
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push edx
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;
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; Call External Exception Handler
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;
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mov eax, ASM_PFX(SmiPFHandler)
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call eax
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add esp, 8
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;; UINT32 ExceptionData;
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add esp, 4
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;; FX_SAVE_STATE_IA32 FxSaveState;
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mov esi, esp
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db 0xf, 0xae, 0xe ; fxrstor [esi]
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add esp, 512
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support debuggers
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;; that set breakpoint in interrupt/exception context
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add esp, 4 * 6
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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pop eax
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mov cr0, eax
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add esp, 4 ; not for Cr1
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pop eax
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mov cr2, eax
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pop eax
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mov cr3, eax
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pop eax
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mov cr4, eax
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;; UINT32 EFlags;
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pop dword [ebp + 5 * 4]
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;; UINT32 Ldtr, Tr;
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;; UINT32 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add esp, 24
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;; UINT32 Eip;
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pop dword [ebp + 3 * 4]
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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;; NOTE - modified segment registers could hang the debugger... We
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;; could attempt to insulate ourselves against this possibility,
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;; but that poses risks as well.
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;;
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pop gs
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pop fs
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pop es
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pop ds
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pop dword [ebp + 4 * 4]
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pop ss
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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pop edi
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pop esi
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add esp, 4 ; not for ebp
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add esp, 4 ; not for esp
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pop ebx
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pop edx
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pop ecx
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pop eax
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mov esp, ebp
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pop ebp
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; Enable TF bit after page fault handler runs
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bts dword [esp + 16], 8 ; EFLAGS
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add esp, 8 ; skip INT# & ErrCode
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Return:
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iretd
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;
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; Page Fault Exception Handler entry when SMM Stack Guard is enabled
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; Executiot starts here after a task switch
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;
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PFHandlerEntry:
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;
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; Get this processor's TSS
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;
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sub esp, 8
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sgdt [esp + 2]
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mov eax, [esp + 4] ; GDT base
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add esp, 8
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mov ecx, [eax + TSS_SEL + 2]
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shl ecx, 8
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mov cl, [eax + TSS_SEL + 7]
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ror ecx, 8 ; ecx = TSS base
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mov ebp, esp
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;
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; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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; is 16-byte aligned
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;
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and esp, 0xfffffff0
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sub esp, 12
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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push dword [ecx + IA32_TSS._EAX]
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push dword [ecx + IA32_TSS._ECX]
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push dword [ecx + IA32_TSS._EDX]
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push dword [ecx + IA32_TSS._EBX]
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push dword [ecx + IA32_TSS._ESP]
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push dword [ecx + IA32_TSS._EBP]
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push dword [ecx + IA32_TSS._ESI]
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push dword [ecx + IA32_TSS._EDI]
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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movzx eax, word [ecx + IA32_TSS._SS]
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push eax
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movzx eax, word [ecx + IA32_TSS._CS]
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push eax
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movzx eax, word [ecx + IA32_TSS._DS]
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push eax
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movzx eax, word [ecx + IA32_TSS._ES]
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push eax
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movzx eax, word [ecx + IA32_TSS._FS]
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push eax
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movzx eax, word [ecx + IA32_TSS._GS]
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push eax
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;; UINT32 Eip;
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push dword [ecx + IA32_TSS.EIP]
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;; UINT32 Gdtr[2], Idtr[2];
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sub esp, 8
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sidt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
|
||||
mov [esp+4], eax
|
||||
|
||||
sub esp, 8
|
||||
sgdt [esp]
|
||||
mov eax, [esp + 2]
|
||||
xchg eax, [esp]
|
||||
and eax, 0xFFFF
|
||||
mov [esp+4], eax
|
||||
|
||||
;; UINT32 Ldtr, Tr;
|
||||
mov eax, TSS_SEL
|
||||
push eax
|
||||
movzx eax, word [ecx + IA32_TSS.LDT]
|
||||
push eax
|
||||
|
||||
;; UINT32 EFlags;
|
||||
push dword [ecx + IA32_TSS.EFLAGS]
|
||||
|
||||
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
mov eax, cr4
|
||||
or eax, 0x208
|
||||
mov cr4, eax
|
||||
push eax
|
||||
mov eax, cr3
|
||||
push eax
|
||||
mov eax, cr2
|
||||
push eax
|
||||
xor eax, eax
|
||||
push eax
|
||||
mov eax, cr0
|
||||
push eax
|
||||
|
||||
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
mov eax, dr7
|
||||
push eax
|
||||
mov eax, dr6
|
||||
push eax
|
||||
mov eax, dr3
|
||||
push eax
|
||||
mov eax, dr2
|
||||
push eax
|
||||
mov eax, dr1
|
||||
push eax
|
||||
mov eax, dr0
|
||||
push eax
|
||||
|
||||
;; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
|
||||
;; when executing fxsave/fxrstor instruction
|
||||
clts
|
||||
sub esp, 512
|
||||
mov edi, esp
|
||||
db 0xf, 0xae, 0x7 ;fxsave [edi]
|
||||
|
||||
; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
|
||||
cld
|
||||
|
||||
;; UINT32 ExceptionData;
|
||||
push dword [ebp]
|
||||
|
||||
;; call into exception handler
|
||||
mov ebx, ecx
|
||||
mov eax, ASM_PFX(SmiPFHandler)
|
||||
|
||||
;; Prepare parameter and call
|
||||
mov edx, esp
|
||||
push edx
|
||||
mov edx, 14
|
||||
push edx
|
||||
|
||||
;
|
||||
; Call External Exception Handler
|
||||
;
|
||||
call eax
|
||||
add esp, 8
|
||||
|
||||
mov ecx, ebx
|
||||
;; UINT32 ExceptionData;
|
||||
add esp, 4
|
||||
|
||||
;; FX_SAVE_STATE_IA32 FxSaveState;
|
||||
mov esi, esp
|
||||
db 0xf, 0xae, 0xe ; fxrstor [esi]
|
||||
add esp, 512
|
||||
|
||||
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
|
||||
;; Skip restoration of DRx registers to support debuggers
|
||||
;; that set breakpoints in interrupt/exception context
|
||||
add esp, 4 * 6
|
||||
|
||||
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
|
||||
pop eax
|
||||
mov cr0, eax
|
||||
add esp, 4 ; not for Cr1
|
||||
pop eax
|
||||
mov cr2, eax
|
||||
pop eax
|
||||
mov dword [ecx + IA32_TSS._CR3], eax
|
||||
pop eax
|
||||
mov cr4, eax
|
||||
|
||||
;; UINT32 EFlags;
|
||||
pop dword [ecx + IA32_TSS.EFLAGS]
|
||||
|
||||
;; UINT32 Ldtr, Tr;
|
||||
;; UINT32 Gdtr[2], Idtr[2];
|
||||
;; Best not let anyone mess with these particular registers...
|
||||
add esp, 24
|
||||
|
||||
;; UINT32 Eip;
|
||||
pop dword [ecx + IA32_TSS.EIP]
|
||||
|
||||
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
|
||||
;; NOTE - modified segment registers could hang the debugger... We
|
||||
;; could attempt to insulate ourselves against this possibility,
|
||||
;; but that poses risks as well.
|
||||
;;
|
||||
pop eax
|
||||
o16 mov [ecx + IA32_TSS._GS], ax
|
||||
pop eax
|
||||
o16 mov [ecx + IA32_TSS._FS], ax
|
||||
pop eax
|
||||
o16 mov [ecx + IA32_TSS._ES], ax
|
||||
pop eax
|
||||
o16 mov [ecx + IA32_TSS._DS], ax
|
||||
pop eax
|
||||
o16 mov [ecx + IA32_TSS._CS], ax
|
||||
pop eax
|
||||
o16 mov [ecx + IA32_TSS._SS], ax
|
||||
|
||||
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
|
||||
pop dword [ecx + IA32_TSS._EDI]
|
||||
pop dword [ecx + IA32_TSS._ESI]
|
||||
add esp, 4 ; not for ebp
|
||||
add esp, 4 ; not for esp
|
||||
pop dword [ecx + IA32_TSS._EBX]
|
||||
pop dword [ecx + IA32_TSS._EDX]
|
||||
pop dword [ecx + IA32_TSS._ECX]
|
||||
pop dword [ecx + IA32_TSS._EAX]
|
||||
|
||||
mov esp, ebp
|
||||
|
||||
; Set single step DB# if SMM profile is enabled and page fault exception happens
|
||||
cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable))], 0
|
||||
jz @Done2
|
||||
|
||||
; Create return context for iretd in stub function
|
||||
mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
|
||||
mov ebx, dword [ecx + IA32_TSS.EIP]
|
||||
mov [eax - 0xc], ebx ; create EIP in old stack
|
||||
movzx ebx, word [ecx + IA32_TSS._CS]
|
||||
mov [eax - 0x8], ebx ; create CS in old stack
|
||||
mov ebx, dword [ecx + IA32_TSS.EFLAGS]
|
||||
bts ebx, 8
|
||||
mov [eax - 0x4], ebx ; create eflags in old stack
|
||||
mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
|
||||
sub eax, 0xc ; minus 12 byte
|
||||
mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
|
||||
; Replace the EIP of interrupted task with stub function
|
||||
mov eax, ASM_PFX(PageFaultStubFunction)
|
||||
mov dword [ecx + IA32_TSS.EIP], eax
|
||||
; Jump to the iretd so next page fault handler as a task will start again after iretd.
|
||||
@Done2:
|
||||
add esp, 4 ; skip ErrCode
|
||||
|
||||
jmp Return
|
||||
|
||||
global ASM_PFX(PageFaultStubFunction)
|
||||
ASM_PFX(PageFaultStubFunction):
|
||||
;
|
||||
; we need clean TS bit in CR0 to execute
|
||||
; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
|
||||
;
|
||||
clts
|
||||
iretd
|
||||
|
||||
global ASM_PFX(InitializeIDTSmmStackGuard)
|
||||
ASM_PFX(InitializeIDTSmmStackGuard):
|
||||
push ebx
|
||||
;
|
||||
; If SMM Stack Guard feature is enabled, the Page Fault Exception entry in IDT
|
||||
; is a Task Gate Descriptor so that when a Page Fault Exception occurrs,
|
||||
; the processors can use a known good stack in case stack is ran out.
|
||||
;
|
||||
lea ebx, [_SmiIDT + 14 * 8]
|
||||
lea edx, [TaskGateDescriptor]
|
||||
mov eax, [edx]
|
||||
mov [ebx], eax
|
||||
mov eax, [edx + 4]
|
||||
mov [ebx + 4], eax
|
||||
pop ebx
|
||||
ret
|
||||
|
||||
END
|
||||
Loading…
Reference in New Issue