mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmVExpress-CTA15-A7: Added support for CoreTile Express A15x2_A7x3
This is the big.LITTLE test chip for ARM Versatile Express Motherboard. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13775 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
17839a45b8
commit
295c2eb804
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#
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# Copyright (c) 2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#
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################################################################################
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#
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# Defines Section - statements that will be processed to create a Makefile.
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#
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################################################################################
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[Defines]
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PLATFORM_NAME = ArmVExpressPkg-CTA15-A7
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PLATFORM_GUID = 0b511920-978d-4b34-acc0-3d9f8e6f9d81
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PLATFORM_VERSION = 0.1
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DSC_SPECIFICATION = 0x00010005
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OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15-A7
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SUPPORTED_ARCHITECTURES = ARM
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BUILD_TARGETS = DEBUG|RELEASE
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SKUID_IDENTIFIER = DEFAULT
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FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf
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DEFINE EDK2_SKIP_PEICORE=1
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!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
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[LibraryClasses.common]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
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ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
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ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
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NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
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#DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf
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# ARM PL390 General Interrupt Driver in Secure and Non-secure
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ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
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LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf
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TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
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ArmSmcLib|ArmPlatformPkg/Library/ArmSmcLib/ArmSmcLib.inf
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[BuildOptions]
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!ifdef $(ARM_BIGLITTLE_TC2)
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RVCT:*_*_ARM_ARCHCC_FLAGS = -DARM_BIGLITTLE_TC2=1
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RVCT:*_*_ARM_PP_FLAGS = -DARM_BIGLITTLE_TC2=1
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GCC:*_*_ARM_ARCHCC_FLAGS = -DARM_BIGLITTLE_TC2=1
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GCC:*_*_ARM_PP_FLAGS = -DARM_BIGLITTLE_TC2=1
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!endif
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RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7
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GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7
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XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7
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################################################################################
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#
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# Pcd Section - list of all EDK II PCD Entries defined by this Platform
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#
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################################################################################
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[PcdsFeatureFlag.common]
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
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gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
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## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
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# It could be set FALSE to save size.
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gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
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[PcdsFixedAtBuild.common]
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gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
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gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-CTA15-A7"
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gArmPlatformTokenSpaceGuid.PcdCoreCount|5
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#
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# NV Storage PCDs. Use base of 0x0C000000 for NOR1
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#
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
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gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
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gArmTokenSpaceGuid.PcdVFPEnabled|1
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# Stacks for MPCores in Secure World
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# SRAM (CS1) is only available between 0x14000000 and 0x14001000 on the model
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# ZBT SRAM is available between 0x2E000000 and 0x2E010000 on the model
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!ifdef $(ARM_BIGLITTLE_TC2)
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x17000000
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!else
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E000000
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!endif
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x8000
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000
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# Share Monitor stacks with Secure World
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0
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# System Memory (1GB) - An additional 1GB will be added if UEFI is running on a 2GB Test Chip
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gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
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gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
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!ifdef $(ARM_BIGLITTLE_TC2)
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# TC2 Dual-Cluster profile
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gArmPlatformTokenSpaceGuid.PcdClusterCount|2
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# Core Ids and Gic values
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# A15_0 = 0x000, GicCoreId = 0
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# A15_1 = 0x001, GicCoreId = 1
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# A7_0 = 0x100, GicCoreId = 2
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# A7_1 = 0x101, GicCoreId = 3
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# A7_2 = 0x102, GicCoreId = 4
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gArmTokenSpaceGuid.PcdArmPrimaryCore|0x100
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gArmTokenSpaceGuid.PcdGicPrimaryCoreId|2
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!endif
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#
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# SEC Phase Global Variables :
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# - 0x00-0x04: Debugger Exception Handler Pointer address
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# - 0x04-0x08: Normal Exception Handler Pointer
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# - 0x0C-0x10: MpSafe Serial Console SpinLock
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# - 0x10-0x20: KfScb 8 Bakery Locks of 2Bytes each
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# - 0x20-0x30: CCI 8 Bakery Locks of 2Bytes each
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# - 0x30-0x48: ARM SMC Events (8 cores * 3 max_event * sizeof(UINT8))
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gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x48
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#
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# ARM PrimeCell
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#
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## SP805 Watchdog - Motherboard Watchdog
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gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000
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## PL011 - Serial Terminal
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
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## PL031 RealTimeClock
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gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
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!ifdef $(ARM_BIGLITTLE_TC2)
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## PL111 Lcd & HdLcd
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gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000
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gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000
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gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5
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!endif
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#
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# PL180 MMC/SD card controller
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#
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gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
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gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
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#
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# ARM PL390 General Interrupt Controller
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000
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#
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# ARM OS Loader
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#
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# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
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gArmTokenSpaceGuid.PcdArmMachineType|2272
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0xE000000,0xE800000)"
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gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400 earlyprintk debug verbose"
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gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
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gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x0E800000,0x0E803000)"
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# Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
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# PL111 - CLCD
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#gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
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# HDLCD
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gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
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gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
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#
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# ARM Architectural Timer Frequency
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#
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!ifdef $(ARM_BIGLITTLE_TC2)
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|24000000
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!else
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|10000000
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!endif
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################################################################################
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#
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# Components Section - list of all EDK II Modules needed by this Platform
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#
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################################################################################
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[Components.common]
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#
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# PEI Phase modules
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#
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ArmPlatformPkg/PrePi/PeiMPCore.inf {
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<LibraryClasses>
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
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ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
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ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
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}
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#
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# DXE
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#
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MdeModulePkg/Core/Dxe/DxeMain.inf {
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<LibraryClasses>
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PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
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NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
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}
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#
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# Architectural Protocols
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#
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ArmPkg/Drivers/CpuDxe/CpuDxe.inf
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MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
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MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
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MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
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MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
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MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
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MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
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EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
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EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
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EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
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MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
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MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
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MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
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EmbeddedPkg/SerialDxe/SerialDxe.inf
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MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
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ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
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ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
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#ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
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ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
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ArmPkg/Drivers/TimerDxe/TimerDxe.inf
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ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
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#
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# Filesystems
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#
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!ifndef $(ARM_BIGLITTLE_TC2)
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ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
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!endif
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#
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# Multimedia Card Interface
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#
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EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
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ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
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#
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# FAT filesystem + GPT/MBR partitioning
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#
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MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
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MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
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MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
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MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
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#
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# Bds
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#
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MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
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ArmPlatformPkg/Bds/Bds.inf
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#
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# Copyright (c) 2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
|
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# http://opensource.org/licenses/bsd-license.php
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||||
#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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################################################################################
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#
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# FD Section
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# The [FD] Section is made up of the definition statements and a
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# description of what goes into the Flash Device Image. Each FD section
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# defines one flash "device" image. A flash device image may be one of
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# the following: Removable media bootable image (like a boot floppy
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# image,) an Option ROM image (that would be "flashed" into an add-in
|
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# card,) a System "Flash" image (that would be burned into a system's
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# flash) or an Update ("Capsule") image that will be used to update and
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# existing system flash.
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#
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################################################################################
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[FD.ARM_VEXPRESS_CTA15A7_EFI]
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BaseAddress = 0x81000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM.
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Size = 0x000B0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
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ErasePolarity = 1
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BlockSize = 0x00001000
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NumBlocks = 0xB0
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0x00000000|0x000B0000
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gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
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FV = FVMAIN_COMPACT
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################################################################################
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#
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# FV Section
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#
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# [FV] section is used to define what components or modules are placed within a flash
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# device file. This section also defines order the components and modules are positioned
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# within the image. The [FV] section consists of define statements, set statements and
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# module statements.
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#
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################################################################################
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[FV.FvMain]
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BlockSize = 0x40
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NumBlocks = 0 # This FV gets compressed so make it just big enough
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FvAlignment = 8 # FV alignment and FV attributes setting.
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ERASE_POLARITY = 1
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MEMORY_MAPPED = TRUE
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STICKY_WRITE = TRUE
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LOCK_CAP = TRUE
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LOCK_STATUS = TRUE
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WRITE_DISABLED_CAP = TRUE
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WRITE_ENABLED_CAP = TRUE
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WRITE_STATUS = TRUE
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WRITE_LOCK_CAP = TRUE
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WRITE_LOCK_STATUS = TRUE
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READ_DISABLED_CAP = TRUE
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READ_ENABLED_CAP = TRUE
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READ_STATUS = TRUE
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READ_LOCK_CAP = TRUE
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READ_LOCK_STATUS = TRUE
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INF MdeModulePkg/Core/Dxe/DxeMain.inf
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#
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# PI DXE Drivers producing Architectural Protocols (EFI Services)
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#
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INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
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INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
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INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
|
||||
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
|
||||
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
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INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
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INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
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INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
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INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
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INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
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INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
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||||
|
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#
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# Multiple Console IO support
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#
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INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
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INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
|
||||
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
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INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
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INF EmbeddedPkg/SerialDxe/SerialDxe.inf
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INF ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
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INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
|
||||
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
|
||||
#INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
|
||||
INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
|
||||
INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
|
||||
|
||||
#
|
||||
# Multimedia Card Interface
|
||||
#
|
||||
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
|
||||
INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
|
||||
|
||||
#
|
||||
# Filesystems
|
||||
#
|
||||
!ifndef $(ARM_BIGLITTLE_TC2)
|
||||
INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
|
||||
!endif
|
||||
|
||||
#
|
||||
# FAT filesystem + GPT/MBR partitioning
|
||||
#
|
||||
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
|
||||
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
|
||||
INF FatBinPkg/EnhancedFatDxe/Fat.inf
|
||||
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
|
||||
|
||||
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
|
||||
|
||||
#
|
||||
# UEFI application
|
||||
#
|
||||
INF ShellBinPkg/UefiShell/UefiShell.inf
|
||||
|
||||
#
|
||||
# Bds
|
||||
#
|
||||
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
|
||||
INF ArmPlatformPkg/Bds/Bds.inf
|
||||
|
||||
[FV.FVMAIN_COMPACT]
|
||||
FvBaseAddress = 0x81000000
|
||||
FvForceRebase = TRUE
|
||||
FvAlignment = 8
|
||||
ERASE_POLARITY = 1
|
||||
MEMORY_MAPPED = TRUE
|
||||
STICKY_WRITE = TRUE
|
||||
LOCK_CAP = TRUE
|
||||
LOCK_STATUS = TRUE
|
||||
WRITE_DISABLED_CAP = TRUE
|
||||
WRITE_ENABLED_CAP = TRUE
|
||||
WRITE_STATUS = TRUE
|
||||
WRITE_LOCK_CAP = TRUE
|
||||
WRITE_LOCK_STATUS = TRUE
|
||||
READ_DISABLED_CAP = TRUE
|
||||
READ_ENABLED_CAP = TRUE
|
||||
READ_STATUS = TRUE
|
||||
READ_LOCK_CAP = TRUE
|
||||
READ_LOCK_STATUS = TRUE
|
||||
|
||||
INF ArmPlatformPkg/PrePi/PeiMPCore.inf
|
||||
|
||||
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
|
||||
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
|
||||
SECTION FV_IMAGE = FVMAIN
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
################################################################################
|
||||
#
|
||||
# Rules are use with the [FV] section's module INF type to define
|
||||
# how an FFS file is created for a given INF file. The following Rule are the default
|
||||
# rules for the different module type. User can add the customized rules to define the
|
||||
# content of the FFS file.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
############################################################################
|
||||
# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
|
||||
############################################################################
|
||||
#
|
||||
#[Rule.Common.DXE_DRIVER]
|
||||
# FILE DRIVER = $(NAMED_GUID) {
|
||||
# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
|
||||
# COMPRESS PI_STD {
|
||||
# GUIDED {
|
||||
# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
# UI STRING="$(MODULE_NAME)" Optional
|
||||
# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
|
||||
# }
|
||||
# }
|
||||
# }
|
||||
#
|
||||
############################################################################
|
||||
|
||||
[Rule.Common.SEC]
|
||||
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
|
||||
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
}
|
||||
|
||||
[Rule.Common.PEI_CORE]
|
||||
FILE PEI_CORE = $(NAMED_GUID) {
|
||||
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING ="$(MODULE_NAME)" Optional
|
||||
}
|
||||
|
||||
[Rule.Common.PEIM]
|
||||
FILE PEIM = $(NAMED_GUID) {
|
||||
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
|
||||
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
}
|
||||
|
||||
[Rule.Common.PEIM.TIANOCOMPRESSED]
|
||||
FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
|
||||
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
|
||||
GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
|
||||
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
}
|
||||
}
|
||||
|
||||
[Rule.Common.DXE_CORE]
|
||||
FILE DXE_CORE = $(NAMED_GUID) {
|
||||
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
}
|
||||
|
||||
[Rule.Common.UEFI_DRIVER]
|
||||
FILE DRIVER = $(NAMED_GUID) {
|
||||
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
|
||||
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
}
|
||||
|
||||
[Rule.Common.DXE_DRIVER]
|
||||
FILE DRIVER = $(NAMED_GUID) {
|
||||
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
|
||||
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
}
|
||||
|
||||
[Rule.Common.DXE_RUNTIME_DRIVER]
|
||||
FILE DRIVER = $(NAMED_GUID) {
|
||||
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
|
||||
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
}
|
||||
|
||||
[Rule.Common.UEFI_APPLICATION]
|
||||
FILE APPLICATION = $(NAMED_GUID) {
|
||||
UI STRING ="$(MODULE_NAME)" Optional
|
||||
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
|
||||
}
|
||||
|
||||
[Rule.Common.UEFI_DRIVER.BINARY]
|
||||
FILE DRIVER = $(NAMED_GUID) {
|
||||
DXE_DEPEX DXE_DEPEX Optional |.depex
|
||||
PE32 PE32 |.efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
|
||||
}
|
||||
|
||||
[Rule.Common.UEFI_APPLICATION.BINARY]
|
||||
FILE APPLICATION = $(NAMED_GUID) {
|
||||
PE32 PE32 |.efi
|
||||
UI STRING="$(MODULE_NAME)" Optional
|
||||
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
|
||||
}
|
||||
|
|
@ -49,3 +49,4 @@
|
|||
#
|
||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000003
|
||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000004
|
||||
gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000009
|
||||
|
|
|
|||
|
|
@ -0,0 +1,153 @@
|
|||
/** @file
|
||||
* Header defining Versatile Express constants (Base addresses, sizes, flags)
|
||||
*
|
||||
* Copyright (c) 2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARM_VEXPRESS_CTA15A7_H__
|
||||
#define __ARM_VEXPRESS_CTA15A7_H__
|
||||
|
||||
#include <VExpressMotherBoard.h>
|
||||
|
||||
/***********************************************************************************
|
||||
// Platform Memory Map
|
||||
************************************************************************************/
|
||||
|
||||
// Motherboard Peripheral and On-chip peripheral
|
||||
#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
|
||||
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
|
||||
// Secure NOR Flash
|
||||
#define ARM_VE_SEC_NOR0_BASE 0x00000000
|
||||
#define ARM_VE_SEC_NOR0_SZ SIZE_64MB
|
||||
|
||||
// Secure RAM
|
||||
#define ARM_VE_SEC_RAM0_BASE 0x04000000
|
||||
#define ARM_VE_SEC_RAM0_SZ SIZE_64MB
|
||||
|
||||
#endif
|
||||
|
||||
// NOR Flash 0
|
||||
#define ARM_VE_SMB_NOR0_BASE 0x08000000
|
||||
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
|
||||
// NOR Flash 1
|
||||
#define ARM_VE_SMB_NOR1_BASE 0x0C000000
|
||||
#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
|
||||
|
||||
// SRAM
|
||||
#define ARM_VE_SMB_SRAM_BASE 0x14000000
|
||||
#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
|
||||
|
||||
// USB, Ethernet, VRAM
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
#define ARM_VE_SMB_PERIPH_BASE 0x18000000
|
||||
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZE_16MB)
|
||||
#else
|
||||
#define ARM_VE_SMB_PERIPH_BASE 0x1C000000
|
||||
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB)
|
||||
#endif
|
||||
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
|
||||
|
||||
// On-Chip non-secure ROM
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000
|
||||
#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB
|
||||
#endif
|
||||
|
||||
// On-Chip Peripherals
|
||||
#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000
|
||||
#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000
|
||||
|
||||
// On-Chip non-secure SRAM
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000
|
||||
#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB
|
||||
#endif
|
||||
|
||||
// Allocate a section for the VRAM (Video RAM)
|
||||
// If 0 then allow random memory allocation
|
||||
#define LCD_VRAM_CORE_TILE_BASE 0
|
||||
|
||||
// Define SEC phase sync point
|
||||
#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX + 1)
|
||||
|
||||
/***********************************************************************************
|
||||
Core Tile memory-mapped Peripherals
|
||||
************************************************************************************/
|
||||
|
||||
// PL354 Static Memory Controller Base
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000
|
||||
#else
|
||||
#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
|
||||
#endif
|
||||
|
||||
#define ARM_CTA15A7_SCC_BASE 0x7FFF0000
|
||||
#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x700)
|
||||
|
||||
#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48
|
||||
|
||||
#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)
|
||||
#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)
|
||||
#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)
|
||||
#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)
|
||||
|
||||
#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x3C)
|
||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x68)
|
||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x6C)
|
||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x70)
|
||||
#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x74)
|
||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x78)
|
||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x7C)
|
||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x80)
|
||||
#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x84)
|
||||
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8)
|
||||
#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9)
|
||||
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5)
|
||||
#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6)
|
||||
|
||||
|
||||
/***********************************************************************************
|
||||
// Memory-mapped peripherals
|
||||
************************************************************************************/
|
||||
|
||||
/*// SP810 Controller
|
||||
#undef SP810_CTRL_BASE
|
||||
#define SP810_CTRL_BASE 0x1C020000
|
||||
|
||||
// PL111 Colour LCD Controller
|
||||
#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
|
||||
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
|
||||
#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
|
||||
|
||||
// VRAM offset for the PL111 Colour LCD Controller on the motherboard
|
||||
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
#/* @file
|
||||
#
|
||||
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#*/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = CTA15A7ArmVExpressLib
|
||||
FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmPlatformLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
IoLib
|
||||
ArmLib
|
||||
MemoryAllocationLib
|
||||
SerialPortLib
|
||||
|
||||
[Sources.common]
|
||||
CTA15-A7.c
|
||||
CTA15-A7Mem.c
|
||||
CTA15-A7Helper.asm | RVCT
|
||||
CTA15-A7Helper.S | GCC
|
||||
|
||||
[FeaturePcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdCacheEnable
|
||||
gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
|
||||
gArmPlatformTokenSpaceGuid.PcdStandalone
|
||||
|
||||
[FixedPcd]
|
||||
gArmPlatformTokenSpaceGuid.PcdCoreCount
|
||||
|
||||
gArmTokenSpaceGuid.PcdTrustzoneSupport
|
||||
gArmTokenSpaceGuid.PcdSystemMemoryBase
|
||||
gArmTokenSpaceGuid.PcdSystemMemorySize
|
||||
gArmTokenSpaceGuid.PcdFvBaseAddress
|
||||
|
||||
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
|
||||
gArmTokenSpaceGuid.PcdArmPrimaryCore
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/ArmPlatformLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
#include <Ppi/ArmMpCoreInfo.h>
|
||||
|
||||
#include <ArmPlatform.h>
|
||||
|
||||
ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] = {
|
||||
{
|
||||
// Cluster 0, Core 0
|
||||
0x0, 0x0,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0,
|
||||
(UINT64)0
|
||||
},
|
||||
{
|
||||
// Cluster 0, Core 1
|
||||
0x0, 0x1,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1,
|
||||
(UINT64)0
|
||||
},
|
||||
#ifndef ARM_BIGLITTLE_TC2
|
||||
{
|
||||
// Cluster 0, Core 2
|
||||
0x0, 0x2,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2,
|
||||
(UINT64)0
|
||||
},
|
||||
{
|
||||
// Cluster 0, Core 3
|
||||
0x0, 0x3,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3,
|
||||
(UINT64)0
|
||||
},
|
||||
#endif
|
||||
{
|
||||
// Cluster 1, Core 0
|
||||
0x1, 0x0,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0,
|
||||
(UINT64)0
|
||||
},
|
||||
{
|
||||
// Cluster 1, Core 1
|
||||
0x1, 0x1,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1,
|
||||
(UINT64)0
|
||||
},
|
||||
{
|
||||
// Cluster 1, Core 2
|
||||
0x1, 0x2,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2,
|
||||
(UINT64)0
|
||||
}
|
||||
#ifndef ARM_BIGLITTLE_TC2
|
||||
,{
|
||||
// Cluster 1, Core 3
|
||||
0x1, 0x3,
|
||||
|
||||
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
|
||||
(EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3,
|
||||
(UINT64)0
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
Return the current Boot Mode
|
||||
|
||||
This function returns the boot reason on the platform
|
||||
|
||||
@return Return the current Boot Mode of the platform
|
||||
|
||||
**/
|
||||
EFI_BOOT_MODE
|
||||
ArmPlatformGetBootMode (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return BOOT_WITH_FULL_CONFIGURATION;
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize controllers that must setup in the normal world
|
||||
|
||||
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
|
||||
in the PEI phase.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
ArmPlatformInitialize (
|
||||
IN UINTN MpId
|
||||
)
|
||||
{
|
||||
if (!IS_PRIMARY_CORE(MpId)) {
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
// Nothing to do here
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize the system (or sometimes called permanent) memory
|
||||
|
||||
This memory is generally represented by the DRAM.
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformInitializeSystemMemory (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PrePeiCoreGetMpCoreInfo (
|
||||
OUT UINTN *CoreCount,
|
||||
OUT ARM_CORE_INFO **ArmCoreTable
|
||||
)
|
||||
{
|
||||
// Only support one cluster
|
||||
*CoreCount = sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM_CORE_INFO);
|
||||
*ArmCoreTable = mVersatileExpressCTA15A7InfoTable;
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
|
||||
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
|
||||
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
|
||||
|
||||
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
|
||||
{
|
||||
EFI_PEI_PPI_DESCRIPTOR_PPI,
|
||||
&mArmMpCoreInfoPpiGuid,
|
||||
&mMpCoreInfoPpi
|
||||
}
|
||||
};
|
||||
|
||||
VOID
|
||||
ArmPlatformGetPlatformPpiList (
|
||||
OUT UINTN *PpiListSize,
|
||||
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
|
||||
)
|
||||
{
|
||||
*PpiListSize = sizeof(gPlatformPpiTable);
|
||||
*PpiList = gPlatformPpiTable;
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
//
|
||||
// Copyright (c) 2012, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
|
||||
.text
|
||||
.align 3
|
||||
|
||||
GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
|
||||
|
||||
//UINTN
|
||||
//ArmPlatformGetCorePosition (
|
||||
// IN UINTN MpId
|
||||
// );
|
||||
ASM_PFX(ArmPlatformGetCorePosition):
|
||||
and r1, r0, #ARM_CORE_MASK
|
||||
and r0, r0, #ARM_CLUSTER_MASK
|
||||
add r0, r1, r0, LSR #7
|
||||
bx lr
|
||||
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
//
|
||||
// Copyright (c) 2012, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//
|
||||
|
||||
#include <Library/ArmLib.h>
|
||||
|
||||
INCLUDE AsmMacroIoLib.inc
|
||||
|
||||
EXPORT ArmPlatformGetCorePosition
|
||||
|
||||
PRESERVE8
|
||||
AREA CTA15A7Helper, CODE, READONLY
|
||||
|
||||
//UINTN
|
||||
//ArmPlatformGetCorePosition (
|
||||
// IN UINTN MpId
|
||||
// );
|
||||
ArmPlatformGetCorePosition FUNCTION
|
||||
and r1, r0, #ARM_CORE_MASK
|
||||
and r0, r0, #ARM_CLUSTER_MASK
|
||||
add r0, r1, r0, LSR #7
|
||||
bx lr
|
||||
ENDFUNC
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2012, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#include <Library/ArmPlatformLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/HobLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
#include <ArmPlatform.h>
|
||||
|
||||
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
|
||||
|
||||
// DDR attributes
|
||||
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
|
||||
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
|
||||
|
||||
/**
|
||||
Return the Virtual Memory Map of your platform
|
||||
|
||||
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
|
||||
|
||||
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
|
||||
Virtual Memory mapping. This array must be ended by a zero-filled
|
||||
entry
|
||||
|
||||
**/
|
||||
VOID
|
||||
ArmPlatformGetVirtualMemoryMap (
|
||||
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
|
||||
)
|
||||
{
|
||||
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
|
||||
UINTN Index = 0;
|
||||
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
|
||||
|
||||
ASSERT (VirtualMemoryMap != NULL);
|
||||
|
||||
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
|
||||
if (VirtualMemoryTable == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
|
||||
CacheAttributes = DDR_ATTRIBUTES_CACHED;
|
||||
} else {
|
||||
CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
|
||||
}
|
||||
|
||||
// Detect if it is a 1GB or 2GB Test Chip
|
||||
// [16:19]: 0=1GB TC2, 1=2GB TC2
|
||||
if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {
|
||||
DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));
|
||||
BuildResourceDescriptorHob (
|
||||
EFI_RESOURCE_SYSTEM_MEMORY,
|
||||
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
|
||||
EFI_RESOURCE_ATTRIBUTE_TESTED,
|
||||
PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),
|
||||
0x40000000
|
||||
);
|
||||
}
|
||||
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
// Secure NOR0 Flash
|
||||
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
// Secure RAM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
#endif
|
||||
|
||||
// SMB CS0 - NOR0 Flash
|
||||
VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
|
||||
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
// Environment Variables region
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
|
||||
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
// SMB CS1 or CS4 - NOR1 Flash
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;
|
||||
VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
// Environment Variables region
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);
|
||||
VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
// SMB CS3 or CS1 - PSRAM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
|
||||
// Motherboard peripherals
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
// Non-secure ROM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
#endif
|
||||
|
||||
// OnChip peripherals
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
// SCC Region
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;
|
||||
VirtualMemoryTable[Index].Length = SIZE_64KB;
|
||||
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
|
||||
|
||||
#ifdef ARM_BIGLITTLE_TC2
|
||||
// TC2 OnChip non-secure SRAM
|
||||
VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;
|
||||
VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
#endif
|
||||
|
||||
#ifndef ARM_BIGLITTLE_TC2
|
||||
// Workaround for SRAM bug in RTSM
|
||||
if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {
|
||||
VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;
|
||||
VirtualMemoryTable[Index].VirtualBase = 0x80000000;
|
||||
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
}
|
||||
#endif
|
||||
|
||||
// DDR
|
||||
VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);
|
||||
VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);
|
||||
VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);
|
||||
VirtualMemoryTable[Index].Attributes = CacheAttributes;
|
||||
|
||||
// End of Table
|
||||
VirtualMemoryTable[++Index].PhysicalBase = 0;
|
||||
VirtualMemoryTable[Index].VirtualBase = 0;
|
||||
VirtualMemoryTable[Index].Length = 0;
|
||||
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
||||
|
||||
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
|
||||
|
||||
*VirtualMemoryMap = VirtualMemoryTable;
|
||||
}
|
||||
|
||||
/**
|
||||
Return the EFI Memory Map provided by extension memory on your platform
|
||||
|
||||
This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
|
||||
Descriptor HOBs used by DXE core.
|
||||
|
||||
@param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
|
||||
EFI Memory region. This array must be ended by a zero-filled entry
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
ArmPlatformGetAdditionalSystemMemory (
|
||||
OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
/**
|
||||
|
||||
Copyright (c) 2012, ARM Ltd. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <PiDxe.h>
|
||||
|
||||
#include <Library/ArmPlatformSysConfigLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/LcdPlatformLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Protocol/EdidDiscovered.h>
|
||||
#include <Protocol/EdidActive.h>
|
||||
|
||||
#include <ArmPlatform.h>
|
||||
|
||||
typedef struct {
|
||||
UINT32 Mode;
|
||||
UINT32 HorizontalResolution;
|
||||
UINT32 VerticalResolution;
|
||||
LCD_BPP Bpp;
|
||||
UINT32 OscFreq;
|
||||
|
||||
// These are used by HDLCD
|
||||
UINT32 HSync;
|
||||
UINT32 HBackPorch;
|
||||
UINT32 HFrontPorch;
|
||||
UINT32 VSync;
|
||||
UINT32 VBackPorch;
|
||||
UINT32 VFrontPorch;
|
||||
} LCD_RESOLUTION;
|
||||
|
||||
|
||||
LCD_RESOLUTION mResolutions[] = {
|
||||
{ // Mode 0 : VGA : 640 x 480 x 24 bpp
|
||||
VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY,
|
||||
VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH,
|
||||
VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH
|
||||
},
|
||||
{ // Mode 1 : SVGA : 800 x 600 x 24 bpp
|
||||
SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY,
|
||||
SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH,
|
||||
SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH
|
||||
},
|
||||
{ // Mode 2 : XGA : 1024 x 768 x 24 bpp
|
||||
XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY,
|
||||
XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH,
|
||||
XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH
|
||||
},
|
||||
{ // Mode 3 : SXGA : 1280 x 1024 x 24 bpp
|
||||
SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2),
|
||||
SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH,
|
||||
SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH
|
||||
},
|
||||
{ // Mode 4 : UXGA : 1600 x 1200 x 24 bpp
|
||||
UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2),
|
||||
UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH,
|
||||
UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH
|
||||
},
|
||||
{ // Mode 5 : HD : 1920 x 1080 x 24 bpp
|
||||
HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2),
|
||||
HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH,
|
||||
HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH
|
||||
}
|
||||
};
|
||||
|
||||
EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered = {
|
||||
0,
|
||||
NULL
|
||||
};
|
||||
|
||||
EFI_EDID_ACTIVE_PROTOCOL mEdidActive = {
|
||||
0,
|
||||
NULL
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformInitializeDisplay (
|
||||
IN EFI_HANDLE Handle
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
// Set the FPGA multiplexer to select the video output from the motherboard or the daughterboard
|
||||
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
// Install the EDID Protocols
|
||||
Status = gBS->InstallMultipleProtocolInterfaces (
|
||||
&Handle,
|
||||
&gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered,
|
||||
&gEfiEdidActiveProtocolGuid, &mEdidActive,
|
||||
NULL
|
||||
);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformGetVram (
|
||||
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
|
||||
OUT UINTN* VramSize
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_CPU_ARCH_PROTOCOL *Cpu;
|
||||
EFI_ALLOCATE_TYPE AllocationType;
|
||||
|
||||
// Set the vram size
|
||||
*VramSize = LCD_VRAM_SIZE;
|
||||
|
||||
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE;
|
||||
|
||||
// Allocate the VRAM from the DRAM so that nobody else uses it.
|
||||
if (*VramBaseAddress == 0) {
|
||||
AllocationType = AllocateAnyPages;
|
||||
} else {
|
||||
AllocationType = AllocateAddress;
|
||||
}
|
||||
Status = gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
// Ensure the Cpu architectural protocol is already installed
|
||||
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
// Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable.
|
||||
Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
if (EFI_ERROR(Status)) {
|
||||
gBS->FreePool (VramBaseAddress);
|
||||
return Status;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
UINT32
|
||||
LcdPlatformGetMaxMode (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
//
|
||||
// The following line will report correctly the total number of graphics modes
|
||||
// that could be supported by the graphics driver:
|
||||
//
|
||||
return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION));
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformSetMode (
|
||||
IN UINT32 ModeNumber
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
// Set the video mode oscillator
|
||||
do {
|
||||
Status = ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq);
|
||||
} while (Status == EFI_TIMEOUT);
|
||||
if (EFI_ERROR(Status)) {
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
return Status;
|
||||
}
|
||||
|
||||
// Set the DVI into the new mode
|
||||
do {
|
||||
Status = ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[ModeNumber].Mode);
|
||||
} while (Status == EFI_TIMEOUT);
|
||||
if (EFI_ERROR(Status)) {
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
return Status;
|
||||
}
|
||||
|
||||
// Set the multiplexer
|
||||
Status = ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOARD_1_SITE);
|
||||
if (EFI_ERROR(Status)) {
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
return Status;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformQueryMode (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info
|
||||
)
|
||||
{
|
||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
Info->Version = 0;
|
||||
Info->HorizontalResolution = mResolutions[ModeNumber].HorizontalResolution;
|
||||
Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution;
|
||||
Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution;
|
||||
|
||||
switch (mResolutions[ModeNumber].Bpp) {
|
||||
case LCD_BITS_PER_PIXEL_24:
|
||||
Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
|
||||
Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK;
|
||||
Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK;
|
||||
Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK;
|
||||
Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK;
|
||||
break;
|
||||
|
||||
case LCD_BITS_PER_PIXEL_16_555:
|
||||
case LCD_BITS_PER_PIXEL_16_565:
|
||||
case LCD_BITS_PER_PIXEL_12_444:
|
||||
case LCD_BITS_PER_PIXEL_8:
|
||||
case LCD_BITS_PER_PIXEL_4:
|
||||
case LCD_BITS_PER_PIXEL_2:
|
||||
case LCD_BITS_PER_PIXEL_1:
|
||||
default:
|
||||
// These are not supported
|
||||
ASSERT(FALSE);
|
||||
break;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformGetTimings (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT UINT32* HRes,
|
||||
OUT UINT32* HSync,
|
||||
OUT UINT32* HBackPorch,
|
||||
OUT UINT32* HFrontPorch,
|
||||
OUT UINT32* VRes,
|
||||
OUT UINT32* VSync,
|
||||
OUT UINT32* VBackPorch,
|
||||
OUT UINT32* VFrontPorch
|
||||
)
|
||||
{
|
||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
*HRes = mResolutions[ModeNumber].HorizontalResolution;
|
||||
*HSync = mResolutions[ModeNumber].HSync;
|
||||
*HBackPorch = mResolutions[ModeNumber].HBackPorch;
|
||||
*HFrontPorch = mResolutions[ModeNumber].HFrontPorch;
|
||||
*VRes = mResolutions[ModeNumber].VerticalResolution;
|
||||
*VSync = mResolutions[ModeNumber].VSync;
|
||||
*VBackPorch = mResolutions[ModeNumber].VBackPorch;
|
||||
*VFrontPorch = mResolutions[ModeNumber].VFrontPorch;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
LcdPlatformGetBpp (
|
||||
IN UINT32 ModeNumber,
|
||||
OUT LCD_BPP * Bpp
|
||||
)
|
||||
{
|
||||
if (ModeNumber >= LcdPlatformGetMaxMode ()) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
*Bpp = mResolutions[ModeNumber].Bpp;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
#/** @file
|
||||
#
|
||||
# Component description file for HdLcdArmLib module
|
||||
#
|
||||
# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = HdLcdArmVExpress
|
||||
FILE_GUID = 535a720e-06c0-4bb9-b563-452216abbed4
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = LcdPlatformLib
|
||||
|
||||
[Sources.common]
|
||||
|
||||
HdLcdArmVExpress.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
ArmPlatformSysConfigLib
|
||||
|
||||
[Protocols]
|
||||
gEfiEdidDiscoveredProtocolGuid # Produced
|
||||
gEfiEdidActiveProtocolGuid # Produced
|
||||
|
||||
[Pcd]
|
||||
gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode
|
||||
gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId
|
||||
Loading…
Reference in New Issue