tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

OvmfPkg/PlatformInitLib: q35 mtrr setup fix 

Traditional q35 memory layout is 2.75 GB of low memory, leaving room
for the pcie mmconfig at 0xb0000000 and the 32-bit pci mmio window at
0xc0000000.  Because of that OVMF tags the memory range above
0xb0000000 as uncachable via mtrr.

A while ago qemu started to gigabyte-align memory by default (to make
huge pages more effective) and q35 uses only 2G of low memory in that
case.  Which effectively makes the 32-bit pci mmio window start at
0x80000000.

This patch updates the mtrr setup code accordingly.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Gerd Hoffmann 2022-09-22 07:55:30 +02:00 committed by mergify[bot]
parent 3c0d567c37
commit 2a0bd3bffc
1 changed files with 18 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
OvmfPkg/Library/PlatformInitLib/MemDetect.c
View File

@ -55,15 +55,25 @@ PlatformQemuUc32BaseInitialization (
} }
if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
// LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
// starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
// setting PcdPciExpressBaseAddress such that describing the
// [PcdPciExpressBaseAddress, 4GB) range require a very small number of
// variable MTRRs (preferably 1 or 2).
//
ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32); ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress); ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= LowerMemorySize);
if (LowerMemorySize <= BASE_2GB) {
// Newer qemu with gigabyte aligned memory,
// 32-bit pci mmio window is 2G -> 4G then.
PlatformInfoHob->Uc32Base = BASE_2GB;
} else {
//
// On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
// starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
// setting PcdPciExpressBaseAddress such that describing the
// [PcdPciExpressBaseAddress, 4GB) range require a very small number of
// variable MTRRs (preferably 1 or 2).
//
PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);
}
return; return;
} }