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UefiCpuPkg: Replace Opcode with the corresponding instructions. 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
(tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
This commit is contained in:
Jason 2022-01-10 22:01:18 +08:00 committed by mergify[bot]
parent 7bc8b1d9f4
commit 2aa107c0aa
10 changed files with 43 additions and 43 deletions
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4
UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm
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@ -1,6 +1,6 @@
;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------
;* ;*
;* Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> ;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
;* SPDX-License-Identifier: BSD-2-Clause-Patent ;* SPDX-License-Identifier: BSD-2-Clause-Patent
;* ;*
;* CpuAsm.nasm ;* CpuAsm.nasm
@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector):
push rcx push rcx
lea rax, [setCodeSelectorLongJump] lea rax, [setCodeSelectorLongJump]
push rax push rax
o64 retf retfq
setCodeSelectorLongJump: setCodeSelectorLongJump:
ret ret

11
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
; Module Name: ; Module Name:
@ -32,12 +32,13 @@ ALIGN 8
; exception handler stub table ; exception handler stub table
; ;
AsmIdtVectorBegin: AsmIdtVectorBegin:
%assign Vector 0
%rep 32 %rep 32
db 0x6a ; push #VectorNum push byte %[Vector];
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
push eax push eax
mov eax, ASM_PFX(CommonInterruptEntry) mov eax, ASM_PFX(CommonInterruptEntry)
jmp eax jmp eax
%assign Vector Vector+1
%endrep %endrep
AsmIdtVectorEnd: AsmIdtVectorEnd:
@ -287,7 +288,7 @@ ErrorCodeAndVectorOnStack:
test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
; edx still contains result from CPUID above ; edx still contains result from CPUID above
jz .3 jz .3
db 0xf, 0xae, 0x7 ;fxsave [edi] fxsave [edi]
.3: .3:
;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
@ -320,7 +321,7 @@ ErrorCodeAndVectorOnStack:
; are supported ; are supported
test edx, BIT24 ; Test for FXSAVE/FXRESTOR support test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
jz .4 jz .4
db 0xf, 0xae, 0xe ; fxrstor [esi] fxrstor [esi]
.4: .4:
add esp, 512 add esp, 512

9
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
; Module Name: ; Module Name:
@ -79,8 +79,7 @@ AsmExceptionEntryBegin:
DoIret%[Vector]: DoIret%[Vector]:
iretd iretd
ASM_PFX(ExceptionTaskSwtichEntry%[Vector]): ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
db 0x6a ; push #VectorNum push byte %[Vector]
db %[Vector]
mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
call eax call eax
mov esp, eax ; Restore stack top mov esp, eax ; Restore stack top
@ -244,7 +243,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint):
clts clts
sub esp, 512 sub esp, 512
mov edi, esp mov edi, esp
db 0xf, 0xae, 0x7 ;fxsave [edi] fxsave [edi]
.3: .3:
;; UINT32 ExceptionData; ;; UINT32 ExceptionData;
@ -277,7 +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint):
test edx, BIT24 ; Test for FXSAVE/FXRESTOR support test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
jz .4 jz .4
mov esi, esp mov esi, esp
db 0xf, 0xae, 0xe ; fxrstor [esi] fxrstor [esi]
.4: .4:
add esp, 512 add esp, 512

14
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
; Module Name: ; Module Name:
@ -32,12 +32,13 @@ SECTION .text
ALIGN 8 ALIGN 8
AsmIdtVectorBegin: AsmIdtVectorBegin:
%assign Vector 0
%rep 32 %rep 32
db 0x6a ; push #VectorNum push byte %[Vector]
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
push rax push rax
mov rax, ASM_PFX(CommonInterruptEntry) mov rax, ASM_PFX(CommonInterruptEntry)
jmp rax jmp rax
%assign Vector Vector+1
%endrep %endrep
AsmIdtVectorEnd: AsmIdtVectorEnd:
@ -257,7 +258,7 @@ DrFinish:
;; FX_SAVE_STATE_X64 FxSaveState; ;; FX_SAVE_STATE_X64 FxSaveState;
sub rsp, 512 sub rsp, 512
mov rdi, rsp mov rdi, rsp
db 0xf, 0xae, 0x7 ;fxsave [rdi] fxsave [rdi]
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld cld
@ -284,7 +285,7 @@ DrFinish:
;; FX_SAVE_STATE_X64 FxSaveState; ;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp mov rsi, rsp
db 0xf, 0xae, 0xE ; fxrstor [rsi] fxrstor [rsi]
add rsp, 512 add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
@ -371,8 +372,7 @@ DoReturn:
push qword [rax + 0x18] ; save EFLAGS in new location push qword [rax + 0x18] ; save EFLAGS in new location
mov rax, [rax] ; restore rax mov rax, [rax] ; restore rax
popfq ; restore EFLAGS popfq ; restore EFLAGS
DB 0x48 ; prefix to composite "retq" with next "retf" retfq
retf ; far return
DoIret: DoIret:
iretq iretq

26
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
; Module Name: ; Module Name:
@ -54,12 +54,13 @@ SECTION .text
ALIGN 8 ALIGN 8
AsmIdtVectorBegin: AsmIdtVectorBegin:
%assign Vector 0
%rep 32 %rep 32
db 0x6a ; push #VectorNum push byte %[Vector]
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
push rax push rax
mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry) mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry)
jmp rax jmp rax
%assign Vector Vector+1
%endrep %endrep
AsmIdtVectorEnd: AsmIdtVectorEnd:
@ -280,7 +281,7 @@ DrFinish:
;; FX_SAVE_STATE_X64 FxSaveState; ;; FX_SAVE_STATE_X64 FxSaveState;
sub rsp, 512 sub rsp, 512
mov rdi, rsp mov rdi, rsp
db 0xf, 0xae, 0x7 ;fxsave [rdi] fxsave [rdi]
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld cld
@ -335,15 +336,15 @@ DrFinish:
jz CetDone jz CetDone
; SSP should be 0xFC0 at this point ; SSP should be 0xFC0 at this point
mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token
INCSSP_RAX ; After this SSP should be 0xFE0 incsspq rax ; After this SSP should be 0xFE0
SAVEPREVSSP ; now the shadow stack restore token will be created at 0xFB8 saveprevssp ; now the shadow stack restore token will be created at 0xFB8
READSSP_RAX ; Read new SSP, SSP should be 0xFE8 rdsspq rax ; Read new SSP, SSP should be 0xFE8
sub rax, 0x10 sub rax, 0x10
CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 after this clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this
sub rax, 0x20 sub rax, 0x20
RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will be 0xFB8 rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8
mov rax, 0x01 ; Pop off the new save token created mov rax, 0x01 ; Pop off the new save token created
INCSSP_RAX ; SSP should be 0xFC0 now incsspq rax ; SSP should be 0xFC0 now
CetDone: CetDone:
cli cli
@ -353,7 +354,7 @@ CetDone:
;; FX_SAVE_STATE_X64 FxSaveState; ;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp mov rsi, rsp
db 0xf, 0xae, 0xE ; fxrstor [rsi] fxrstor [rsi]
add rsp, 512 add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
@ -440,8 +441,7 @@ DoReturn:
push qword [rax + 0x18] ; save EFLAGS in new location push qword [rax + 0x18] ; save EFLAGS in new location
mov rax, [rax] ; restore rax mov rax, [rax] ; restore rax
popfq ; restore EFLAGS popfq ; restore EFLAGS
DB 0x48 ; prefix to composite "retq" with next "retf" retfq
retf ; far return
DoIret: DoIret:
iretq iretq

6
UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
; Module Name: ; Module Name:
@ -345,7 +345,7 @@ BITS 64
; ;
; Far return into 32-bit mode ; Far return into 32-bit mode
; ;
o64 retf retfq
BITS 32 BITS 32
CompatMode: CompatMode:
@ -507,7 +507,7 @@ NoSevEs:
; ;
; Far return into 32-bit mode ; Far return into 32-bit mode
; ;
o64 retf retfq
BITS 32 BITS 32
PmEntry: PmEntry:

4
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
@ -13,7 +13,7 @@ ASM_PFX(DisableCet):
; Skip the pushed data for call ; Skip the pushed data for call
mov eax, 1 mov eax, 1
INCSSP_EAX incsspd eax
mov eax, cr4 mov eax, cr4
btr eax, 23 ; clear CET btr eax, 23 ; clear CET

4
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
@ -252,7 +252,7 @@ CetInterruptDone:
mov eax, 0x668 | CR4_CET mov eax, 0x668 | CR4_CET
mov cr4, eax mov cr4, eax
SETSSBSY setssbsy
CetDone: CetDone:

4
UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
@ -14,7 +14,7 @@ ASM_PFX(DisableCet):
; Skip the pushed data for call ; Skip the pushed data for call
mov rax, 1 mov rax, 1
INCSSP_RAX incsspq rax
mov rax, cr4 mov rax, cr4
btr eax, 23 ; clear CET btr eax, 23 ; clear CET

4
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ; ;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
@ -279,7 +279,7 @@ CetInterruptDone:
mov eax, 0x668 | CR4_CET mov eax, 0x668 | CR4_CET
mov cr4, rax mov cr4, rax
SETSSBSY setssbsy
CetDone: CetDone: