mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmGic: Move out the EndOfInterrupt from the interrupt acknowledgement
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15619 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -38,35 +38,14 @@ ArmGicSendSgiTo (
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
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}
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RETURN_STATUS
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UINTN
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EFIAPI
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ArmGicAcknowledgeInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicInterruptInterfaceBase,
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OUT UINTN *CoreId,
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OUT UINTN *InterruptId
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IN UINTN GicInterruptInterfaceBase
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)
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{
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UINT32 Interrupt;
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// Read the Interrupt Acknowledge Register
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Interrupt = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Check if it is a valid interrupt ID
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if ((Interrupt & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {
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// Got a valid SGI number hence signal End of Interrupt by writing to ICCEOIR
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ArmGicEndOfInterrupt (GicInterruptInterfaceBase, Interrupt);
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if (CoreId) {
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*CoreId = (Interrupt >> 10) & 0x7;
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}
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if (InterruptId) {
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*InterruptId = Interrupt & 0x3FF;
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}
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return RETURN_SUCCESS;
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} else {
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return RETURN_INVALID_PARAMETER;
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}
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return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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}
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VOID
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@ -252,10 +252,10 @@ IrqInterruptHandler (
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UINT32 GicInterrupt;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
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GicInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicInterruptInterfaceBase));
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// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
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if (GicInterrupt >= mGicNumInterrupts) {
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if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
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// The special interrupt do not need to be acknowledge
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return;
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}
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@ -1,7 +1,7 @@
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#/** @file
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
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# Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -76,6 +76,9 @@
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#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr) (((IccIdr) >> 12) & 0xF)
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#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr) ((IccIdr) & 0xFFF)
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// Bit Mask for
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#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
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//
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// GIC Secure interfaces
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//
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@ -128,13 +131,10 @@ ArmGicSendSgiTo (
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IN INTN SgiId
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);
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RETURN_STATUS
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UINTN
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EFIAPI
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ArmGicAcknowledgeInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicInterruptInterfaceBase,
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OUT UINTN *CoreId,
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OUT UINTN *InterruptId
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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@ -31,6 +31,7 @@ NonSecureWaitForFirmware (
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)
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{
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VOID (*secondary_start)(VOID);
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UINTN Interrupt;
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// The secondary cores will execute the firmware once wake from WFI.
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secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress);
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@ -38,7 +39,12 @@ NonSecureWaitForFirmware (
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);
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Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
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// Check if it is a valid interrupt ID
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if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
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// Got a valid SGI number hence signal End of Interrupt
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ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
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}
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// Jump to secondary core entry point.
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secondary_start ();
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@ -45,6 +45,7 @@ SecondaryMain (
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UINT32 CoreId;
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VOID (*SecondaryStart)(VOID);
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UINTN SecondaryEntryAddr;
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UINTN Interrupt;
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ClusterId = GET_CLUSTER_ID(MpId);
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CoreId = GET_CORE_ID(MpId);
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@ -87,7 +88,12 @@ SecondaryMain (
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SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);
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Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
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// Check if it is a valid interrupt ID
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if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
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// Got a valid SGI number hence signal End of Interrupt
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ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
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}
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} while (SecondaryEntryAddr == 0);
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// Jump to secondary core entry point.
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@ -55,6 +55,7 @@ SecondaryMain (
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UINT32 CoreId;
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VOID (*SecondaryStart)(VOID);
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UINTN SecondaryEntryAddr;
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UINTN Interrupt;
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ClusterId = GET_CLUSTER_ID(MpId);
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CoreId = GET_CORE_ID(MpId);
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@ -87,7 +88,12 @@ SecondaryMain (
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SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);
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Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
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// Check if it is a valid interrupt ID
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if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
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// Got a valid SGI number hence signal End of Interrupt
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ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
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}
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} while (SecondaryEntryAddr == 0);
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// Jump to secondary core entry point.
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