ArmPkg/ArmGic: Move out the EndOfInterrupt from the interrupt acknowledgement

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15619 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-07-04 11:13:27 +00:00 committed by oliviermartin
parent d80401a16f
commit 2ca815a495
7 changed files with 33 additions and 36 deletions

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011-2012, ARM Limited. All rights reserved. * Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -38,35 +38,14 @@ ArmGicSendSgiTo (
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
} }
RETURN_STATUS UINTN
EFIAPI EFIAPI
ArmGicAcknowledgeInterrupt ( ArmGicAcknowledgeInterrupt (
IN UINTN GicDistributorBase, IN UINTN GicInterruptInterfaceBase
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *CoreId,
OUT UINTN *InterruptId
) )
{ {
UINT32 Interrupt;
// Read the Interrupt Acknowledge Register // Read the Interrupt Acknowledge Register
Interrupt = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Check if it is a valid interrupt ID
if ((Interrupt & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {
// Got a valid SGI number hence signal End of Interrupt by writing to ICCEOIR
ArmGicEndOfInterrupt (GicInterruptInterfaceBase, Interrupt);
if (CoreId) {
*CoreId = (Interrupt >> 10) & 0x7;
}
if (InterruptId) {
*InterruptId = Interrupt & 0x3FF;
}
return RETURN_SUCCESS;
} else {
return RETURN_INVALID_PARAMETER;
}
} }
VOID VOID

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@ -252,10 +252,10 @@ IrqInterruptHandler (
UINT32 GicInterrupt; UINT32 GicInterrupt;
HARDWARE_INTERRUPT_HANDLER InterruptHandler; HARDWARE_INTERRUPT_HANDLER InterruptHandler;
GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR); GicInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicInterruptInterfaceBase));
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt). // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
if (GicInterrupt >= mGicNumInterrupts) { if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
// The special interrupt do not need to be acknowledge // The special interrupt do not need to be acknowledge
return; return;
} }

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@ -1,7 +1,7 @@
#/** @file #/** @file
# #
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR> # Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License

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@ -76,6 +76,9 @@
#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr) (((IccIdr) >> 12) & 0xF) #define ARM_GIC_ICCIDR_GET_REVISION(IccIdr) (((IccIdr) >> 12) & 0xF)
#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr) ((IccIdr) & 0xFFF) #define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr) ((IccIdr) & 0xFFF)
// Bit Mask for
#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
// //
// GIC Secure interfaces // GIC Secure interfaces
// //
@ -128,13 +131,10 @@ ArmGicSendSgiTo (
IN INTN SgiId IN INTN SgiId
); );
RETURN_STATUS UINTN
EFIAPI EFIAPI
ArmGicAcknowledgeInterrupt ( ArmGicAcknowledgeInterrupt (
IN UINTN GicDistributorBase, IN UINTN GicInterruptInterfaceBase
IN UINTN GicInterruptInterfaceBase,
OUT UINTN *CoreId,
OUT UINTN *InterruptId
); );
VOID VOID

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@ -31,6 +31,7 @@ NonSecureWaitForFirmware (
) )
{ {
VOID (*secondary_start)(VOID); VOID (*secondary_start)(VOID);
UINTN Interrupt;
// The secondary cores will execute the firmware once wake from WFI. // The secondary cores will execute the firmware once wake from WFI.
secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress); secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress);
@ -38,7 +39,12 @@ NonSecureWaitForFirmware (
ArmCallWFI(); ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL); Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
// Check if it is a valid interrupt ID
if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
// Got a valid SGI number hence signal End of Interrupt
ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
}
// Jump to secondary core entry point. // Jump to secondary core entry point.
secondary_start (); secondary_start ();

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@ -45,6 +45,7 @@ SecondaryMain (
UINT32 CoreId; UINT32 CoreId;
VOID (*SecondaryStart)(VOID); VOID (*SecondaryStart)(VOID);
UINTN SecondaryEntryAddr; UINTN SecondaryEntryAddr;
UINTN Interrupt;
ClusterId = GET_CLUSTER_ID(MpId); ClusterId = GET_CLUSTER_ID(MpId);
CoreId = GET_CORE_ID(MpId); CoreId = GET_CORE_ID(MpId);
@ -87,7 +88,12 @@ SecondaryMain (
SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress); SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL); Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
// Check if it is a valid interrupt ID
if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
// Got a valid SGI number hence signal End of Interrupt
ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
}
} while (SecondaryEntryAddr == 0); } while (SecondaryEntryAddr == 0);
// Jump to secondary core entry point. // Jump to secondary core entry point.

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@ -55,6 +55,7 @@ SecondaryMain (
UINT32 CoreId; UINT32 CoreId;
VOID (*SecondaryStart)(VOID); VOID (*SecondaryStart)(VOID);
UINTN SecondaryEntryAddr; UINTN SecondaryEntryAddr;
UINTN Interrupt;
ClusterId = GET_CLUSTER_ID(MpId); ClusterId = GET_CLUSTER_ID(MpId);
CoreId = GET_CORE_ID(MpId); CoreId = GET_CORE_ID(MpId);
@ -87,7 +88,12 @@ SecondaryMain (
SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress); SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL); Interrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase));
// Check if it is a valid interrupt ID
if ((Interrupt & ARM_GIC_ICCIAR_ACKINTID) < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {
// Got a valid SGI number hence signal End of Interrupt
ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), Interrupt);
}
} while (SecondaryEntryAddr == 0); } while (SecondaryEntryAddr == 0);
// Jump to secondary core entry point. // Jump to secondary core entry point.