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Fix License Header. 

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wei, David <david.wei@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Cc: Wu, Mike <mike.wu@intel.com>
This commit is contained in:
zwei4 2017-12-25 16:30:50 +08:00
parent 56649f4301
commit 2ec099da13
4 changed files with 523 additions and 616 deletions
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128
Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
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@ -1,69 +1,59 @@
/** @file /** @file
Header file of Serial port hardware definition. Header file of Serial port hardware definition.
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution. the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php. http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation **/
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as #ifndef __PLATFORM_SERIAL_PORT_LIB_H_
permitted by such license, no part of this software or #define __PLATFORM_SERIAL_PORT_LIB_H_
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written #include <Base.h>
consent of Intel Corporation. #include <Library/BaseLib.h>
#include <Library/IoLib.h>
Module Name: PlatformSerialPortLib.h #include <Library/PcdLib.h>
#include <Library/SerialPortLib.h>
**/
//
#ifndef __PLATFORM_SERIAL_PORT_LIB_H_ // UART Register Offsets
#define __PLATFORM_SERIAL_PORT_LIB_H_ //
#define BAUD_LOW_OFFSET 0x00
#include <Base.h> #define BAUD_HIGH_OFFSET 0x01
#include <Library/BaseLib.h> #define IER_OFFSET 0x01
#include <Library/IoLib.h> #define LCR_SHADOW_OFFSET 0x01
#include <Library/PcdLib.h> #define FCR_SHADOW_OFFSET 0x02
#include <Library/SerialPortLib.h> #define IR_CONTROL_OFFSET 0x02
#define FCR_OFFSET 0x02
// #define EIR_OFFSET 0x02
// UART Register Offsets #define BSR_OFFSET 0x03
// #define LCR_OFFSET 0x03
#define BAUD_LOW_OFFSET 0x00 #define MCR_OFFSET 0x04
#define BAUD_HIGH_OFFSET 0x01 #define LSR_OFFSET 0x05
#define IER_OFFSET 0x01 #define MSR_OFFSET 0x06
#define LCR_SHADOW_OFFSET 0x01
#define FCR_SHADOW_OFFSET 0x02 //
#define IR_CONTROL_OFFSET 0x02 // UART Register Bit Defines
#define FCR_OFFSET 0x02 //
#define EIR_OFFSET 0x02 #define LSR_TXRDY 0x20
#define BSR_OFFSET 0x03 #define LSR_RXDA 0x01
#define LCR_OFFSET 0x03 #define DLAB 0x01
#define MCR_OFFSET 0x04
#define LSR_OFFSET 0x05 #define UART_DATA 8
#define MSR_OFFSET 0x06 #define UART_STOP 1
#define UART_PARITY 0
// #define UART_BREAK_SET 0
// UART Register Bit Defines
// VOID
#define LSR_TXRDY 0x20 InitializeSio (
#define LSR_RXDA 0x01 VOID
#define DLAB 0x01 );
#define UART_DATA 8 #endif
#define UART_STOP 1
#define UART_PARITY 0
#define UART_BREAK_SET 0
VOID
InitializeSio (
VOID
);
#endif

514
Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
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@ -1,262 +1,252 @@
/** @file /** @file
Serial I/O Port library functions with no library constructor/destructor Serial I/O Port library functions with no library constructor/destructor
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution. the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php. http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation **/
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as #include "PlatformSerialPortLib.h"
permitted by such license, no part of this software or
documentation may be reproduced, stored in a retrieval system, or UINT16 gComBase = 0x3f8;
transmitted in any form or by any means without the express written UINTN gBps = 115200;
consent of Intel Corporation. UINT8 gData = 8;
UINT8 gStop = 1;
Module Name: SerialPortLib.c UINT8 gParity = 0;
UINT8 gBreakSet = 0;
**/
/**
#include "PlatformSerialPortLib.h" Initialize Serial Port
UINT16 gComBase = 0x3f8; The Baud Rate Divisor registers are programmed and the LCR
UINTN gBps = 115200; is used to configure the communications format. Hard coded
UINT8 gData = 8; UART config comes from globals in DebugSerialPlatform lib.
UINT8 gStop = 1;
UINT8 gParity = 0; @param None
UINT8 gBreakSet = 0;
@retval None
/**
Initialize Serial Port **/
RETURN_STATUS
The Baud Rate Divisor registers are programmed and the LCR EFIAPI
is used to configure the communications format. Hard coded UARTInitialize (
UART config comes from globals in DebugSerialPlatform lib. VOID
)
@param None {
UINTN Divisor;
@retval None UINT8 OutputData;
UINT8 Data;
**/
RETURN_STATUS //
EFIAPI // Map 5..8 to 0..3
UARTInitialize ( //
VOID Data = (UINT8) (gData - (UINT8) 5);
)
{ //
UINTN Divisor; // Calculate divisor for baud generator
UINT8 OutputData; //
UINT8 Data; Divisor = 115200 / gBps;
// //
// Map 5..8 to 0..3 // Set communications format
// //
Data = (UINT8) (gData - (UINT8) 5); OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
IoWrite8 (gComBase + LCR_OFFSET, OutputData);
//
// Calculate divisor for baud generator //
// // Configure baud rate
Divisor = 115200 / gBps; //
IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));
// IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
// Set communications format
// //
OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data)))); // Switch back to bank 0
IoWrite8 (gComBase + LCR_OFFSET, OutputData); //
OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
// IoWrite8 (gComBase + LCR_OFFSET, OutputData);
// Configure baud rate
// return RETURN_SUCCESS;
IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); }
IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));
/**
// Common function to initialize UART Serial device and USB Serial device.
// Switch back to bank 0
// @param None
OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));
IoWrite8 (gComBase + LCR_OFFSET, OutputData); @retval None
return RETURN_SUCCESS; **/
} RETURN_STATUS
EFIAPI
/** SerialPortInitialize (
Common function to initialize UART Serial device and USB Serial device. VOID
)
@param None {
@retval None UARTInitialize ();
**/
RETURN_STATUS return RETURN_SUCCESS;
EFIAPI }
SerialPortInitialize (
VOID /**
) Write data to serial device.
{
If the buffer is NULL, then return 0;
UARTInitialize (); if NumberOfBytes is zero, then return 0.
@param Buffer Point of data buffer which need to be writed.
return RETURN_SUCCESS; @param NumberOfBytes Number of output bytes which are cached in Buffer.
}
@retval 0 Write data failed.
/** @retval !0 Actual number of bytes writed to serial device.
Write data to serial device.
**/
If the buffer is NULL, then return 0; UINTN
if NumberOfBytes is zero, then return 0. EFIAPI
UARTDbgOut (
@param Buffer Point of data buffer which need to be writed. IN UINT8 *Buffer,
@param NumberOfBytes Number of output bytes which are cached in Buffer. IN UINTN NumberOfBytes
)
@retval 0 Write data failed. {
@retval !0 Actual number of bytes writed to serial device. UINTN Result;
UINT8 Data;
**/
UINTN if (NULL == Buffer) {
EFIAPI return 0;
UARTDbgOut ( }
IN UINT8 *Buffer,
IN UINTN NumberOfBytes Result = NumberOfBytes;
)
{ while (NumberOfBytes--) {
UINTN Result; //
UINT8 Data; // Wait for the serial port to be ready.
//
if (NULL == Buffer) { do {
return 0; Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} } while ((Data & LSR_TXRDY) == 0);
IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);
Result = NumberOfBytes; }
while (NumberOfBytes--) { return Result;
// }
// Wait for the serial port to be ready.
// /**
do { Common function to write data to UART Serial device and USB Serial device.
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} while ((Data & LSR_TXRDY) == 0); @param Buffer Point of data buffer which need to be writed.
IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++); @param NumberOfBytes Number of output bytes which are cached in Buffer.
}
**/
return Result; UINTN
} EFIAPI
SerialPortWrite (
/** IN UINT8 *Buffer,
Common function to write data to UART Serial device and USB Serial device. IN UINTN NumberOfBytes
)
@param Buffer Point of data buffer which need to be writed. {
@param NumberOfBytes Number of output bytes which are cached in Buffer. if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgOut (Buffer, NumberOfBytes);
**/ }
UINTN
EFIAPI return RETURN_SUCCESS;
SerialPortWrite ( }
IN UINT8 *Buffer,
IN UINTN NumberOfBytes /**
) Read data from serial device and save the datas in buffer.
{
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) { If the buffer is NULL, then return 0;
UARTDbgOut (Buffer, NumberOfBytes); if NumberOfBytes is zero, then return 0.
}
@param Buffer Point of data buffer which need to be writed.
return RETURN_SUCCESS; @param NumberOfBytes Number of output bytes which are cached in Buffer.
}
@retval 0 Read data failed.
/** @retval !0 Actual number of bytes raed to serial device.
Read data from serial device and save the datas in buffer.
**/
If the buffer is NULL, then return 0; UINTN
if NumberOfBytes is zero, then return 0. EFIAPI
UARTDbgIn (
@param Buffer Point of data buffer which need to be writed. OUT UINT8 *Buffer,
@param NumberOfBytes Number of output bytes which are cached in Buffer. IN UINTN NumberOfBytes
)
@retval 0 Read data failed. {
@retval !0 Actual number of bytes raed to serial device. UINTN Result;
UINT8 Data;
**/
UINTN if (NULL == Buffer) {
EFIAPI return 0;
UARTDbgIn ( }
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes Result = NumberOfBytes;
)
{ while (NumberOfBytes--) {
UINTN Result; //
UINT8 Data; // Wait for the serial port to be ready.
//
if (NULL == Buffer) { do {
return 0; Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
} } while ((Data & LSR_RXDA) == 0);
Result = NumberOfBytes; *Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));
}
while (NumberOfBytes--) {
// return Result;
// Wait for the serial port to be ready. }
//
do { /**
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET); Common function to Read data from UART serial device, USB serial device and save the datas in buffer.
} while ((Data & LSR_RXDA) == 0);
@param Buffer Point of data buffer which need to be writed.
*Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase)); @param NumberOfBytes Number of output bytes which are cached in Buffer.
}
**/
return Result; UINTN
} EFIAPI
SerialPortRead (
/** OUT UINT8 *Buffer,
Common function to Read data from UART serial device, USB serial device and save the datas in buffer. IN UINTN NumberOfBytes
)
@param Buffer Point of data buffer which need to be writed. {
@param NumberOfBytes Number of output bytes which are cached in Buffer. if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgIn (Buffer, NumberOfBytes);
**/ }
UINTN
EFIAPI return RETURN_SUCCESS;
SerialPortRead ( }
OUT UINT8 *Buffer,
IN UINTN NumberOfBytes
) /**
{ Polls a serial device to see if there is any data waiting to be read.
if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {
UARTDbgIn (Buffer, NumberOfBytes); Polls aserial device to see if there is any data waiting to be read.
} If there is data waiting to be read from the serial device, then TRUE is returned.
If there is no data waiting to be read from the serial device, then FALSE is returned.
return RETURN_SUCCESS;
} @retval TRUE Data is waiting to be read from the serial device.
@retval FALSE There is no data waiting to be read from the serial device.
/** **/
Polls a serial device to see if there is any data waiting to be read. BOOLEAN
EFIAPI
Polls aserial device to see if there is any data waiting to be read. SerialPortPoll (
If there is data waiting to be read from the serial device, then TRUE is returned. VOID
If there is no data waiting to be read from the serial device, then FALSE is returned. )
{
@retval TRUE Data is waiting to be read from the serial device. UINT8 Data;
@retval FALSE There is no data waiting to be read from the serial device.
//
**/ // Read the serial port status.
BOOLEAN //
EFIAPI Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
SerialPortPoll (
VOID return (BOOLEAN) ((Data & LSR_RXDA) != 0);
) }
{
UINT8 Data;
//
// Read the serial port status.
//
Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);
return (BOOLEAN) ((Data & LSR_RXDA) != 0);
}

146
Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
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@ -1,78 +1,68 @@
/** @file /** @file
Header file of Serial port hardware definition. Header file of Serial port hardware definition.
Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution. the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php. http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This software and associated documentation **/
(if any) is furnished under a license and may only be used or
copied in accordance with the terms of the license. Except as #ifndef _SIO_INIT_H_
permitted by such license, no part of this software or #define _SIO_INIT_H_
documentation may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means without the express written #define WPCN381U_CONFIG_INDEX 0x2E
consent of Intel Corporation. #define WPCN381U_CONFIG_DATA 0x2F
#define WPCN381U_CONFIG_INDEX1 0x164E
Module Name: PlatformSerialPortLib.h #define WPCN381U_CONFIG_DATA1 0x164F
#define WPCN381U_CHIP_ID 0xF4
**/ #define WDCP376_CHIP_ID 0xF1
#ifndef _SIO_INIT_H_ //
#define _SIO_INIT_H_ // SIO Logical Devices Numbers
//
#define WPCN381U_CONFIG_INDEX 0x2E #define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller
#define WPCN381U_CONFIG_DATA 0x2F #define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller
#define WPCN381U_CONFIG_INDEX1 0x164E #define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
#define WPCN381U_CONFIG_DATA1 0x164F #define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller
#define WPCN381U_CHIP_ID 0xF4 #define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller
#define WDCP376_CHIP_ID 0xF1 #define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller
#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source
// #define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
// SIO Logical Devices Numbers
// //
#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller // SIO Registers Layout
#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller //
#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller #define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address
#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller #define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller #define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address
#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller #define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address
#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source #define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address
#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO #define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address
// #define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
// SIO Registers Layout #define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address
//
#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address //
#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address // SIO Activation Values
#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address //
#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address #define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address #define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address //
#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address // SIO GPIO
#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address //
#define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address
//
// SIO Activation Values //
// // SIO Serial Port Settings
#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device //
#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device #define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
#define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
//
// SIO GPIO #endif
//
#define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address
//
// SIO Serial Port Settings
//
#define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
#define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
#endif

351
Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.h
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@ -1,207 +1,144 @@
/*++ /*++
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution. the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php. http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name: Module Name:
PlatformStatusCode.h PlatformStatusCode.h
Abstract: Abstract:
Contains Platform specific implementations required to use status codes. Contains Platform specific implementations required to use status codes.
--*/ --*/
#ifndef _PLATFORM_STATUS_CODE_H_ #ifndef _PLATFORM_STATUS_CODE_H_
#define _PLATFORM_STATUS_CODE_H_ #define _PLATFORM_STATUS_CODE_H_
#define CONFIG_PORT0 0x4E #define CONFIG_PORT0 0x4E
#define INDEX_PORT0 0x4E #define INDEX_PORT0 0x4E
#define DATA_PORT0 0x4F #define DATA_PORT0 0x4F
#define PCI_IDX 0xCF8 #define PCI_IDX 0xCF8
#define PCI_DAT 0xCFC #define PCI_DAT 0xCFC
#include "MonoStatusCode.h" #include "MonoStatusCode.h"
#ifndef _PEI_PORT_80_STATUS_CODE_H_
/*++ #define _PEI_PORT_80_STATUS_CODE_H_
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under //
the terms and conditions of the BSD License that accompanies this distribution. // Status code reporting function
The full text of the license may be found at //
http://opensource.org/licenses/bsd-license.php. EFI_STATUS
Port80ReportStatusCode (
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, IN CONST EFI_PEI_SERVICES **PeiServices,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. IN EFI_STATUS_CODE_TYPE CodeType,
IN EFI_STATUS_CODE_VALUE Value,
This software and associated documentation (if any) is furnished IN UINT32 Instance,
under a license and may only be used or copied in accordance IN CONST EFI_GUID * CallerId,
with the terms of the license. Except as permitted by such IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
license, no part of this software or documentation may be );
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of #endif
Intel Corporation.
#ifndef _PEI_SERIAL_STATUS_CODE_LIB_H_
#define _PEI_SERIAL_STATUS_CODE_LIB_H_
Module Name:
Port80StatusCodeLib.h #include <Guid/StatusCodeDataTypeId.h>
#include <Guid/StatusCodeDataTypeDebug.h>
Abstract: #include <Library/ReportStatusCodeLib.h>
#include <Library/PrintLib.h>
Lib to provide status code reporting via port 80. #include <Library/BaseMemoryLib.h>
--*/ //
// Initialization function
#ifndef _PEI_PORT_80_STATUS_CODE_H_ //
#define _PEI_PORT_80_STATUS_CODE_H_ VOID
SerialInitializeStatusCode (
VOID
);
//
// Status code reporting function //
// // Status code reporting function
EFI_STATUS //
Port80ReportStatusCode ( EFI_STATUS
IN CONST EFI_PEI_SERVICES **PeiServices, SerialReportStatusCode (
IN EFI_STATUS_CODE_TYPE CodeType, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_STATUS_CODE_VALUE Value, IN EFI_STATUS_CODE_TYPE CodeType,
IN UINT32 Instance, IN EFI_STATUS_CODE_VALUE Value,
IN CONST EFI_GUID * CallerId, IN UINT32 Instance,
IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL IN CONST EFI_GUID * CallerId,
); IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
);
#endif
#endif
/*++
extern EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi;
Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved extern EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode;
#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
This program and the accompanying materials are licensed and made available under #define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
the terms and conditions of the BSD License that accompanies this distribution. #define STATUSCODE_PEIM_SIGNATURE EFI_SIGNATURE_32 ('p', 's', 't', 'c')
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php. typedef struct {
UINT32 Signature;
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, EFI_FFS_FILE_HEADER *FfsHeader;
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. EFI_PEI_NOTIFY_DESCRIPTOR StatusCodeNotify;
} STATUSCODE_CALLBACK_STATE_INFORMATION;
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance #pragma pack(1)
with the terms of the license. Except as permitted by such typedef struct {
license, no part of this software or documentation may be UINT16 Limit;
reproduced, stored in a retrieval system, or transmitted in any UINT32 Base;
form or by any means without the express written consent of } GDT_DSCRIPTOR;
Intel Corporation. #pragma pack()
#define STATUSCODE_PEIM_FROM_THIS(a) \
Module Name: BASE_CR ( \
a, \
SerialStatusCodeLib.h STATUSCODE_CALLBACK_STATE_INFORMATION, \
StatusCodeNotify \
Abstract: )
Lib to provide Serial I/O status code reporting. VOID
EFIAPI
--*/ PlatformInitializeStatusCode (
IN EFI_FFS_FILE_HEADER *FfsHeader,
#ifndef _PEI_SERIAL_STATUS_CODE_LIB_H_ IN CONST EFI_PEI_SERVICES **PeiServices
#define _PEI_SERIAL_STATUS_CODE_LIB_H_ );
#include <Guid/StatusCodeDataTypeId.h> //
#include <Guid/StatusCodeDataTypeDebug.h> // Function declarations
#include <Library/ReportStatusCodeLib.h> //
#include <Library/PrintLib.h> /**
#include <Library/BaseMemoryLib.h> Install Firmware Volume Hob's once there is main memory
// @param PeiServices General purpose services available to every PEIM.
// Initialization function @param NotifyDescriptor Not Used
// @param Ppi Not Used
VOID
SerialInitializeStatusCode ( @retval Status EFI_SUCCESS if the interface could be successfully
VOID installed
);
**/
// EFI_STATUS
// Status code reporting function EFIAPI
// MemoryDiscoveredPpiNotifyCallback (
EFI_STATUS IN EFI_PEI_SERVICES **PeiServices,
SerialReportStatusCode ( IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN CONST EFI_PEI_SERVICES **PeiServices, IN VOID *Ppi
IN EFI_STATUS_CODE_TYPE CodeType, );
IN EFI_STATUS_CODE_VALUE Value,
IN UINT32 Instance, #endif
IN CONST EFI_GUID * CallerId,
IN CONST EFI_STATUS_CODE_DATA * Data OPTIONAL
);
#endif
extern EFI_PEI_PROGRESS_CODE_PPI mStatusCodePpi;
extern EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode;
#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
#define STATUSCODE_PEIM_SIGNATURE EFI_SIGNATURE_32 ('p', 's', 't', 'c')
typedef struct {
UINT32 Signature;
EFI_FFS_FILE_HEADER *FfsHeader;
EFI_PEI_NOTIFY_DESCRIPTOR StatusCodeNotify;
} STATUSCODE_CALLBACK_STATE_INFORMATION;
#pragma pack(1)
typedef struct {
UINT16 Limit;
UINT32 Base;
} GDT_DSCRIPTOR;
#pragma pack()
#define STATUSCODE_PEIM_FROM_THIS(a) \
BASE_CR ( \
a, \
STATUSCODE_CALLBACK_STATE_INFORMATION, \
StatusCodeNotify \
)
VOID
EFIAPI
PlatformInitializeStatusCode (
IN EFI_FFS_FILE_HEADER *FfsHeader,
IN CONST EFI_PEI_SERVICES **PeiServices
);
//
// Function declarations
//
/**
Install Firmware Volume Hob's once there is main memory
@param PeiServices General purpose services available to every PEIM.
@param NotifyDescriptor Not Used
@param Ppi Not Used
@retval Status EFI_SUCCESS if the interface could be successfully
installed
**/
EFI_STATUS
EFIAPI
MemoryDiscoveredPpiNotifyCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
);
#endif