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Enable NEON (SIMD instructions) via coprocessor register so CopyMem/SetMem can use VLDM and friends if you want. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10386 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-04-21 17:40:27 +00:00
parent 5efb9132d3
commit 2ed3c9ccf8
2 changed files with 15 additions and 0 deletions
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8
BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S
View File

@ -36,6 +36,14 @@ ASM_PFX(_ModuleEntryPoint):
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
// Enable NEON register in case folks want to use them for optimizations (CopyMem)
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC
mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
// Set CPU vectors to start of DRAM // Set CPU vectors to start of DRAM
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
mcr p15, 0, r0, c12, c0, 0 mcr p15, 0, r0, c12, c0, 0

7
BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm
View File

@ -39,6 +39,13 @@ _ModuleEntryPoint
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
// Enable NEON register in case folks want to use them for optimizations (CopyMem)
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC
msr FPEXC,r0
// Set CPU vectors to start of DRAM // Set CPU vectors to start of DRAM
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
mcr p15, 0, r0, c12, c0, 0 mcr p15, 0, r0, c12, c0, 0