diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
new file mode 100644
index 0000000000..9773f450e3
--- /dev/null
+++ b/ArmPkg/ArmPkg.dec
@@ -0,0 +1,36 @@
+#%HEADER%
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = ArmPkg
+ PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[LibraryClasses.common]
+ SemihostLib|Include/Library/Semihosting.h
+
+[Guids.common]
+ gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
+
+[Protocols.common]
+ gTimerDebugSupportProtocolGuid = { 0x68300561, 0x0197, 0x465d, { 0xb5, 0xa1, 0x28, 0xeb, 0xa1, 0x98, 0xdd, 0x0b } }
+
+[PcdsFeatureFlag.common]
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
+
+[PcdsFixedAtBuild.common]
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xfff00000|UINT32|0x00000004
+ gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
new file mode 100644
index 0000000000..ca4f4fa555
--- /dev/null
+++ b/ArmPkg/ArmPkg.dsc
@@ -0,0 +1,61 @@
+#%HEADER%
+#/** @file
+#
+# ARM Package
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmPkg
+ PLATFORM_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/Arm
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+
+
+[LibraryClasses.common]
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/Null/NullArmLib.inf
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+
+[Components.common]
+ ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
+ ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
+ ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
+ ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
+ ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+ ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
+ ArmPkg/Library/ArmLib/Null/NullArmLib.inf
+ ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+ ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
+ ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
+ ArmPkg/Library/SemihostLib/SemihostLib.inf
+ ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644
index 0000000000..c57dac2f74
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
@@ -0,0 +1,154 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuDxe.h"
+
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+ switch (FlushType) {
+ case EfiCpuFlushTypeWriteBack:
+ WriteBackDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ case EfiCpuFlushTypeInvalidate:
+ InvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ case EfiCpuFlushTypeWriteBackInvalidate:
+ WriteBackInvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ if (ArmProcessorMode() != ARM_PROCESSOR_MODE_IRQ) {
+ ArmEnableInterrupts();
+ }
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ if (ArmProcessorMode() != ARM_PROCESSOR_MODE_IRQ) {
+ ArmDisableInterrupts();
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ )
+{
+ if (State == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *State = ArmGetInterruptState();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ return RegisterInterruptHandler(InterruptType, InterruptHandler);
+}
+
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+//
+// Globals used to initialize the protocol
+//
+EFI_HANDLE mCpuHandle = NULL;
+EFI_CPU_ARCH_PROTOCOL mCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 0, // NumberOfTimers
+ 4, // DmaBufferAlignment
+};
+
+EFI_STATUS
+CpuDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ InitializeExceptions(&mCpu);
+ return gBS->InstallMultipleProtocolInterfaces(&mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, NULL);
+}
+
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
new file mode 100644
index 0000000000..36133e11c3
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
@@ -0,0 +1,91 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CPU_DXE_ARM_EXCEPTION_H__
+#define __CPU_DXE_ARM_EXCEPTION_H__
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterDebuggerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+
+EFI_STATUS
+InitializeExceptions (
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ );
+
+#endif // __CPU_DXE_ARM_EXCEPTION_H__
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
new file mode 100644
index 0000000000..314965ca4a
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
@@ -0,0 +1,56 @@
+#%HEADER%
+#/** @file
+#
+# DXE CPU driver
+#
+# Copyright (c) 2009, Apple Inc.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmCpuDxe
+ FILE_GUID = B8D9777E-D72A-451F-9BDB-BAFB52A68415
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = CpuDxeInitialize
+
+[Sources.ARM]
+ CpuDxe.c
+ CpuDxe.h
+ DebugSupport.c
+ Exception.c
+ ExceptionSupport.asm | RVCT
+ ExceptionSupport.S | GCC
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ CacheMaintenanceLib
+ UefiDriverEntryPoint
+ ArmLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+ gEfiDebugSupportPeriodicCallbackProtocolGuid
+
+[Pcd.common]
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
+
+[FeaturePcd.common]
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport
+
+[depex]
+ gHardwareInterruptProtocolGuid
diff --git a/ArmPkg/Drivers/CpuDxe/DebugSupport.c b/ArmPkg/Drivers/CpuDxe/DebugSupport.c
new file mode 100644
index 0000000000..b8a5584939
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/DebugSupport.c
@@ -0,0 +1,247 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/** @file
+ DXE Cpu Driver.
+
+ May need some porting work for platform specifics.
+
+ Copyright (c) 2008, Apple Inc
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuDxe.h"
+
+EFI_PERIODIC_CALLBACK gPeriodicCallBack = (EFI_PERIODIC_CALLBACK)NULL;
+
+EFI_DEBUG_SUPPORT_PERIODIC_CALLBACK_PROTOCOL *gDebugSupportCallback = NULL;
+
+
+EFI_STATUS
+EFIAPI
+DebugSupportGetMaximumProcessorIndex (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ OUT UINTN *MaxProcessorIndex
+ )
+/*++
+
+Routine Description: This is a DebugSupport protocol member function.
+
+Arguments:
+ This - The DebugSupport instance
+ MaxProcessorIndex - The maximuim supported processor index
+
+Returns:
+ Always returns EFI_SUCCESS with *MaxProcessorIndex set to 0
+
+--*/
+{
+ *MaxProcessorIndex = 0;
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+DebugSupportRegisterPeriodicCallback (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN EFI_PERIODIC_CALLBACK PeriodicCallback
+ )
+/*++
+
+Routine Description: This is a DebugSupport protocol member function.
+
+Arguments:
+ This - The DebugSupport instance
+ ProcessorIndex - Which processor the callback applies to.
+ PeriodicCallback - Callback function
+
+Returns:
+
+ EFI_SUCCESS
+ EFI_INVALID_PARAMETER - requested uninstalling a handler from a vector that has
+ no handler registered for it
+ EFI_ALREADY_STARTED - requested install to a vector that already has a handler registered.
+
+ Other possible return values are passed through from UnHookEntry and HookEntry.
+
+--*/
+{
+ if (ProcessorIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((gPeriodicCallBack != (EFI_PERIODIC_CALLBACK)NULL) && (PeriodicCallback != (EFI_PERIODIC_CALLBACK)NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gPeriodicCallBack = PeriodicCallback;
+
+ if (gDebugSupportCallback != NULL) {
+ //
+ // We can only update this protocol if the Register Protocol Notify has fired. If it fires
+ // after this call it will update with gPeriodicCallBack value.
+ //
+ gDebugSupportCallback->PeriodicCallback = gPeriodicCallBack;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+DebugSupportRegisterExceptionCallback (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN EFI_EXCEPTION_CALLBACK NewCallback,
+ IN EFI_EXCEPTION_TYPE ExceptionType
+ )
+/*++
+
+Routine Description:
+ This is a DebugSupport protocol member function.
+
+ This code executes in boot services context.
+
+Arguments:
+ This - The DebugSupport instance
+ ProcessorIndex - Which processor the callback applies to.
+ NewCallback - Callback function
+ ExceptionType - Which exception to hook
+
+Returns:
+
+ EFI_SUCCESS
+ EFI_INVALID_PARAMETER - requested uninstalling a handler from a vector that has
+ no handler registered for it
+ EFI_ALREADY_STARTED - requested install to a vector that already has a handler registered.
+
+ Other possible return values are passed through from UnHookEntry and HookEntry.
+
+--*/
+{
+ if (ProcessorIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return RegisterDebuggerInterruptHandler (ExceptionType, NewCallback);
+}
+
+
+EFI_STATUS
+EFIAPI
+DebugSupportInvalidateInstructionCache (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN VOID *Start,
+ IN UINT64 Length
+ )
+/*++
+
+Routine Description:
+ This is a DebugSupport protocol member function.
+ Calls assembly routine to flush cache.
+
+Arguments:
+ This - The DebugSupport instance
+ ProcessorIndex - Which processor the callback applies to.
+ Start - Physical base of the memory range to be invalidated
+ Length - mininum number of bytes in instruction cache to invalidate
+
+Returns:
+
+ EFI_SUCCESS - always return success
+
+--*/
+{
+ if (ProcessorIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ InvalidateInstructionCache();
+
+ return EFI_SUCCESS;
+}
+
+//
+// This is a global that is the actual interface
+//
+EFI_DEBUG_SUPPORT_PROTOCOL gDebugSupportProtocolInterface = {
+ IsaArm, // Fixme to be more generic
+ DebugSupportGetMaximumProcessorIndex,
+ DebugSupportRegisterPeriodicCallback,
+ DebugSupportRegisterExceptionCallback,
+ DebugSupportInvalidateInstructionCache
+};
+
+
+VOID
+EFIAPI
+DebugSupportPeriodicCallbackEventProtocolNotify (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol (&gEfiDebugSupportPeriodicCallbackProtocolGuid, NULL, (VOID **)&gDebugSupportCallback);
+ if (!EFI_ERROR (Status)) {
+ gDebugSupportCallback->PeriodicCallback = gPeriodicCallBack;
+ }
+}
+
+VOID *gRegistration = NULL;
+
+
+EFI_DEBUG_SUPPORT_PROTOCOL *
+InitilaizeDebugSupport (
+ VOID
+ )
+{
+ // RPN gEfiDebugSupportPeriodicCallbackProtocolGuid
+ EFI_STATUS Status;
+ EFI_EVENT Event;
+
+ if (!FeaturePcdGet (PcdCpuDxeProduceDebugSupport)) {
+ // Don't include this code unless Feature Flag is set
+ return NULL;
+ }
+
+
+ Status = gBS->CreateEvent (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ DebugSupportPeriodicCallbackEventProtocolNotify,
+ NULL,
+ &Event
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->RegisterProtocolNotify (&gEfiDebugSupportPeriodicCallbackProtocolGuid, Event, &gRegistration);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // We assume the Timer must depend on our driver to register interrupts so we don't need to do
+ // a gBS->SignalEvent (Event) here to check to see if the protocol allready exists
+ //
+
+ return &gDebugSupportProtocolInterface;
+}
diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c
new file mode 100644
index 0000000000..fa256e60f8
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/Exception.c
@@ -0,0 +1,238 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuDxe.h"
+#include
+
+VOID
+ExceptionHandlersStart (
+ VOID
+ );
+
+VOID
+ExceptionHandlersEnd (
+ VOID
+ );
+
+VOID
+CommonExceptionEntry (
+ VOID
+ );
+
+VOID
+AsmCommonExceptionEntry (
+ VOID
+ );
+
+
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1];
+EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1];
+
+
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ if (InterruptType > MAX_ARM_EXCEPTION) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gExceptionHandlers[InterruptType] = InterruptHandler;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+
+ @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts
+ are enabled and FALSE if interrupts are disabled.
+ @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
+
+**/
+EFI_STATUS
+RegisterDebuggerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ if (InterruptType > MAX_ARM_EXCEPTION) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((InterruptHandler != NULL) && (gDebuggerExceptionHandlers[InterruptType] != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gDebuggerExceptionHandlers[InterruptType] = InterruptHandler;
+
+ return EFI_SUCCESS;
+}
+
+
+
+VOID
+EFIAPI
+CommonCExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ BOOLEAN Dispatched = FALSE;
+
+ if (ExceptionType <= MAX_ARM_EXCEPTION) {
+ if (gDebuggerExceptionHandlers[ExceptionType]) {
+ //
+ // If DebugSupport hooked the interrupt call the handler. This does not disable
+ // the normal handler.
+ //
+ gDebuggerExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);
+ Dispatched = TRUE;
+ }
+ if (gExceptionHandlers[ExceptionType]) {
+ gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);
+ Dispatched = TRUE;
+ }
+ }
+
+ if (Dispatched) {
+ //
+ // We did work so this was an expected ExceptionType
+ //
+ return;
+ }
+
+ if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {
+ //
+ // ARM JTAG debuggers some times use this vector, so it is not an error to get one
+ //
+ return;
+ }
+
+ //
+ // Code after here is the default exception handler...
+ //
+ DEBUG ((EFI_D_ERROR, "Exception %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));
+ ASSERT (FALSE);
+
+}
+
+
+
+EFI_STATUS
+InitializeExceptions (
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN Length;
+ UINTN Index;
+ BOOLEAN Enabled;
+ EFI_PHYSICAL_ADDRESS Base;
+
+ //
+ // Disable interrupts
+ //
+ Cpu->GetInterruptState (Cpu, &Enabled);
+ Cpu->DisableInterrupt (Cpu);
+
+ //
+ // Initialize the C entry points for interrupts
+ //
+ for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {
+ Status = RegisterInterruptHandler (Index, NULL);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = RegisterDebuggerInterruptHandler (Index, NULL);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ //
+ // Copy an implementation of the ARM exception vectors to 0x0.
+ //
+ Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;
+
+ //
+ // Reserve space for the exception handlers
+ //
+ Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);
+ Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);
+ // If the request was for memory that's not in the memory map (which is often the case for 0x00000000
+ // on embedded systems, for example, we don't want to hang up. So we'll check here for a status of
+ // EFI_NOT_FOUND, and continue in that case.
+ if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ CopyMem ((VOID *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress), (VOID *)ExceptionHandlersStart, Length);
+
+ //
+ // Patch in the common Assembly exception handler
+ //
+ Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;
+ *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;
+
+ // Flush Caches since we updated executable stuff
+ InvalidateInstructionCacheRange((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);
+
+ if (Enabled) {
+ //
+ // Restore interrupt state
+ //
+ Status = Cpu->EnableInterrupt (Cpu);
+ }
+
+ return Status;
+}
diff --git a/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S
new file mode 100755
index 0000000000..8574af6d71
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S
@@ -0,0 +1,152 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+
+.globl ASM_PFX(ExceptionHandlersStart)
+.globl ASM_PFX(ExceptionHandlersEnd)
+.globl ASM_PFX(CommonExceptionEntry)
+.globl ASM_PFX(AsmCommonExceptionEntry)
+.globl ASM_PFX(CommonCExceptionHandler)
+
+ASM_PFX(ExceptionHandlersStart):
+
+ASM_PFX(Reset):
+ b ASM_PFX(ResetEntry)
+
+ASM_PFX(UndefinedInstruction):
+ b ASM_PFX(UndefinedInstructionEntry)
+
+ASM_PFX(SoftwareInterrupt):
+ b ASM_PFX(SoftwareInterruptEntry)
+
+ASM_PFX(PrefetchAbort):
+ b ASM_PFX(PrefetchAbortEntry)
+
+ASM_PFX(DataAbort):
+ b ASM_PFX(DataAbortEntry)
+
+ASM_PFX(ReservedException):
+ b ASM_PFX(ReservedExceptionEntry)
+
+ASM_PFX(Irq):
+ b ASM_PFX(IrqEntry)
+
+ASM_PFX(Fiq):
+ b ASM_PFX(FiqEntry)
+
+ASM_PFX(ResetEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#0
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(UndefinedInstructionEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#1
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(SoftwareInterruptEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#2
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(PrefetchAbortEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#3
+ sub lr,lr,#4
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(DataAbortEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#4
+ sub lr,lr,#8
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(ReservedExceptionEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#5
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(IrqEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#6
+ sub lr,lr,#4
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(FiqEntry):
+ stmfd sp!,{r0-r1}
+ mov r0,#7
+ sub lr,lr,#4
+ ldr r1,ASM_PFX(CommonExceptionEntry)
+ bx r1
+
+ASM_PFX(CommonExceptionEntry):
+ .byte 0x12
+ .byte 0x34
+ .byte 0x56
+ .byte 0x78
+
+ASM_PFX(ExceptionHandlersEnd):
+
+ASM_PFX(AsmCommonExceptionEntry):
+ mrc p15, 0, r1, c6, c0, 2 @ Read IFAR
+ stmfd sp!,{r1} @ Store the IFAR
+
+ mrc p15, 0, r1, c5, c0, 1 @ Read IFSR
+ stmfd sp!,{r1} @ Store the IFSR
+
+ mrc p15, 0, r1, c6, c0, 0 @ Read DFAR
+ stmfd sp!,{r1} @ Store the DFAR
+
+ mrc p15, 0, r1, c5, c0, 0 @ Read DFSR
+ stmfd sp!,{r1} @ Store the DFSR
+
+ mrs r1,spsr @ Read SPSR (which is the pre-exception CPSR)
+ stmfd sp!,{r1} @ Store the SPSR
+
+ stmfd sp!,{lr} @ Store the link register (which is the pre-exception PC)
+ stmfd sp,{sp,lr}^ @ Store user/system mode stack pointer and link register
+ nop @ Required by ARM architecture
+ sub sp,sp,#0x08 @ Adjust stack pointer
+ stmfd sp!,{r2-r12} @ Store general purpose registers
+
+ ldr r3,[sp,#0x50] @ Read saved R1 from the stack (it was saved by the exception entry routine)
+ ldr r2,[sp,#0x4C] @ Read saved R0 from the stack (it was saved by the exception entry routine)
+ stmfd sp!,{r2-r3} @ Store general purpose registers R0 and R1
+
+ mov r1,sp @ Prepare System Context pointer as an argument for the exception handler
+
+ sub sp,sp,#4 @ Adjust SP to preserve 8-byte alignment
+ bl ASM_PFX(CommonCExceptionHandler) @ Call exception handler
+ add sp,sp,#4 @ Adjust SP back to where we were
+
+ ldr r2,[sp,#0x40] @ Load CPSR from context, in case it has changed
+ msr SPSR_cxsf,r2 @ Store it back to the SPSR to be restored when exiting this handler
+
+ ldmfd sp!,{r0-r12} @ Restore general purpose registers
+ ldmia sp,{sp,lr}^ @ Restore user/system mode stack pointer and link register
+ nop @ Required by ARM architecture
+ add sp,sp,#0x08 @ Adjust stack pointer
+ ldmfd sp!,{lr} @ Restore the link register (which is the pre-exception PC)
+ add sp,sp,#0x1C @ Clear out the remaining stack space
+ movs pc,lr @ Return from exception
+
diff --git a/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm
new file mode 100755
index 0000000000..d91720cff3
--- /dev/null
+++ b/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm
@@ -0,0 +1,152 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ExceptionHandlersStart
+ EXPORT ExceptionHandlersEnd
+ EXPORT CommonExceptionEntry
+ EXPORT AsmCommonExceptionEntry
+ IMPORT CommonCExceptionHandler
+
+ PRESERVE8
+ AREA DxeExceptionHandlers, CODE, READONLY
+
+ExceptionHandlersStart
+
+Reset
+ b ResetEntry
+
+UndefinedInstruction
+ b UndefinedInstructionEntry
+
+SoftwareInterrupt
+ b SoftwareInterruptEntry
+
+PrefetchAbort
+ b PrefetchAbortEntry
+
+DataAbort
+ b DataAbortEntry
+
+ReservedException
+ b ReservedExceptionEntry
+
+Irq
+ b IrqEntry
+
+Fiq
+ b FiqEntry
+
+ResetEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#0
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+UndefinedInstructionEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#1
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+SoftwareInterruptEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#2
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+PrefetchAbortEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#3
+ SUB LR,LR,#4
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+DataAbortEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#4
+ SUB LR,LR,#8
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+ReservedExceptionEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#5
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+IrqEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#6
+ SUB LR,LR,#4
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+FiqEntry
+ stmfd SP!,{R0-R1}
+ mov R0,#7
+ SUB LR,LR,#4
+ ldr R1,CommonExceptionEntry
+ bx R1
+
+CommonExceptionEntry
+ dcd 0x12345678
+
+ExceptionHandlersEnd
+
+AsmCommonExceptionEntry
+ mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
+ stmfd SP!,{R1} ; Store the IFAR
+
+ mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
+ stmfd SP!,{R1} ; Store the IFSR
+
+ mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
+ stmfd SP!,{R1} ; Store the DFAR
+
+ mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
+ stmfd SP!,{R1} ; Store the DFSR
+
+ mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
+ stmfd SP!,{R1} ; Store the SPSR
+
+ stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
+ stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
+ nop ; Required by ARM architecture
+ SUB SP,SP,#0x08 ; Adjust stack pointer
+ stmfd SP!,{R2-R12} ; Store general purpose registers
+
+ ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
+ ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
+ stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
+
+ mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
+
+ sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
+ blx CommonCExceptionHandler ; Call exception handler
+ add SP,SP,#4 ; Adjust SP back to where we were
+
+ ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
+ MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
+
+ ldmfd SP!,{R0-R12} ; Restore general purpose registers
+ ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
+ nop ; Required by ARM architecture
+ add SP,SP,#0x08 ; Adjust stack pointer
+ ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
+ add SP,SP,#0x1C ; Clear out the remaining stack space
+ movs PC,LR ; Return from exception
+
+ END
+
+
diff --git a/ArmPkg/Drivers/DebugSupportDxe/DebugSupport.c b/ArmPkg/Drivers/DebugSupportDxe/DebugSupport.c
new file mode 100644
index 0000000000..26f4c387dc
--- /dev/null
+++ b/ArmPkg/Drivers/DebugSupportDxe/DebugSupport.c
@@ -0,0 +1,119 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+EFI_STATUS
+EFIAPI
+DebugSupportGetMaximumProcessorIndex (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ OUT UINTN *MaxProcessorIndex
+ )
+{
+ if (MaxProcessorIndex == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *MaxProcessorIndex = 0;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+DebugSupportRegisterPeriodicCallback (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN EFI_PERIODIC_CALLBACK PeriodicCallback
+ )
+{
+ TIMER_DEBUG_SUPPORT_PROTOCOL *Timer;
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol(&gTimerDebugSupportProtocolGuid, NULL, (VOID **)&Timer);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = Timer->RegisterPeriodicCallback(Timer, PeriodicCallback);
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+DebugSupportRegisterExceptionCallback (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN EFI_EXCEPTION_CALLBACK ExceptionCallback,
+ IN EFI_EXCEPTION_TYPE ExceptionType
+ )
+{
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = Cpu->RegisterInterruptHandler(Cpu, ExceptionType, (EFI_CPU_INTERRUPT_HANDLER)ExceptionCallback);
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+DebugSupportInvalidateInstructionCache (
+ IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
+ IN UINTN ProcessorIndex,
+ IN VOID *Start,
+ IN UINT64 Length
+ )
+{
+ InvalidateInstructionCacheRange(Start, Length);
+ return EFI_SUCCESS;
+}
+
+EFI_DEBUG_SUPPORT_PROTOCOL mDebugSupport = {
+ IsaArm,
+ DebugSupportGetMaximumProcessorIndex,
+ DebugSupportRegisterPeriodicCallback,
+ DebugSupportRegisterExceptionCallback,
+ DebugSupportInvalidateInstructionCache
+};
+
+EFI_STATUS
+DebugSupportDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle = NULL;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiDebugSupportProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiDebugSupportProtocolGuid, &mDebugSupport, NULL);
+
+ return Status;
+}
+
diff --git a/ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf b/ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
new file mode 100644
index 0000000000..59f44879c4
--- /dev/null
+++ b/ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
@@ -0,0 +1,30 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmDebugSupportDxe
+ FILE_GUID = 2e7c151b-cbd8-4df6-a0e3-cde660067c6a
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = DebugSupportDxeInitialize
+
+[Sources.common]
+ DebugSupport.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ CacheMaintenanceLib
+ UefiDriverEntryPoint
+ ArmLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+ gEfiDebugSupportProtocolGuid
+ gTimerDebugSupportProtocolGuid
+
+[Depex]
+ TRUE
\ No newline at end of file
diff --git a/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
new file mode 100644
index 0000000000..0f1da65ba0
--- /dev/null
+++ b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
@@ -0,0 +1,526 @@
+/** @file
+ Support a Semi Host file system over a debuggers JTAG
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "SemihostFs.h"
+
+
+EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,
+ VolumeOpen
+};
+
+EFI_FILE gSemihostFsFile = {
+ EFI_FILE_PROTOCOL_REVISION,
+ FileOpen,
+ FileClose,
+ FileDelete,
+ FileRead,
+ FileWrite,
+ FileGetPosition,
+ FileSetPosition,
+ FileGetInfo,
+ FileSetInfo,
+ FileFlush
+};
+
+//
+// Device path for SemiHosting. It contains our autogened Caller ID GUID.
+//
+typedef struct {
+ VENDOR_DEVICE_PATH Guid;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} SEMIHOST_DEVICE_PATH;
+
+SEMIHOST_DEVICE_PATH gDevicePath = {
+ {
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
+ EFI_CALLER_ID_GUID
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
+};
+
+typedef struct {
+ LIST_ENTRY Link;
+ UINT64 Signature;
+ EFI_FILE File;
+ CHAR8 *FileName;
+ UINT32 Position;
+ UINT32 SemihostHandle;
+ BOOLEAN IsRoot;
+} SEMIHOST_FCB;
+
+#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )
+#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)
+#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);
+
+EFI_HANDLE gInstallHandle = NULL;
+LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);
+
+SEMIHOST_FCB *
+AllocateFCB (
+ VOID
+ )
+{
+ SEMIHOST_FCB *Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
+
+ if (Fcb != NULL) {
+ CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile));
+ Fcb->Signature = SEMIHOST_FCB_SIGNATURE;
+ }
+
+ return Fcb;
+}
+
+VOID
+FreeFCB (
+ IN SEMIHOST_FCB *Fcb
+ )
+{
+ // Remove Fcb from gFileList.
+ RemoveEntryList (&Fcb->Link);
+
+ // To help debugging...
+ Fcb->Signature = 0;
+
+ FreePool (Fcb);
+}
+
+
+
+EFI_STATUS
+VolumeOpen (
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
+ OUT EFI_FILE **Root
+ )
+{
+ SEMIHOST_FCB *RootFcb = NULL;
+
+ if (Root == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ RootFcb = AllocateFCB ();
+ if (RootFcb == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ RootFcb->IsRoot = TRUE;
+
+ InsertTailList (&gFileList, &RootFcb->Link);
+
+ *Root = &RootFcb->File;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+FileOpen (
+ IN EFI_FILE *File,
+ OUT EFI_FILE **NewHandle,
+ IN CHAR16 *FileName,
+ IN UINT64 OpenMode,
+ IN UINT64 Attributes
+ )
+{
+ SEMIHOST_FCB *FileFcb = NULL;
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 SemihostHandle;
+ CHAR8 *AsciiFileName;
+ CHAR8 *AsciiPtr;
+ UINTN Length;
+ UINT32 SemihostMode;
+ BOOLEAN IsRoot;
+
+ if ((FileName == NULL) || (NewHandle == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Semihost interface requires ASCII filesnames
+ Length = StrSize (FileName);
+
+ AsciiFileName = AllocatePool (Length);
+ if (AsciiFileName == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ AsciiPtr = AsciiFileName;
+
+ while (Length--) {
+ *AsciiPtr++ = *FileName++ & 0xFF;
+ }
+
+ if ((AsciiStrCmp (AsciiFileName, "\\") == 0) || (AsciiStrCmp (AsciiFileName, "/") == 0) || (AsciiStrCmp (AsciiFileName, "") == 0)) {
+ // Opening '/', '\', or the NULL pathname is trying to open the root directory
+ IsRoot = TRUE;
+
+ // Root directory node doesn't have a name.
+ FreePool (AsciiFileName);
+ AsciiFileName = NULL;
+ } else {
+ // Translate EFI_FILE_MODE into Semihosting mode
+ if (OpenMode & EFI_FILE_MODE_WRITE) {
+ SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY;
+ } else if (OpenMode & EFI_FILE_MODE_READ) {
+ SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+
+ // Add the creation flag if necessary
+ if (OpenMode & EFI_FILE_MODE_CREATE) {
+ SemihostMode |= SEMIHOST_FILE_MODE_CREATE;
+ }
+
+ // Call the semihosting interface to open the file.
+ Status = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ IsRoot = FALSE;
+ }
+
+ // Allocate a control block and fill it
+ FileFcb = AllocateFCB ();
+ if (FileFcb == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ FileFcb->FileName = AsciiFileName;
+ FileFcb->SemihostHandle = SemihostHandle;
+ FileFcb->Position = 0;
+ FileFcb->IsRoot = IsRoot;
+
+ InsertTailList (&gFileList, &FileFcb->Link);
+
+ *NewHandle = &FileFcb->File;
+
+ return Status;
+}
+
+
+EFI_STATUS
+FileClose (
+ IN EFI_FILE *File
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ if (Fcb->IsRoot == TRUE) {
+ FreeFCB (Fcb);
+ Status = EFI_SUCCESS;
+ } else {
+ Status = SemihostFileClose (Fcb->SemihostHandle);
+ if (!EFI_ERROR(Status)) {
+ FreePool (Fcb->FileName);
+ FreeFCB (Fcb);
+ }
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+FileDelete (
+ IN EFI_FILE *File
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+ EFI_STATUS Status;
+ CHAR8 *FileName;
+ UINTN NameSize;
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ // Get the filename from the Fcb
+ NameSize = AsciiStrLen (Fcb->FileName);
+ FileName = AllocatePool (NameSize + 1);
+
+ AsciiStrCpy (FileName, Fcb->FileName);
+
+ // Close the file if it's open. Disregard return status,
+ // since it might give an error if the file isn't open.
+ File->Close (File);
+
+ // Call the semihost interface to delete the file.
+ Status = SemihostFileRemove (FileName);
+
+ return Status;
+}
+
+EFI_STATUS
+FileRead (
+ IN EFI_FILE *File,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+ EFI_STATUS Status;
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ if (Fcb->IsRoot == TRUE) {
+ Status = EFI_UNSUPPORTED;
+ } else {
+ Status = SemihostFileRead (Fcb->SemihostHandle, BufferSize, Buffer);
+ if (!EFI_ERROR (Status)) {
+ Fcb->Position += *BufferSize;
+ }
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+FileWrite (
+ IN EFI_FILE *File,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+ EFI_STATUS Status;
+ UINTN WriteSize = *BufferSize;
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ Status = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);
+
+ if (!EFI_ERROR(Status)) {
+ // Semihost write return the number of bytes *NOT* written.
+ *BufferSize -= WriteSize;
+ Fcb->Position += *BufferSize;
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+FileGetPosition (
+ IN EFI_FILE *File,
+ OUT UINT64 *Position
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+
+ if (Position == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ *Position = Fcb->Position;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+FileSetPosition (
+ IN EFI_FILE *File,
+ IN UINT64 Position
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+ UINT32 Length;
+ EFI_STATUS Status;
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ Status = SemihostFileLength (Fcb->SemihostHandle, &Length);
+ if (!EFI_ERROR(Status) && (Length < Position)) {
+ Position = Length;
+ }
+
+ Status = SemihostFileSeek (Fcb->SemihostHandle, (UINT32)Position);
+ if (!EFI_ERROR(Status)) {
+ Fcb->Position = Position;
+ }
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+GetFileInfo (
+ IN SEMIHOST_FCB *Fcb,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ EFI_FILE_INFO *Info = NULL;
+ UINTN NameSize = 0;
+ UINTN ResultSize;
+ UINTN Index;
+ UINT32 Length;
+ EFI_STATUS Status;
+
+ if (Fcb->IsRoot == TRUE) {
+ ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
+ } else {
+ NameSize = AsciiStrLen (Fcb->FileName) + 1;
+ ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16);
+ }
+
+ if (*BufferSize < ResultSize) {
+ *BufferSize = ResultSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ Info = Buffer;
+
+ // Zero out the structure
+ ZeroMem (Info, SIZE_OF_EFI_FILE_INFO);
+
+ // Fill in the structure
+ Info->Size = ResultSize;
+
+ if (Fcb->IsRoot == TRUE) {
+ Info->Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;
+ Info->FileName[0] = L'\0';
+ } else {
+ Status = SemihostFileLength (Fcb->SemihostHandle, &Length);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Info->FileSize = Length;
+ Info->PhysicalSize = Length;
+
+ for (Index = 0; Index < NameSize; Index++) {
+ Info->FileName[Index] = Fcb->FileName[Index];
+ }
+ }
+
+
+ *BufferSize = ResultSize;
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+GetFilesystemInfo (
+ IN SEMIHOST_FCB *Fcb,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ EFI_FILE_SYSTEM_INFO *Info = NULL;
+ EFI_STATUS Status;
+ STATIC CHAR16 Label[] = L"SemihostFs";
+ UINTN ResultSize = SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize(Label);
+
+ if(*BufferSize >= ResultSize) {
+ ZeroMem (Buffer, ResultSize);
+ Status = EFI_SUCCESS;
+
+ Info = Buffer;
+
+ Info->Size = ResultSize;
+ Info->ReadOnly = FALSE;
+ Info->VolumeSize = 0;
+ Info->FreeSpace = 0;
+ Info->BlockSize = 0;
+
+ StrCpy (Info->VolumeLabel, Label);
+ } else {
+ Status = EFI_BUFFER_TOO_SMALL;
+ }
+
+ *BufferSize = ResultSize;
+ return Status;
+}
+
+EFI_STATUS
+FileGetInfo (
+ IN EFI_FILE *File,
+ IN EFI_GUID *InformationType,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ SEMIHOST_FCB *Fcb = NULL;
+ EFI_STATUS Status = EFI_UNSUPPORTED;
+
+ Fcb = SEMIHOST_FCB_FROM_THIS(File);
+
+ if (CompareGuid(InformationType, &gEfiFileSystemInfoGuid) != 0) {
+ Status = GetFilesystemInfo(Fcb, BufferSize, Buffer);
+ } else if (CompareGuid(InformationType, &gEfiFileInfoGuid) != 0) {
+ Status = GetFileInfo(Fcb, BufferSize, Buffer);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+FileSetInfo (
+ IN EFI_FILE *File,
+ IN EFI_GUID *InformationType,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+FileFlush (
+ IN EFI_FILE *File
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SemihostFsEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status = EFI_NOT_FOUND;
+
+ if (SemihostConnectionSupported ()) {
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &gInstallHandle,
+ &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs,
+ &gEfiDevicePathProtocolGuid, &gDevicePath,
+ NULL
+ );
+ }
+
+ return Status;
+}
+
diff --git a/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h
new file mode 100644
index 0000000000..f058d92e29
--- /dev/null
+++ b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h
@@ -0,0 +1,114 @@
+/** @file
+ Support a Semi Host file system over a debuggers JTAG
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SEMIHOST_FS_H__
+#define __SEMIHOST_FS_H__
+
+EFI_STATUS
+SemihostFsSupported(
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+EFI_STATUS
+SemihostFsStart(
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+EFI_STATUS
+SemihostFsStop(
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ );
+
+EFI_STATUS
+VolumeOpen(
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
+ OUT EFI_FILE **Root
+ );
+
+EFI_STATUS
+FileOpen(
+ IN EFI_FILE *File,
+ OUT EFI_FILE **NewHandle,
+ IN CHAR16 *FileName,
+ IN UINT64 OpenMode,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+FileClose(
+ IN EFI_FILE *File
+ );
+
+EFI_STATUS
+FileDelete(
+ IN EFI_FILE *File
+ );
+
+EFI_STATUS
+FileRead(
+ IN EFI_FILE *File,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ );
+
+EFI_STATUS
+FileWrite(
+ IN EFI_FILE *File,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
+ );
+
+EFI_STATUS
+FileGetPosition(
+ IN EFI_FILE *File,
+ OUT UINT64 *Position
+ );
+
+EFI_STATUS
+FileSetPosition(
+ IN EFI_FILE *File,
+ IN UINT64 Position
+ );
+
+EFI_STATUS
+FileGetInfo(
+ IN EFI_FILE *File,
+ IN EFI_GUID *InformationType,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ );
+
+EFI_STATUS
+FileSetInfo(
+ IN EFI_FILE *File,
+ IN EFI_GUID *InformationType,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ );
+
+EFI_STATUS
+FileFlush(
+ IN EFI_FILE *File
+ );
+
+#endif // __SEMIHOST_FS_H__
+
diff --git a/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf b/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
new file mode 100644
index 0000000000..7fca293d6f
--- /dev/null
+++ b/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
@@ -0,0 +1,48 @@
+#%HEADER%
+#/** @file
+# Support a Semi Host file system over a debuggers JTAG
+#
+# Copyright (c) 2009, Apple, Inc.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SemihostFs
+ FILE_GUID = C5B9C74A-6D72-4719-99AB-C59F199091EB
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = SemihostFsEntryPoint
+
+
+[Sources.ARM]
+ Arm/SemihostFs.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ MemoryAllocationLib
+ SemihostLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gEfiFileSystemInfoGuid
+ gEfiFileInfoGuid
+ gEfiFileSystemVolumeLabelInfoIdGuid
+
+[Protocols]
+ gEfiSimpleFileSystemProtocolGuid
+ gEfiDevicePathProtocolGuid
+
diff --git a/ArmPkg/Include/AsmMacroIoLib.h b/ArmPkg/Include/AsmMacroIoLib.h
new file mode 100644
index 0000000000..aa3ed61632
--- /dev/null
+++ b/ArmPkg/Include/AsmMacroIoLib.h
@@ -0,0 +1,236 @@
+/** @file
+ Macros to work around lack of Apple support for LDR register, =expr
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef __MACRO_IO_LIB_H__
+#define __MACRO_IO_LIB_H__
+
+#if defined(__APPLE__)
+
+//
+// ldr reg, =expr does not work with current Apple tool chain. So do the work our selves
+//
+
+// returns _Data in R0 and _Address in R1
+#define MmioWrite32(_Address, _Data) \
+ ldr r1, [pc, #8] ; \
+ ldr r0, [pc, #8] ; \
+ str r0, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+ .long (_Data) ; \
+1:
+
+// returns _Data in R0 and _Address in R1, and _OrData in r2
+#define MmioOr32(_Address, _OrData) \
+ ldr r1, [pc, #16] ; \
+ ldr r2, [pc, #16] ; \
+ ldr r0, [r1] ; \
+ orr r0, r0, r2 ; \
+ str r0, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+ .long (_OrData) ; \
+1:
+
+// returns _Data in R0 and _Address in R1, and _OrData in r2
+#define MmioAnd32(_Address, _AndData) \
+ ldr r1, [pc, #16] ; \
+ ldr r2, [pc, #16] ; \
+ ldr r0, [r1] ; \
+ and r0, r0, r2 ; \
+ str r0, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+ .long (_AndData) ; \
+1:
+
+// returns result in R0, _Address in R1, and _OrData in r2
+#define MmioAndThenOr32(_Address, _AndData, _OrData) \
+ ldr r1, [pc, #24] ; \
+ ldr r0, [r1] ; \
+ ldr r2, [pc, #20] ; \
+ and r0, r0, r2 ; \
+ ldr r2, [pc, #16] ; \
+ orr r0, r0, r2 ; \
+ str r0, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+ .long (_AndData) ; \
+ .long (_OrData) ; \
+1:
+
+// returns _Data in _Reg and _Address in R1
+#define MmioWriteFromReg32(_Address, _Reg) \
+ ldr r1, [pc, #4] ; \
+ str _Reg, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+1:
+
+
+// returns _Data in R0 and _Address in R1
+#define MmioRead32(_Address) \
+ ldr r1, [pc, #4] ; \
+ ldr r0, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+1:
+
+// returns _Data in Reg and _Address in R1
+#define MmioReadToReg32(_Address, _Reg) \
+ ldr r1, [pc, #4] ; \
+ ldr _Reg, [r1] ; \
+ b 1f ; \
+ .long (_Address) ; \
+1:
+
+
+// load R0 with _Data
+#define LoadConstant(_Data) \
+ ldr r0, [pc, #0] ; \
+ b 1f ; \
+ .long (_Data) ; \
+1:
+
+// load _Reg with _Data
+#define LoadConstantToReg(_Data, _Reg) \
+ ldr _Reg, [pc, #0] ; \
+ b 1f ; \
+ .long (_Data) ; \
+1:
+
+// load _Reg with _Data if eq
+#define LoadConstantToRegIfEq(_Data, _Reg) \
+ ldreq _Reg, [pc, #0] ; \
+ b 1f ; \
+ .long (_Data) ; \
+1:
+
+
+#elif defined (__GNUC__)
+
+#define MmioWrite32(Address, Data) \
+ ldr r1, =Address ; \
+ ldr r0, =Data ; \
+ str r0, [r1]
+
+#define MmioOr32(Address, OrData) \
+ ldr r1, =Address ; \
+ ldr r2, =OrData ; \
+ ldr r0, [r1] ; \
+ orr r0, r0, r2 ; \
+ str r0, [r1]
+
+#define MmioAnd32(Address, AndData) \
+ ldr r1, =Address ; \
+ ldr r2, =AndData ; \
+ ldr r0, [r1] ; \
+ and r0, r0, r2 ; \
+ str r0, [r1]
+
+#define MmioAndThenOr32(Address, AndData, OrData) \
+ ldr r1, =Address ; \
+ ldr r0, [r1] ; \
+ ldr r2, =AndData ; \
+ and r0, r0, r2 ; \
+ ldr r2, =OrData ; \
+ orr r0, r0, r2 ; \
+ str r0, [r1]
+
+#define MmioWriteFromReg32(Address, Reg) \
+ ldr r1, =Address ; \
+ str Reg, [r1]
+
+#define MmioRead32(Address) \
+ ldr r1, =Address ; \
+ ldr r0, [r1]
+
+#define MmioReadToReg32(Address, Reg) \
+ ldr r1, =Address ; \
+ ldr Reg, [r1]
+
+#define LoadConstant(Data) \
+ ldr r0, =Data
+
+#define LoadConstantToReg(Data, Reg) \
+ ldr Reg, =Data
+
+#else
+
+//
+// Use ARM assembly macros, form armasam
+//
+// Less magic in the macros if ldr reg, =expr works
+//
+
+// returns _Data in R0 and _Address in R1
+
+
+
+#define MmioWrite32(Address, Data) MmioWrite32Macro Address, Data
+
+
+
+
+// returns Data in R0 and Address in R1, and OrData in r2
+#define MmioOr32(Address, OrData) MmioOr32Macro Address, OrData
+
+
+// returns _Data in R0 and _Address in R1, and _OrData in r2
+
+
+#define MmioAnd32(Address, AndData) MmioAnd32Macro Address, AndData
+
+// returns result in R0, _Address in R1, and _OrData in r2
+
+
+#define MmioAndThenOr32(Address, AndData, OrData) MmioAndThenOr32Macro Address, AndData, OrData
+
+
+// returns _Data in _Reg and _Address in R1
+
+
+#define MmioWriteFromReg32(Address, Reg) MmioWriteFromReg32Macro Address, Reg
+
+// returns _Data in R0 and _Address in R1
+
+
+#define MmioRead32(Address) MmioRead32Macro Address
+
+// returns _Data in Reg and _Address in R1
+
+
+#define MmioReadToReg32(Address, Reg) MmioReadToReg32Macro Address, Reg
+
+
+// load R0 with _Data
+
+
+#define LoadConstant(Data) LoadConstantMacro Data
+
+// load _Reg with _Data
+
+
+#define LoadConstantToReg(Data, Reg) LoadConstantToRegMacro Data, Reg
+
+// conditional load testing eq flag
+#define LoadConstantToRegIfEq(Data, Reg) LoadConstantToRegIfEqMacro Data, Reg
+
+
+#endif
+
+
+#endif
diff --git a/ArmPkg/Include/AsmMacroIoLib.inc b/ArmPkg/Include/AsmMacroIoLib.inc
new file mode 100644
index 0000000000..23f3c44d6b
--- /dev/null
+++ b/ArmPkg/Include/AsmMacroIoLib.inc
@@ -0,0 +1,74 @@
+;%HEADER%
+;/** @file
+; Macros to work around lack of Apple support for LDR register, =expr
+;
+; Copyright (c) 2009, Apple, Inc. All rights reserved.
+;
+;**/
+
+
+ MACRO
+ MmioWrite32Macro $Address, $Data
+ ldr r1, = ($Address)
+ ldr r0, = ($Data)
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioOr32Macro $Address, $OrData
+ ldr r1, =($Address)
+ ldr r2, =($OrData)
+ ldr r0, [r1]
+ orr r0, r0, r2
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioAnd32Macro $Address, $AndData
+ ldr r1, =($Address)
+ ldr r2, =($AndData)
+ ldr r0, [r1]
+ and r0, r0, r2
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioAndThenOr32Macro $Address, $AndData, $OrData
+ ldr r1, =($Address)
+ ldr r0, [r1]
+ ldr r2, =($AndData)
+ and r0, r0, r2
+ ldr r2, =($OrData)
+ orr r0, r0, r2
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioWriteFromReg32Macro $Address, $Reg
+ ldr r1, =($Address)
+ str $Reg, [r1]
+ MEND
+
+ MACRO
+ MmioRead32Macro $Address
+ ldr r1, =($Address)
+ ldr r0, [r1]
+ MEND
+
+ MACRO
+ MmioReadToReg32Macro $Address, $Reg
+ ldr r1, =($Address)
+ ldr $Reg, [r1]
+ MEND
+
+ MACRO
+ LoadConstantMacro $Data
+ ldr r0, =($Data)
+ MEND
+
+ MACRO
+ LoadConstantToRegMacro $Data, $Reg
+ ldr $Reg, =($Data)
+ MEND
+
+ END
diff --git a/ArmPkg/Include/Chipset/ARM1176JZ-S.h b/ArmPkg/Include/Chipset/ARM1176JZ-S.h
new file mode 100644
index 0000000000..2331f8effc
--- /dev/null
+++ b/ArmPkg/Include/Chipset/ARM1176JZ-S.h
@@ -0,0 +1,111 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM1176JZ_S_H__
+#define __ARM1176JZ_S_H__
+
+// Domain Access Control Register
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
+
+#define TRANSLATION_TABLE_SIZE (16 * 1024)
+#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)
+#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
+
+// Translation table descriptor types
+#define TT_DESCRIPTOR_TYPE_MASK ((1UL << 18) | (3UL << 0))
+#define TT_DESCRIPTOR_TYPE_PAGE_TABLE ((0UL << 18) | (1UL << 0))
+#define TT_DESCRIPTOR_TYPE_SECTION ((0UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
+
+// Section descriptor definitions
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
+
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)
+
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
+
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
+
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
+
+#define TT_DESCRIPTOR_CACHE_POLICY_NON_CACHEABLE (0UL)
+#define TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_ALLOCATE (1UL)
+#define TT_DESCRIPTOR_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE (2UL)
+#define TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE (3UL)
+
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_MASK ((1UL << 14) | (3UL << 12))
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_NON_CACHEABLE ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_NON_CACHEABLE << 12))
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_ALLOCATE ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_ALLOCATE << 12))
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE << 12))
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE << 12))
+
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_MASK (3UL << 2)
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_NON_CACHEABLE (TT_DESCRIPTOR_CACHE_POLICY_NON_CACHEABLE << 2)
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_ALLOCATE (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_ALLOCATE << 2)
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE (TT_DESCRIPTOR_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE << 2)
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE << 2)
+
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK (TT_DESCRIPTOR_OUTER_CACHE_POLICY_MASK | TT_DESCRIPTOR_INNER_CACHE_POLICY_MASK)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC (TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE | TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC (TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE | TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE (TT_DESCRIPTOR_OUTER_CACHE_POLICY_NON_CACHEABLE | TT_DESCRIPTOR_INNER_CACHE_POLICY_NON_CACHEABLE)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC (TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_ALLOCATE | TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_ALLOCATE)
+
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
+
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
+
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
+#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
+
+#endif // __ARM1176JZ_S_H__
diff --git a/ArmPkg/Include/Chipset/ARM926EJ-S.h b/ArmPkg/Include/Chipset/ARM926EJ-S.h
new file mode 100644
index 0000000000..799d60c392
--- /dev/null
+++ b/ArmPkg/Include/Chipset/ARM926EJ-S.h
@@ -0,0 +1,71 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM926EJ_S_H__
+#define __ARM926EJ_S_H__
+
+// Domain Access Control Register
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
+
+#define TRANSLATION_TABLE_SIZE (16 * 1024)
+#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)
+#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
+
+// Translation table descriptor types
+#define TT_DESCRIPTOR_TYPE_MASK (3UL << 0)
+#define TT_DESCRIPTOR_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_TYPE_COARSE ((1UL << 0) | (1UL << 4))
+#define TT_DESCRIPTOR_TYPE_SECTION ((2UL << 0) | (1UL << 4))
+#define TT_DESCRIPTOR_TYPE_FINE ((3UL << 0) | (1UL << 4))
+
+// Section descriptor definitions
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
+
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK (3UL << 2)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED (0UL << 2)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_BUFFERED (1UL << 2)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH (2UL << 2)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK (3UL << 2)
+
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_MASK (3UL << 10)
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_NONE (1UL << 10)
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_ONLY (2UL << 10)
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE (3UL << 10)
+
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0xF) << 5)
+
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
+
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK | \
+ TT_DESCRIPTOR_TYPE_SECTION)
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH | \
+ TT_DESCRIPTOR_TYPE_SECTION)
+#define TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED | \
+ TT_DESCRIPTOR_TYPE_SECTION)
+
+#endif // __ARM926EJ_S_H__
diff --git a/ArmPkg/Include/Chipset/Cortex-A8.h b/ArmPkg/Include/Chipset/Cortex-A8.h
new file mode 100644
index 0000000000..75ce397a79
--- /dev/null
+++ b/ArmPkg/Include/Chipset/Cortex-A8.h
@@ -0,0 +1,104 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CORTEX_A8_H__
+#define __CORTEX_A8_H__
+
+// Domain Access Control Register
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
+
+#define TRANSLATION_TABLE_SIZE (16 * 1024)
+#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)
+#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
+
+// Translation table descriptor types
+#define TT_DESCRIPTOR_TYPE_MASK ((1UL << 18) | (3UL << 0))
+#define TT_DESCRIPTOR_TYPE_PAGE_TABLE ((0UL << 18) | (1UL << 0))
+#define TT_DESCRIPTOR_TYPE_SECTION ((0UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
+
+// Section descriptor definitions
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
+
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS_SECURE (0UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE (1UL << 19)
+
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
+
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
+
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
+
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
+
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
+
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
+#define TT_DESCRIPTOR_SECTION_DEVICE (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
+#define TT_DESCRIPTOR_SECTION_UNCACHED (TT_DESCRIPTOR_TYPE_SECTION | \
+ TT_DESCRIPTOR_SECTION_NS_NON_SECURE | \
+ TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
+ TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
+ TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
+ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
+ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
+
+#endif // __CORTEX_A8_H__
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
new file mode 100644
index 0000000000..d68b334e2a
--- /dev/null
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -0,0 +1,294 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_LIB__
+#define __ARM_LIB__
+
+typedef enum {
+ ARM_CACHE_TYPE_WRITE_BACK,
+ ARM_CACHE_TYPE_UNKNOWN
+} ARM_CACHE_TYPE;
+
+typedef enum {
+ ARM_CACHE_ARCHITECTURE_UNIFIED,
+ ARM_CACHE_ARCHITECTURE_SEPARATE,
+ ARM_CACHE_ARCHITECTURE_UNKNOWN
+} ARM_CACHE_ARCHITECTURE;
+
+typedef struct {
+ ARM_CACHE_TYPE Type;
+ ARM_CACHE_ARCHITECTURE Architecture;
+ BOOLEAN DataCachePresent;
+ UINTN DataCacheSize;
+ UINTN DataCacheAssociativity;
+ UINTN DataCacheLineLength;
+ BOOLEAN InstructionCachePresent;
+ UINTN InstructionCacheSize;
+ UINTN InstructionCacheAssociativity;
+ UINTN InstructionCacheLineLength;
+} ARM_CACHE_INFO;
+
+typedef enum {
+ ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
+ ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+} ARM_MEMORY_REGION_ATTRIBUTES;
+
+typedef struct {
+ UINT32 PhysicalBase;
+ UINT32 VirtualBase;
+ UINT32 Length;
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;
+} ARM_MEMORY_REGION_DESCRIPTOR;
+
+typedef VOID (*CACHE_OPERATION)(VOID);
+typedef VOID (*LINE_OPERATION)(UINTN);
+
+typedef enum {
+ ARM_PROCESSOR_MODE_USER = 0x10,
+ ARM_PROCESSOR_MODE_FIQ = 0x11,
+ ARM_PROCESSOR_MODE_IRQ = 0x12,
+ ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
+ ARM_PROCESSOR_MODE_ABORT = 0x17,
+ ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
+ ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
+ ARM_PROCESSOR_MODE_MASK = 0x1F
+} ARM_PROCESSOR_MODE;
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+ VOID
+ );
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCacheInformation (
+ OUT ARM_CACHE_INFO *CacheInfo
+ );
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDataCacheSize (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+ VOID
+ );
+
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+ VOID
+ );
+
+UINT32
+EFIAPI
+Cp15IdCode (
+ VOID
+ );
+
+UINT32
+EFIAPI
+Cp15CacheInfo (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateInstructionCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
+ );
+
+VOID
+EFIAPI
+ArmEnableDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableDataCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableInstructionCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableInstructionCache (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableMmu (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableMmu (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableInterrupts (
+ VOID
+ );
+
+UINTN
+EFIAPI
+ArmDisableInterrupts (
+ VOID
+ );
+
+BOOLEAN
+EFIAPI
+ArmGetInterruptState (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateTlb (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmSetDomainAccessControl (
+ IN UINT32 Domain
+ );
+
+VOID
+EFIAPI
+ArmSetTranslationTableBaseAddress (
+ IN VOID *TranslationTableBase
+ );
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ );
+
+VOID
+EFIAPI
+ArmSwitchProcessorMode (
+ IN ARM_PROCESSOR_MODE Mode
+ );
+
+ARM_PROCESSOR_MODE
+EFIAPI
+ArmProcessorMode (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmEnableBranchPrediction (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmDisableBranchPrediction (
+ VOID
+ );
+
+#endif // __ARM_LIB__
diff --git a/ArmPkg/Include/Library/SemihostLib.h b/ArmPkg/Include/Library/SemihostLib.h
new file mode 100644
index 0000000000..2c8b6ac7d8
--- /dev/null
+++ b/ArmPkg/Include/Library/SemihostLib.h
@@ -0,0 +1,100 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SEMIHOSTING_H__
+#define __SEMIHOSTING_H__
+
+/*
+ *
+ * Please refer to ARM RVDS 3.0 Compiler and Libraries Guide for more information
+ * about the semihosting interface.
+ *
+ */
+
+#define SEMIHOST_FILE_MODE_READ (0 << 2)
+#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
+#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
+#define SEMIHOST_FILE_MODE_CREATE (1 << 1)
+#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
+#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
+
+BOOLEAN
+SemihostConnectionSupported (
+ VOID
+ );
+
+EFI_STATUS
+SemihostFileOpen (
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINT32 *FileHandle
+ );
+
+EFI_STATUS
+SemihostFileSeek (
+ IN UINT32 FileHandle,
+ IN UINT32 Offset
+ );
+
+EFI_STATUS
+SemihostFileRead (
+ IN UINT32 FileHandle,
+ IN OUT UINT32 *Length,
+ OUT VOID *Buffer
+ );
+
+EFI_STATUS
+SemihostFileWrite (
+ IN UINT32 FileHandle,
+ IN OUT UINT32 *Length,
+ IN VOID *Buffer
+ );
+
+EFI_STATUS
+SemihostFileClose (
+ IN UINT32 FileHandle
+ );
+
+EFI_STATUS
+SemihostFileLength (
+ IN UINT32 FileHandle,
+ OUT UINT32 *Length
+ );
+
+EFI_STATUS
+SemihostFileRemove (
+ IN CHAR8 *FileName
+ );
+
+CHAR8
+SemihostReadCharacter (
+ VOID
+ );
+
+VOID
+SemihostWriteCharacter (
+ IN CHAR8 Character
+ );
+
+VOID
+SemihostWriteString (
+ IN CHAR8 *String
+ );
+
+UINT32
+SemihostSystem (
+ IN CHAR8 *CommandLine
+ );
+
+#endif // __SEMIHOSTING_H__
diff --git a/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h b/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
new file mode 100644
index 0000000000..8a65fcc586
--- /dev/null
+++ b/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
@@ -0,0 +1,665 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __UNCACHED_MEMORY_ALLOCATION_LIB_H__
+#define __UNCACHED_MEMORY_ALLOCATION_LIB_H__
+
+/**
+ Converts a cached or uncached address to a physical address suitable for use in SoC registers.
+
+ @param VirtualAddress The pointer to convert.
+
+ @return The physical address of the supplied virtual pointer.
+
+**/
+EFI_PHYSICAL_ADDRESS
+ConvertToPhysicalAddress (
+ IN VOID *VirtualAddress
+ );
+
+/**
+ Converts a cached or uncached address to a cached address.
+
+ @param Address The pointer to convert.
+
+ @return The address of the cached memory location corresponding to the input address.
+
+**/
+VOID *
+ConvertToCachedAddress (
+ IN VOID *Address
+ );
+
+/**
+ Converts a cached or uncached address to an uncached address.
+
+ @param Address The pointer to convert.
+
+ @return The address of the uncached memory location corresponding to the input address.
+
+**/
+VOID *
+ConvertToUncachedAddress (
+ IN VOID *Address
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiBootServicesData.
+
+ Allocates the number of 4KB pages of type EfiBootServicesData and returns a pointer to the
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is
+ returned.
+
+ @param Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocatePages (
+ IN UINTN Pages
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiRuntimeServicesData.
+
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is
+ returned.
+
+ @param Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimePages (
+ IN UINTN Pages
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiReservedMemoryType.
+
+ Allocates the number of 4KB pages of type EfiReservedMemoryType and returns a pointer to the
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is
+ returned.
+
+ @param Pages The number of 4 KB pages to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedPages (
+ IN UINTN Pages
+ );
+
+/**
+ Frees one or more 4KB pages that were previously allocated with one of the page allocation
+ functions in the Memory Allocation Library.
+
+ Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer
+ must have been allocated on a previous call to the page allocation services of the Memory
+ Allocation Library.
+ If Buffer was not allocated with a page allocation function in the Memory Allocation Library,
+ then ASSERT().
+ If Pages is zero, then ASSERT().
+
+ @param Buffer Pointer to the buffer of pages to free.
+ @param Pages The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreePages (
+ IN VOID *Buffer,
+ IN UINTN Pages
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment.
+
+ Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an
+ alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
+ returned. If there is not enough memory at the specified alignment remaining to satisfy the
+ request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param Pages The number of 4 KB pages to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedPages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiRuntimeServicesData at a specified alignment.
+
+ Allocates the number of 4KB pages specified by Pages of type EfiRuntimeServicesData with an
+ alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
+ returned. If there is not enough memory at the specified alignment remaining to satisfy the
+ request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param Pages The number of 4 KB pages to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates one or more 4KB pages of type EfiReservedMemoryType at a specified alignment.
+
+ Allocates the number of 4KB pages specified by Pages of type EfiReservedMemoryType with an
+ alignment specified by Alignment. The allocated buffer is returned. If Pages is 0, then NULL is
+ returned. If there is not enough memory at the specified alignment remaining to satisfy the
+ request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param Pages The number of 4 KB pages to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ );
+
+/**
+ Frees one or more 4KB pages that were previously allocated with one of the aligned page
+ allocation functions in the Memory Allocation Library.
+
+ Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer. Buffer
+ must have been allocated on a previous call to the aligned page allocation services of the Memory
+ Allocation Library.
+ If Buffer was not allocated with an aligned page allocation function in the Memory Allocation
+ Library, then ASSERT().
+ If Pages is zero, then ASSERT().
+
+ @param Buffer Pointer to the buffer of pages to free.
+ @param Pages The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreeAlignedPages (
+ IN VOID *Buffer,
+ IN UINTN Pages
+ );
+
+/**
+ Allocates a buffer of type EfiBootServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a
+ pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
+ returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocatePool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates a buffer of type EfiRuntimeServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData and returns
+ a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
+ returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimePool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates a buffer of type EfieservedMemoryType.
+
+ Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType and returns
+ a pointer to the allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is
+ returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiBootServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the
+ buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a
+ valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the
+ request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate and zero.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateZeroPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiRuntimeServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, clears the
+ buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a
+ valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the
+ request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate and zero.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimeZeroPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiReservedMemoryType.
+
+ Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, clears the
+ buffer with zeros, and returns a pointer to the allocated buffer. If AllocationSize is 0, then a
+ valid buffer of 0 size is returned. If there is not enough memory remaining to satisfy the
+ request, then NULL is returned.
+
+ @param AllocationSize The number of bytes to allocate and zero.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedZeroPool (
+ IN UINTN AllocationSize
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiBootServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, copies
+ AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory remaining to satisfy the request, then NULL is returned.
+ If Buffer is NULL, then ASSERT().
+ If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate and zero.
+ @param Buffer The buffer to copy to the allocated buffer.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiRuntimeServicesData.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, copies
+ AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory remaining to satisfy the request, then NULL is returned.
+ If Buffer is NULL, then ASSERT().
+ If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate and zero.
+ @param Buffer The buffer to copy to the allocated buffer.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimeCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiReservedMemoryType.
+
+ Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, copies
+ AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory remaining to satisfy the request, then NULL is returned.
+ If Buffer is NULL, then ASSERT().
+ If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate and zero.
+ @param Buffer The buffer to copy to the allocated buffer.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ );
+
+/**
+ Frees a buffer that was previously allocated with one of the pool allocation functions in the
+ Memory Allocation Library.
+
+ Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the
+ pool allocation services of the Memory Allocation Library.
+ If Buffer was not allocated with a pool allocation function in the Memory Allocation Library,
+ then ASSERT().
+
+ @param Buffer Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreePool (
+ IN VOID *Buffer
+ );
+
+/**
+ Allocates a buffer of type EfiBootServicesData at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
+ alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0,
+ then a valid buffer of 0 size is returned. If there is not enough memory at the specified
+ alignment remaining to satisfy the request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates a buffer of type EfiRuntimeServicesData at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an
+ alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0,
+ then a valid buffer of 0 size is returned. If there is not enough memory at the specified
+ alignment remaining to satisfy the request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates a buffer of type EfieservedMemoryType at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an
+ alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0,
+ then a valid buffer of 0 size is returned. If there is not enough memory at the specified
+ alignment remaining to satisfy the request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiBootServicesData at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
+ alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+ returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedZeroPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates and zeros a buffer of type EfiRuntimeServicesData at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an
+ alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+ returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeZeroPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ );
+
+/**
+ Allocates and zeros a buffer of type EfieservedMemoryType at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an
+ alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+ allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
+ is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+ returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedZeroPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiBootServicesData at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiBootServicesData type with an
+ alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0,
+ then a valid buffer of 0 size is returned. If there is not enough memory at the specified
+ alignment remaining to satisfy the request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Buffer The buffer to copy to the allocated buffer.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiRuntimeServicesData at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData type with an
+ alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0,
+ then a valid buffer of 0 size is returned. If there is not enough memory at the specified
+ alignment remaining to satisfy the request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Buffer The buffer to copy to the allocated buffer.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ );
+
+/**
+ Copies a buffer to an allocated buffer of type EfiReservedMemoryType at a specified alignment.
+
+ Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType type with an
+ alignment specified by Alignment. The allocated buffer is returned. If AllocationSize is 0,
+ then a valid buffer of 0 size is returned. If there is not enough memory at the specified
+ alignment remaining to satisfy the request, then NULL is returned.
+ If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+ @param AllocationSize The number of bytes to allocate.
+ @param Buffer The buffer to copy to the allocated buffer.
+ @param Alignment The requested alignment of the allocation. Must be a power of two.
+ If Alignment is zero, then byte alignment is used.
+
+ @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ );
+
+/**
+ Frees a buffer that was previously allocated with one of the aligned pool allocation functions
+ in the Memory Allocation Library.
+
+ Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the
+ aligned pool allocation services of the Memory Allocation Library.
+ If Buffer was not allocated with an aligned pool allocation function in the Memory Allocation
+ Library, then ASSERT().
+
+ @param Buffer Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreeAlignedPool (
+ IN VOID *Buffer
+ );
+
+VOID
+EFIAPI
+UncachedSafeFreePool (
+ IN VOID *Buffer
+ );
+
+#endif // __UNCACHED_MEMORY_ALLOCATION_LIB_H__
diff --git a/ArmPkg/Include/Protocol/TimerDebugSupport.h b/ArmPkg/Include/Protocol/TimerDebugSupport.h
new file mode 100644
index 0000000000..8ed9254176
--- /dev/null
+++ b/ArmPkg/Include/Protocol/TimerDebugSupport.h
@@ -0,0 +1,59 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __TIMERDEBUGSUPPORTPROTOCOL_H__
+#define __TIMERDEBUGSUPPORTPROTOCOL_H__
+
+//
+// Protocol GUID
+//
+#define TIMER_DEBUG_PROTOCOL_GUID { 0x68300561, 0x0197, 0x465d, { 0xb5, 0xa1, 0x28, 0xeb, 0xa1, 0x98, 0xdd, 0x0b } }
+
+
+
+//
+// Protocol interface structure
+//
+typedef struct _TIMER_DEBUG_SUPPORT_PROTOCOL TIMER_DEBUG_SUPPORT_PROTOCOL;
+
+
+typedef
+EFI_STATUS
+(EFIAPI *TIMER_DEBUG_SUPPORT_REGISTER_PERIODIC_CALLBACK) (
+ IN TIMER_DEBUG_SUPPORT_PROTOCOL *This,
+ IN EFI_PERIODIC_CALLBACK PeriodicCallback
+ )
+/*++
+
+Routine Description:
+ Register a periodic callback for debug support.
+
+Arguments:
+ This - pointer to protocol
+ PeriodicCallback - callback to be registered
+
+Returns:
+ EFI_SUCCESS - callback registered
+
+--*/
+;
+
+struct _TIMER_DEBUG_SUPPORT_PROTOCOL {
+ TIMER_DEBUG_SUPPORT_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
+};
+
+extern EFI_GUID gTimerDebugSupportProtocolGuid;
+
+#endif // __TIMERDEBUGSUPPORTPROTOCOL_H__
+
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
new file mode 100644
index 0000000000..7da6b42a92
--- /dev/null
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -0,0 +1,129 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include
+#include
+#include
+
+VOID
+CacheRangeOperation (
+ IN VOID *Start,
+ IN UINTN Length,
+ IN CACHE_OPERATION CacheOperation,
+ IN LINE_OPERATION LineOperation
+ )
+{
+ UINTN ArmCacheLineLength = ArmDataCacheLineLength();
+ UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
+ UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
+
+ if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
+ {
+ CacheOperation();
+ }
+ else
+ {
+ // Align address (rounding down)
+ UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+ UINTN EndAddress = (UINTN)Start + Length;
+
+ // Perform the line operation on an address in each cache line
+ while (AlignedAddress < EndAddress)
+ {
+ LineOperation(AlignedAddress);
+ AlignedAddress += ArmCacheLineLength;
+ }
+ }
+}
+
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ ArmCleanDataCache();
+ ArmInvalidateInstructionCache();
+}
+
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ ArmInvalidateDataCache();
+}
+
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
+ ArmInvalidateInstructionCache();
+ return Address;
+}
+
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ ArmCleanInvalidateDataCache();
+}
+
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
+ return Address;
+}
+
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ ArmCleanDataCache();
+}
+
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
+ return Address;
+}
+
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
+ return Address;
+}
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
new file mode 100644
index 0000000000..93b88f4ef0
--- /dev/null
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
@@ -0,0 +1,23 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmCacheMaintenanceLib
+ FILE_GUID = 1A20BE1F-33AD-450C-B49A-7123FCA8B7F9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CacheMaintenanceLib
+
+[Sources.common]
+ ArmCacheMaintenanceLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
+
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
new file mode 100644
index 0000000000..8042e4dd31
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
@@ -0,0 +1,32 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Arm11ArmLib
+ FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ Arm11Support.S | GCC
+ Arm11Support.asm | RVCT
+
+ Arm11Lib.c
+ ../Arm9/Arm9CacheInformation.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
new file mode 100644
index 0000000000..040179e445
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
@@ -0,0 +1,32 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Arm11ArmLib
+ FILE_GUID = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ Arm11Support.S | GCC
+ Arm11Support.asm | RVCT
+
+ Arm11Lib.c
+ ../Arm9/Arm9CacheInformation.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PrePiLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
new file mode 100644
index 0000000000..3736904954
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
@@ -0,0 +1,118 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+
+VOID
+FillTranslationTable (
+ IN UINT32 *TranslationTable,
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
+ )
+{
+ UINT32 *Entry;
+ UINTN Sections;
+ UINTN Index;
+ UINT32 Attributes;
+ UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
+
+ switch (MemoryRegion->Attributes) {
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ default:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
+ break;
+ }
+
+ Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
+
+ for (Index = 0; Index < Sections; Index++)
+ {
+ *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+ }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ )
+{
+ VOID *TranslationTable;
+
+ // Allocate pages for translation table.
+ TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+ TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableBase = TranslationTable;
+ }
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+ }
+
+ ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+ ArmInvalidateTlb();
+
+ ArmDisableDataCache();
+ ArmDisableInstructionCache();
+ ArmDisableMmu();
+
+ // Make sure nothing sneaked into the cache
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+
+ while (MemoryTable->Length != 0) {
+ FillTranslationTable(TranslationTable, MemoryTable);
+ MemoryTable++;
+ }
+
+ ArmSetTranslationTableBaseAddress(TranslationTable);
+
+ ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+ DOMAIN_ACCESS_CONTROL_NONE(14) |
+ DOMAIN_ACCESS_CONTROL_NONE(13) |
+ DOMAIN_ACCESS_CONTROL_NONE(12) |
+ DOMAIN_ACCESS_CONTROL_NONE(11) |
+ DOMAIN_ACCESS_CONTROL_NONE(10) |
+ DOMAIN_ACCESS_CONTROL_NONE( 9) |
+ DOMAIN_ACCESS_CONTROL_NONE( 8) |
+ DOMAIN_ACCESS_CONTROL_NONE( 7) |
+ DOMAIN_ACCESS_CONTROL_NONE( 6) |
+ DOMAIN_ACCESS_CONTROL_NONE( 5) |
+ DOMAIN_ACCESS_CONTROL_NONE( 4) |
+ DOMAIN_ACCESS_CONTROL_NONE( 3) |
+ DOMAIN_ACCESS_CONTROL_NONE( 2) |
+ DOMAIN_ACCESS_CONTROL_NONE( 1) |
+ DOMAIN_ACCESS_CONTROL_MANAGER(0));
+
+ ArmEnableInstructionCache();
+ ArmEnableDataCache();
+ ArmEnableMmu();
+}
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
new file mode 100644
index 0000000000..eec8f20b4e
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
@@ -0,0 +1,129 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmCleanInvalidateDataCache)
+.globl ASM_PFX(ArmCleanDataCache)
+.globl ASM_PFX(ArmInvalidateDataCache)
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCache):
+ mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCache):
+ mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
+ bx lr
+
+
+ASM_PFX(ArmInvalidateDataCache):
+ mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
+ bx lr
+
+
+ASM_PFX(ArmInvalidateInstructionCache):
+ mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
+ bx lr
+
+ASM_PFX(ArmEnableMmu):
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ASM_PFX(ArmDisableMmu):
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
+ bx LR
+
+ASM_PFX(ArmEnableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set I bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear I bit.
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
new file mode 100644
index 0000000000..e0be8f0c07
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
@@ -0,0 +1,133 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ArmCleanInvalidateDataCache
+ EXPORT ArmCleanDataCache
+ EXPORT ArmInvalidateDataCache
+ EXPORT ArmInvalidateInstructionCache
+ EXPORT ArmInvalidateDataCacheEntryByMVA
+ EXPORT ArmCleanDataCacheEntryByMVA
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA
+ EXPORT ArmEnableMmu
+ EXPORT ArmDisableMmu
+ EXPORT ArmEnableDataCache
+ EXPORT ArmDisableDataCache
+ EXPORT ArmEnableInstructionCache
+ EXPORT ArmDisableInstructionCache
+ EXPORT ArmEnableBranchPrediction
+ EXPORT ArmDisableBranchPrediction
+
+
+DC_ON EQU ( 0x1:SHL:2 )
+IC_ON EQU ( 0x1:SHL:12 )
+XP_ON EQU ( 0x1:SHL:23 )
+
+
+ AREA ArmCacheLib, CODE, READONLY
+ PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ bx lr
+
+
+ArmCleanDataCacheEntryByMVA
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ bx lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+ mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
+ bx lr
+
+
+ArmCleanDataCache
+ mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
+ bx lr
+
+
+ArmCleanInvalidateDataCache
+ mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
+ bx lr
+
+
+ArmInvalidateDataCache
+ mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
+ bx lr
+
+
+ArmInvalidateInstructionCache
+ mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
+ bx lr
+
+ArmEnableMmu
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ArmDisableMmu
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
+ bx LR
+
+ArmEnableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set I bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear I bit.
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ArmDisableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ END
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
new file mode 100644
index 0000000000..9a940394e2
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
@@ -0,0 +1,32 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Arm9ArmLib
+ FILE_GUID = 375D70D3-91E0-4374-A540-68BD959EB184
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ Arm9Support.S | GCC
+ Arm9Support.asm | RVCT
+
+ Arm9Lib.c
+ Arm9CacheInformation.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
new file mode 100755
index 0000000000..909ce27616
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
@@ -0,0 +1,32 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Arm9ArmLibPrePi
+ FILE_GUID = e9b6011f-ee15-4e59-ab8f-a819a081fa54
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ Arm9Support.S | GCC
+ Arm9Support.asm | RVCT
+
+ Arm9Lib.c
+ Arm9CacheInformation.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PrePiLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
new file mode 100644
index 0000000000..a8207b905f
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
@@ -0,0 +1,164 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include "ArmLibPrivate.h"
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+ VOID
+ )
+{
+ switch (CACHE_TYPE(Cp15CacheInfo()))
+ {
+ case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;
+ default: return ARM_CACHE_TYPE_UNKNOWN;
+ }
+}
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+ VOID
+ )
+{
+ switch (CACHE_ARCHITECTURE(Cp15CacheInfo()))
+ {
+ case CACHE_ARCHITECTURE_UNIFIED: return ARM_CACHE_ARCHITECTURE_UNIFIED;
+ case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;
+ default: return ARM_CACHE_ARCHITECTURE_UNKNOWN;
+ }
+}
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+ VOID
+ )
+{
+ switch (DATA_CACHE_PRESENT(Cp15CacheInfo()))
+ {
+ case CACHE_PRESENT: return TRUE;
+ case CACHE_NOT_PRESENT: return FALSE;
+ default: return FALSE;
+ }
+}
+
+UINTN
+EFIAPI
+ArmDataCacheSize (
+ VOID
+ )
+{
+ switch (DATA_CACHE_SIZE(Cp15CacheInfo()))
+ {
+ case CACHE_SIZE_4_KB: return 4 * 1024;
+ case CACHE_SIZE_8_KB: return 8 * 1024;
+ case CACHE_SIZE_16_KB: return 16 * 1024;
+ case CACHE_SIZE_32_KB: return 32 * 1024;
+ case CACHE_SIZE_64_KB: return 64 * 1024;
+ case CACHE_SIZE_128_KB: return 128 * 1024;
+ default: return 0;
+ }
+}
+
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+ VOID
+ )
+{
+ switch (DATA_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
+ {
+ case CACHE_ASSOCIATIVITY_4_WAY: return 4;
+ case CACHE_ASSOCIATIVITY_DIRECT: return 1;
+ default: return 0;
+ }
+}
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+ VOID
+ )
+{
+ switch (DATA_CACHE_LINE_LENGTH(Cp15CacheInfo()))
+ {
+ case CACHE_LINE_LENGTH_32_BYTES: return 32;
+ default: return 0;
+ }
+}
+
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+ VOID
+ )
+{
+ switch (INSTRUCTION_CACHE_PRESENT(Cp15CacheInfo()))
+ {
+ case CACHE_PRESENT: return TRUE;
+ case CACHE_NOT_PRESENT: return FALSE;
+ default: return FALSE;
+ }
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+ VOID
+ )
+{
+ switch (INSTRUCTION_CACHE_SIZE(Cp15CacheInfo()))
+ {
+ case CACHE_SIZE_4_KB: return 4 * 1024;
+ case CACHE_SIZE_8_KB: return 8 * 1024;
+ case CACHE_SIZE_16_KB: return 16 * 1024;
+ case CACHE_SIZE_32_KB: return 32 * 1024;
+ case CACHE_SIZE_64_KB: return 64 * 1024;
+ case CACHE_SIZE_128_KB: return 128 * 1024;
+ default: return 0;
+ }
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+ VOID
+ )
+{
+ switch (INSTRUCTION_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))
+ {
+ case CACHE_ASSOCIATIVITY_8_WAY: return 8;
+ case CACHE_ASSOCIATIVITY_4_WAY: return 4;
+ case CACHE_ASSOCIATIVITY_DIRECT: return 1;
+ default: return 0;
+ }
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+ VOID
+ )
+{
+ switch (INSTRUCTION_CACHE_LINE_LENGTH(Cp15CacheInfo()))
+ {
+ case CACHE_LINE_LENGTH_32_BYTES: return 32;
+ default: return 0;
+ }
+}
+
+
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c b/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
new file mode 100644
index 0000000000..0ba2237d29
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
@@ -0,0 +1,118 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+
+VOID
+FillTranslationTable (
+ IN UINT32 *TranslationTable,
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
+ )
+{
+ UINT32 *Entry;
+ UINTN Sections;
+ UINTN Index;
+ UINT32 Attributes;
+ UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
+
+ switch (MemoryRegion->Attributes) {
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ default:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
+ break;
+ }
+
+ Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
+
+ for (Index = 0; Index < Sections; Index++)
+ {
+ *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+ }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ )
+{
+ VOID *TranslationTable;
+
+ // Allocate pages for translation table.
+ TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+ TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableBase = TranslationTable;
+ }
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+ }
+
+ ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+ ArmInvalidateTlb();
+
+ ArmDisableDataCache();
+ ArmDisableInstructionCache();
+ ArmDisableMmu();
+
+ // Make sure nothing sneaked into the cache
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+
+ while (MemoryTable->Length != 0) {
+ FillTranslationTable(TranslationTable, MemoryTable);
+ MemoryTable++;
+ }
+
+ ArmSetTranslationTableBaseAddress(TranslationTable);
+
+ ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+ DOMAIN_ACCESS_CONTROL_NONE(14) |
+ DOMAIN_ACCESS_CONTROL_NONE(13) |
+ DOMAIN_ACCESS_CONTROL_NONE(12) |
+ DOMAIN_ACCESS_CONTROL_NONE(11) |
+ DOMAIN_ACCESS_CONTROL_NONE(10) |
+ DOMAIN_ACCESS_CONTROL_NONE( 9) |
+ DOMAIN_ACCESS_CONTROL_NONE( 8) |
+ DOMAIN_ACCESS_CONTROL_NONE( 7) |
+ DOMAIN_ACCESS_CONTROL_NONE( 6) |
+ DOMAIN_ACCESS_CONTROL_NONE( 5) |
+ DOMAIN_ACCESS_CONTROL_NONE( 4) |
+ DOMAIN_ACCESS_CONTROL_NONE( 3) |
+ DOMAIN_ACCESS_CONTROL_NONE( 2) |
+ DOMAIN_ACCESS_CONTROL_NONE( 1) |
+ DOMAIN_ACCESS_CONTROL_MANAGER(0));
+
+ ArmEnableInstructionCache();
+ ArmEnableDataCache();
+ ArmEnableMmu();
+}
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
new file mode 100644
index 0000000000..5c9afe9347
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
@@ -0,0 +1,128 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmCleanInvalidateDataCache)
+.globl ASM_PFX(ArmCleanDataCache)
+.globl ASM_PFX(ArmInvalidateDataCache)
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (1<<2)
+.set IC_ON, (1<<12)
+
+#------------------------------------------------------------------------------
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
+ bx lr
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
+ bx lr
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
+ bx lr
+
+ASM_PFX(ArmEnableInstructionCache):
+ ldr r1,=IC_ON
+ mrc p15,0,r0,c1,c0,0 @Read control register configuration data
+ orr r0,r0,r1 @Set I bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableInstructionCache):
+ ldr r1,=IC_ON
+ mrc p15,0,r0,c1,c0,0 @Read control register configuration data
+ bic r0,r0,r1 @Clear I bit.
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmInvalidateInstructionCache):
+ mov r0,#0
+ mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
+ @Also flushes the branch target cache.
+ mov r0,#0
+ mcr p15,0,r0,c7,c10,4 @Data write buffer
+ bx LR
+
+ASM_PFX(ArmEnableMmu):
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ASM_PFX(ArmDisableMmu):
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Drain write buffer
+ bx LR
+
+ASM_PFX(ArmEnableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmCleanDataCache):
+ mrc p15,0,r15,c7,c10,3
+ bne ASM_PFX(ArmCleanDataCache)
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Drain write buffer
+ bx LR
+
+ASM_PFX(ArmInvalidateDataCache):
+ mov R0,#0
+ mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Drain write buffer
+ bx LR
+
+ASM_PFX(ArmCleanInvalidateDataCache):
+ mrc p15,0,r15,c7,c14,3
+ bne ASM_PFX(ArmCleanInvalidateDataCache)
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Drain write buffer
+ bx LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+ bx LR @Branch prediction is not supported.
+
+ASM_PFX(ArmDisableBranchPrediction):
+ bx LR @Branch prediction is not supported.
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
new file mode 100644
index 0000000000..3204d6607f
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
@@ -0,0 +1,129 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ArmCleanInvalidateDataCache
+ EXPORT ArmCleanDataCache
+ EXPORT ArmInvalidateDataCache
+ EXPORT ArmInvalidateInstructionCache
+ EXPORT ArmInvalidateDataCacheEntryByMVA
+ EXPORT ArmCleanDataCacheEntryByMVA
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA
+ EXPORT ArmEnableMmu
+ EXPORT ArmDisableMmu
+ EXPORT ArmEnableDataCache
+ EXPORT ArmDisableDataCache
+ EXPORT ArmEnableInstructionCache
+ EXPORT ArmDisableInstructionCache
+ EXPORT ArmEnableBranchPrediction
+ EXPORT ArmDisableBranchPrediction
+
+
+DC_ON EQU ( 0x1:SHL:2 )
+IC_ON EQU ( 0x1:SHL:12 )
+
+ AREA ArmCacheLib, CODE, READONLY
+ PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ BX lr
+
+
+ArmCleanDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ BX lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
+ BX lr
+
+ArmEnableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set I bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear I bit.
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmInvalidateInstructionCache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c10,4 ;Drain write buffer
+ BX LR
+
+ArmEnableMmu
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ArmDisableMmu
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 ;Drain write buffer
+ bx LR
+
+ArmEnableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmCleanDataCache
+ MRC p15,0,r15,c7,c10,3
+ BNE ArmCleanDataCache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c10,4 ;Drain write buffer
+ BX LR
+
+ArmInvalidateDataCache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c10,4 ;Drain write buffer
+ BX LR
+
+ArmCleanInvalidateDataCache
+ MRC p15,0,r15,c7,c14,3
+ BNE ArmCleanInvalidateDataCache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c10,4 ;Drain write buffer
+ BX LR
+
+ArmEnableBranchPrediction
+ bx LR ;Branch prediction is not supported.
+
+ArmDisableBranchPrediction
+ bx LR ;Branch prediction is not supported.
+
+ END
diff --git a/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
new file mode 100644
index 0000000000..4dfa18db58
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
@@ -0,0 +1,288 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include "ArmCortexALib.h"
+
+VOID
+FillTranslationTable (
+ IN UINT32 *TranslationTable,
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
+ )
+{
+ UINT32 *Entry;
+ UINTN Sections;
+ UINTN Index;
+ UINT32 Attributes;
+ UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
+
+ switch (MemoryRegion->Attributes) {
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
+ break;
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ default:
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
+ break;
+ }
+
+ Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
+
+ for (Index = 0; Index < Sections; Index++)
+ {
+ *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+ }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
+ OUT VOID **TranslationTableBase OPTIONAL,
+ OUT UINTN *TranslationTableSize OPTIONAL
+ )
+{
+ VOID *TranslationTable;
+
+ // Allocate pages for translation table.
+ TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+ TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableBase = TranslationTable;
+ }
+
+ if (TranslationTableBase != NULL) {
+ *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+ }
+
+ ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+ ArmInvalidateTlb();
+
+ ArmDisableDataCache();
+ ArmDisableInstructionCache();
+ ArmDisableMmu();
+
+ // Make sure nothing sneaked into the cache
+ ArmCleanInvalidateDataCache();
+ ArmInvalidateInstructionCache();
+
+ while (MemoryTable->Length != 0) {
+ FillTranslationTable(TranslationTable, MemoryTable);
+ MemoryTable++;
+ }
+
+ ArmSetTranslationTableBaseAddress(TranslationTable);
+
+ ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+ DOMAIN_ACCESS_CONTROL_NONE(14) |
+ DOMAIN_ACCESS_CONTROL_NONE(13) |
+ DOMAIN_ACCESS_CONTROL_NONE(12) |
+ DOMAIN_ACCESS_CONTROL_NONE(11) |
+ DOMAIN_ACCESS_CONTROL_NONE(10) |
+ DOMAIN_ACCESS_CONTROL_NONE( 9) |
+ DOMAIN_ACCESS_CONTROL_NONE( 8) |
+ DOMAIN_ACCESS_CONTROL_NONE( 7) |
+ DOMAIN_ACCESS_CONTROL_NONE( 6) |
+ DOMAIN_ACCESS_CONTROL_NONE( 5) |
+ DOMAIN_ACCESS_CONTROL_NONE( 4) |
+ DOMAIN_ACCESS_CONTROL_NONE( 3) |
+ DOMAIN_ACCESS_CONTROL_NONE( 2) |
+ DOMAIN_ACCESS_CONTROL_NONE( 1) |
+ DOMAIN_ACCESS_CONTROL_MANAGER(0));
+
+ ArmEnableInstructionCache();
+ ArmEnableDataCache();
+ ArmEnableMmu();
+}
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+ VOID
+ )
+{
+ return ARM_CACHE_TYPE_WRITE_BACK;
+}
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+ VOID
+ )
+{
+ return ARM_CACHE_ARCHITECTURE_SEPARATE;
+}
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheSize (
+ VOID
+ )
+{
+ return 16 * 1024;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+ VOID
+ )
+{
+ return 4;
+}
+
+UINTN
+ArmDataCacheSets (
+ VOID
+ )
+{
+ return 64;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+ VOID
+ )
+{
+ return 64;
+}
+
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+ VOID
+ )
+{
+ return 16 * 1024;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+ VOID
+ )
+{
+ return 4;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+ VOID
+ )
+{
+ return 64;
+}
+
+VOID
+ArmCortexADataCacheOperation (
+ IN ARM_CORTEX_A_CACHE_OPERATION DataCacheOperation
+ )
+{
+ UINTN Set;
+ UINTN SetCount;
+ UINTN SetShift;
+ UINTN Way;
+ UINTN WayCount;
+ UINTN WayShift;
+ UINT32 SetWayFormat;
+ UINTN SavedInterruptState;
+
+ SetCount = ArmDataCacheSets();
+ WayCount = ArmDataCacheAssociativity();
+
+ // Cortex-A8 Manual, System Control Coprocessor chapter
+ SetShift = 6;
+ WayShift = 32 - LowBitSet32 ((UINT32)WayCount);
+
+ SavedInterruptState = ArmDisableInterrupts();
+
+ for (Way = 0; Way < WayCount; Way++) {
+ for (Set = 0; Set < SetCount; Set++) {
+ // Build the format that the CP15 instruction can understand
+ SetWayFormat = (Way << WayShift) | (Set << SetShift);
+
+ // Pass it through
+ (*DataCacheOperation)(SetWayFormat);
+ }
+ }
+
+ ArmDrainWriteBuffer();
+
+ if (SavedInterruptState) {
+ ArmEnableInterrupts();
+ }
+}
+
+VOID
+EFIAPI
+ArmInvalidateDataCache (
+ VOID
+ )
+{
+ ArmCortexADataCacheOperation(ArmInvalidateDataCacheEntryBySetWay);
+}
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+ VOID
+ )
+{
+ ArmCortexADataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay);
+}
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+ VOID
+ )
+{
+ ArmCortexADataCacheOperation(ArmCleanDataCacheEntryBySetWay);
+}
diff --git a/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h
new file mode 100644
index 0000000000..afe98bdfa2
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h
@@ -0,0 +1,45 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARMCORTEXALIB_H__
+#define __ARMCORTEXALIB_H__
+
+typedef VOID (*ARM_CORTEX_A_CACHE_OPERATION)(UINT32);
+
+VOID
+EFIAPI
+ArmDrainWriteBuffer (
+ VOID
+ );
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryBySetWay (
+ IN UINT32 SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryBySetWay (
+ IN UINT32 SetWayFormat
+ );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryBySetWay (
+ IN UINT32 SetWayFormat
+ );
+
+#endif // __ARMCORTEXALIB_H__
+
diff --git a/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S
new file mode 100644
index 0000000000..0e24f6341c
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S
@@ -0,0 +1,140 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmDrainWriteBuffer)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableExtendPTConfig)
+.globl ASM_PFX(ArmDisableExtendPTConfig)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+ mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
+ bx lr
+
+
+ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
+ bx lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
+ bx lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryBySetWay):
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line
+ bx lr
+
+
+ASM_PFX(ArmDrainWriteBuffer):
+ mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
+ bx lr
+
+
+ASM_PFX(ArmInvalidateInstructionCache):
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
+ bx LR
+
+ASM_PFX(ArmEnableMmu):
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ASM_PFX(ArmDisableMmu):
+ mov R0,#0
+ mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0 @Disable MMU
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 @Instruction synchronization barrier
+ bx LR
+
+ASM_PFX(ArmEnableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableDataCache):
+ ldr R1,=DC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear C bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ orr R0,R0,R1 @Set I bit
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmDisableInstructionCache):
+ ldr R1,=IC_ON
+ mrc p15,0,R0,c1,c0,0 @Read control register configuration data
+ bic R0,R0,R1 @Clear I bit.
+ mcr p15,0,r0,c1,c0,0 @Write control register configuration data
+ bx LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm
new file mode 100644
index 0000000000..dbd8bd246a
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm
@@ -0,0 +1,141 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT ArmInvalidateInstructionCache
+ EXPORT ArmInvalidateDataCacheEntryByMVA
+ EXPORT ArmCleanDataCacheEntryByMVA
+ EXPORT ArmCleanInvalidateDataCacheEntryByMVA
+ EXPORT ArmInvalidateDataCacheEntryBySetWay
+ EXPORT ArmCleanDataCacheEntryBySetWay
+ EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
+ EXPORT ArmDrainWriteBuffer
+ EXPORT ArmEnableMmu
+ EXPORT ArmDisableMmu
+ EXPORT ArmEnableDataCache
+ EXPORT ArmDisableDataCache
+ EXPORT ArmEnableInstructionCache
+ EXPORT ArmDisableInstructionCache
+ EXPORT ArmEnableBranchPrediction
+ EXPORT ArmDisableBranchPrediction
+
+DC_ON EQU ( 0x1:SHL:2 )
+IC_ON EQU ( 0x1:SHL:12 )
+XP_ON EQU ( 0x1:SHL:23 )
+
+
+ AREA ArmCacheLib, CODE, READONLY
+ PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ BX lr
+
+
+ArmCleanDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ BX lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+ MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
+ BX lr
+
+
+ArmInvalidateDataCacheEntryBySetWay
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
+ bx lr
+
+
+ArmCleanInvalidateDataCacheEntryBySetWay
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
+ bx lr
+
+
+ArmCleanDataCacheEntryBySetWay
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line
+ bx lr
+
+
+ArmDrainWriteBuffer
+ mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
+ bx lr
+
+
+ArmInvalidateInstructionCache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
+ MOV R0,#0
+ MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
+ BX LR
+
+ArmEnableMmu
+ mrc p15,0,R0,c1,c0,0
+ orr R0,R0,#1
+ mcr p15,0,R0,c1,c0,0
+ bx LR
+
+ArmDisableMmu
+ mov R0,#0
+ mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
+ mrc p15,0,R0,c1,c0,0
+ bic R0,R0,#1
+ mcr p15,0,R0,c1,c0,0 ;Disable MMU
+ mov R0,#0
+ mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
+ mov R0,#0
+ mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
+ bx LR
+
+ArmEnableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableDataCache
+ LDR R1,=DC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear C bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ ORR R0,R0,R1 ;Set I bit
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmDisableInstructionCache
+ LDR R1,=IC_ON
+ MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
+ BIC R0,R0,R1 ;Clear I bit.
+ MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
+ BX LR
+
+ArmEnableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ArmDisableBranchPrediction
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00000800
+ mcr p15, 0, r0, c1, c0, 0
+ bx LR
+
+ END
diff --git a/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
new file mode 100644
index 0000000000..54b77e31b4
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
@@ -0,0 +1,31 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmCortexArmLib
+ FILE_GUID = 411cdfd8-f964-4b9d-a3e3-1719a9c15559
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ ArmCortexASupport.S | GCC
+ ArmCortexASupport.asm | RVCT
+
+ ArmCortexALib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
new file mode 100644
index 0000000000..450dfe5936
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
@@ -0,0 +1,31 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmCortexArmLibPrePi
+ FILE_GUID = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ ArmCortexASupport.S | GCC
+ ArmCortexASupport.asm | RVCT
+
+ ArmCortexALib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ PrePiLib
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLib.c b/ArmPkg/Library/ArmLib/Common/ArmLib.c
new file mode 100644
index 0000000000..b015dc4aa1
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Common/ArmLib.c
@@ -0,0 +1,60 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+
+#include "ArmLibPrivate.h"
+
+VOID
+EFIAPI
+ArmCacheInformation (
+ OUT ARM_CACHE_INFO *CacheInfo
+ )
+{
+ if (CacheInfo != NULL) {
+ CacheInfo->Type = ArmCacheType();
+ CacheInfo->Architecture = ArmCacheArchitecture();
+ CacheInfo->DataCachePresent = ArmDataCachePresent();
+ CacheInfo->DataCacheSize = ArmDataCacheSize();
+ CacheInfo->DataCacheAssociativity = ArmDataCacheAssociativity();
+ CacheInfo->DataCacheLineLength = ArmDataCacheLineLength();
+ CacheInfo->InstructionCachePresent = ArmInstructionCachePresent();
+ CacheInfo->InstructionCacheSize = ArmInstructionCacheSize();
+ CacheInfo->InstructionCacheAssociativity = ArmInstructionCacheAssociativity();
+ CacheInfo->InstructionCacheLineLength = ArmInstructionCacheLineLength();
+ }
+}
+
+VOID
+EFIAPI
+ArmSwitchProcessorMode (
+ IN ARM_PROCESSOR_MODE Mode
+ )
+{
+ CPSRMaskInsert(ARM_PROCESSOR_MODE_MASK, Mode);
+}
+
+
+ARM_PROCESSOR_MODE
+EFIAPI
+ArmProcessorMode (
+ VOID
+ )
+{
+ return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);
+}
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
new file mode 100644
index 0000000000..d1d2523947
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
@@ -0,0 +1,70 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_LIB_PRIVATE_H__
+#define __ARM_LIB_PRIVATE_H__
+
+#define CACHE_SIZE_4_KB (3UL)
+#define CACHE_SIZE_8_KB (4UL)
+#define CACHE_SIZE_16_KB (5UL)
+#define CACHE_SIZE_32_KB (6UL)
+#define CACHE_SIZE_64_KB (7UL)
+#define CACHE_SIZE_128_KB (8UL)
+
+#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
+#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
+#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
+
+#define CACHE_PRESENT (0UL)
+#define CACHE_NOT_PRESENT (1UL)
+
+#define CACHE_LINE_LENGTH_32_BYTES (2UL)
+
+#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)
+#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)
+#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
+#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
+
+#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
+#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
+
+#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
+
+#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+
+#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
+#define CACHE_TYPE_WRITE_BACK (0x0EUL)
+
+#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
+#define CACHE_ARCHITECTURE_UNIFIED (0UL)
+#define CACHE_ARCHITECTURE_SEPARATE (1UL)
+
+VOID
+CPSRMaskInsert (
+ IN UINT32 Mask,
+ IN UINT32 Value
+ );
+
+UINT32
+CPSRRead (
+ VOID
+ );
+
+#endif // __ARM_LIB_PRIVATE_H__
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
new file mode 100644
index 0000000000..d80100c788
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
@@ -0,0 +1,89 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(Cp15IdCode)
+.globl ASM_PFX(Cp15CacheInfo)
+.globl ASM_PFX(ArmEnableInterrupts)
+.globl ASM_PFX(ArmDisableInterrupts)
+.globl ASM_PFX(ArmGetInterruptState)
+.globl ASM_PFX(ArmInvalidateTlb)
+.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
+.globl ASM_PFX(ArmSetDomainAccessControl)
+.globl ASM_PFX(CPSRMaskInsert)
+.globl ASM_PFX(CPSRRead)
+
+#------------------------------------------------------------------------------
+
+ASM_PFX(Cp15IdCode):
+ mrc p15,0,R0,c0,c0,0
+ bx LR
+
+ASM_PFX(Cp15CacheInfo):
+ mrc p15,0,R0,c0,c0,1
+ bx LR
+
+ASM_PFX(ArmEnableInterrupts):
+ mrs R0,CPSR
+ bic R0,R0,#0x80 @Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
+
+ASM_PFX(ArmDisableInterrupts):
+ mrs R0,CPSR
+ orr R1,R0,#0x80 @Disable IRQ interrupts
+ msr CPSR_c,R1
+ tst R0,#0x80
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ASM_PFX(ArmGetInterruptState):
+ mrs R0,CPSR
+ tst R0,#0x80 @Check if IRQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ASM_PFX(ArmInvalidateTlb):
+ mov r0,#0
+ mcr p15,0,r0,c8,c7,0
+ bx lr
+
+ASM_PFX(ArmSetTranslationTableBaseAddress):
+ mcr p15,0,r0,c2,c0,0
+ bx lr
+
+ASM_PFX(ArmSetDomainAccessControl):
+ mcr p15,0,r0,c3,c0,0
+ bx lr
+
+ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
+ stmfd sp!, {r4-r12, lr} @ save all the banked registers
+ mov r3, sp @ copy the stack pointer into a non-banked register
+ mrs r2, cpsr @ read the cpsr
+ bic r2, r2, r0 @ clear mask in the cpsr
+ and r1, r1, r0 @ clear bits outside the mask in the input
+ orr r2, r2, r1 @ set field
+ msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
+ mov sp, r3 @ restore stack pointer
+ ldmfd sp!, {r4-r12, lr} @ restore registers
+ bx lr @ return (hopefully thumb-safe!)
+
+ASM_PFX(CPSRRead):
+ mrs r0, cpsr
+ bx lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
new file mode 100644
index 0000000000..ec7db638af
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -0,0 +1,90 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT Cp15IdCode
+ EXPORT Cp15CacheInfo
+ EXPORT ArmEnableInterrupts
+ EXPORT ArmDisableInterrupts
+ EXPORT ArmGetInterruptState
+ EXPORT ArmInvalidateTlb
+ EXPORT ArmSetTranslationTableBaseAddress
+ EXPORT ArmSetDomainAccessControl
+ EXPORT CPSRMaskInsert
+ EXPORT CPSRRead
+
+ AREA ArmLibSupport, CODE, READONLY
+
+Cp15IdCode
+ mrc p15,0,R0,c0,c0,0
+ bx LR
+
+Cp15CacheInfo
+ mrc p15,0,R0,c0,c0,1
+ bx LR
+
+ArmEnableInterrupts
+ mrs R0,CPSR
+ bic R0,R0,#0x80 ;Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
+
+ArmDisableInterrupts
+ mrs R0,CPSR
+ orr R1,R0,#0x80 ;Disable IRQ interrupts
+ msr CPSR_c,R1
+ tst R0,#0x80
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ArmGetInterruptState
+ mrs R0,CPSR
+ tst R0,#0x80 ;Check if IRQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
+
+ArmInvalidateTlb
+ mov r0,#0
+ mcr p15,0,r0,c8,c7,0
+ bx lr
+
+ArmSetTranslationTableBaseAddress
+ mcr p15,0,r0,c2,c0,0
+ bx lr
+
+ArmSetDomainAccessControl
+ mcr p15,0,r0,c3,c0,0
+ bx lr
+
+CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
+ stmfd sp!, {r4-r12, lr} ; save all the banked registers
+ mov r3, sp ; copy the stack pointer into a non-banked register
+ mrs r2, cpsr ; read the cpsr
+ bic r2, r2, r0 ; clear mask in the cpsr
+ and r1, r1, r0 ; clear bits outside the mask in the input
+ orr r2, r2, r1 ; set field
+ msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
+ mov sp, r3 ; restore stack pointer
+ ldmfd sp!, {r4-r12, lr} ; restore registers
+ bx lr ; return (hopefully thumb-safe!)
+
+CPSRRead
+ mrs r0, cpsr
+ bx lr
+
+ END
+
+
diff --git a/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c b/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
new file mode 100644
index 0000000000..08a1ad0c5f
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
@@ -0,0 +1,106 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include "ArmLibPrivate.h"
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+ VOID
+ )
+{
+ return ARM_CACHE_TYPE_UNKNOWN;
+}
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+ VOID
+ )
+{
+ return ARM_CACHE_ARCHITECTURE_UNKNOWN;
+}
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheSize (
+ VOID
+ )
+{
+ return 0;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+ VOID
+ )
+{
+ return 0;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+ VOID
+ )
+{
+ return 0;
+}
+
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+ VOID
+ )
+{
+ return 0;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+ VOID
+ )
+{
+ return 0;
+}
+
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+ VOID
+ )
+{
+ return 0;
+}
diff --git a/ArmPkg/Library/ArmLib/Null/NullArmLib.c b/ArmPkg/Library/ArmLib/Null/NullArmLib.c
new file mode 100644
index 0000000000..6e95cba706
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Null/NullArmLib.c
@@ -0,0 +1,117 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmInvalidateInstructionCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryByMVA (
+ IN UINTN Address
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryByMVA (
+ IN UINTN Address
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmEnableDataCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmDisableDataCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmEnableInstructionCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
+
+VOID
+EFIAPI
+ArmDisableInstructionCache (
+ VOID
+ )
+{
+ // Do not run code using the Null cache library.
+ ASSERT(FALSE);
+}
diff --git a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
new file mode 100644
index 0000000000..ff31b9cecb
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
@@ -0,0 +1,26 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NullArmLib
+ FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmLib
+
+[Sources.common]
+ ../Common/ArmLibSupport.S | GCC
+ ../Common/ArmLibSupport.asm | RVCT
+ ../Common/ArmLib.c
+
+ NullArmLib.c
+ NullArmCacheInformation.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h
new file mode 100644
index 0000000000..e2c00a2033
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h
@@ -0,0 +1,83 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+#include
+#include
+
+#define CHAR_BIT 8
+
+typedef union {
+ INT64 all;
+ struct {
+ UINT32 low;
+ INT32 high;
+ };
+} dwords;
+
+typedef union {
+ UINT64 all;
+ struct {
+ UINT32 low;
+ UINT32 high;
+ };
+} udwords;
+
+#if __GNUC__
+ #define COUNT_LEADING_ZEROS(_a) __builtin_clz((_a))
+ #define COUNT_TRAILING_ZEROS(_a) __builtin_ctz((_a))
+#else
+#error COUNT_LEADING_ZEROS() and COUNT_TRAILING_ZEROS() macros not ported to your compiler
+#endif
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
new file mode 100644
index 0000000000..ac2bdbafd0
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___ashldi3
+___ashldi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ @ link register save eliminated.
+ cmp r2, #31
+ @ lr needed for prologue
+ bls L2
+ cmp r2, #63
+ subls r2, r2, #32
+ movls r2, r0, asl r2
+ movhi r2, #0
+ mov r1, r2
+ mov r0, #0
+ bx lr
+L2:
+ cmp r2, #0
+ rsbne r3, r2, #32
+ movne r3, r0, lsr r3
+ movne r0, r0, asl r2
+ orrne r1, r3, r1, asl r2
+ bx lr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c
new file mode 100644
index 0000000000..f708737035
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c
@@ -0,0 +1,83 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+#include "Llvm_int_lib.h"
+
+// Returns: a << b
+
+// Precondition: 0 <= b < bits_in_dword
+
+INT64
+__ashldi3(INT64 a, INT32 b)
+{
+ const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
+ dwords input;
+ dwords result;
+ input.all = a;
+ if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
+ {
+ result.low = 0;
+ result.high = input.low << (b - bits_in_word);
+ }
+ else // 0 <= b < bits_in_word
+ {
+ if (b == 0)
+ return a;
+ result.low = input.low << b;
+ result.high = (input.high << b) | (input.low >> (bits_in_word - b));
+ }
+ return result.all;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
new file mode 100644
index 0000000000..fb87c88a09
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___ashrdi3
+___ashrdi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ @ link register save eliminated.
+ cmp r2, #31
+ @ lr needed for prologue
+ bls L2
+ cmp r2, #63
+ subls r2, r2, #32
+ mov ip, r1, asr #31
+ movls r2, r1, asr r2
+ movhi r2, ip
+ mov r0, r2
+ mov r1, ip
+ bx lr
+L2:
+ cmp r2, #0
+ rsbne r3, r2, #32
+ movne r3, r1, asl r3
+ movne r1, r1, asr r2
+ orrne r0, r3, r0, lsr r2
+ bx lr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c
new file mode 100644
index 0000000000..ce5134eb64
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c
@@ -0,0 +1,84 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+#include "Llvm_int_lib.h"
+
+// Returns: arithmetic a >> b
+
+// Precondition: 0 <= b < bits_in_dword
+
+INT64
+__ashrdi3(INT64 a, INT32 b)
+{
+ const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
+ dwords input;
+ dwords result;
+ input.all = a;
+ if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
+ {
+ // result.high = input.high < 0 ? -1 : 0
+ result.high = input.high >> (bits_in_word - 1);
+ result.low = input.high >> (b - bits_in_word);
+ }
+ else // 0 <= b < bits_in_word
+ {
+ if (b == 0)
+ return a;
+ result.high = input.high >> b;
+ result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
+ }
+ return result.all;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c
new file mode 100644
index 0000000000..c7b4607ca4
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c
@@ -0,0 +1,96 @@
+/** @file
+ Compiler intrinsic to return the number of leading zeros, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+// Returns: the number of leading 0-bits
+
+// Precondition: a != 0
+
+INT32
+__clzsi2(INT32 a)
+{
+ UINT32 x = (UINT32)a;
+ INT32 t = ((x & 0xFFFF0000) == 0) << 4; // if (x is small) t = 16 else 0
+ x >>= 16 - t; // x = [0 - 0xFFFF]
+ UINT32 r = t; // r = [0, 16]
+ // return r + clz(x)
+ t = ((x & 0xFF00) == 0) << 3;
+ x >>= 8 - t; // x = [0 - 0xFF]
+ r += t; // r = [0, 8, 16, 24]
+ // return r + clz(x)
+ t = ((x & 0xF0) == 0) << 2;
+ x >>= 4 - t; // x = [0 - 0xF]
+ r += t; // r = [0, 4, 8, 12, 16, 20, 24, 28]
+ // return r + clz(x)
+ t = ((x & 0xC) == 0) << 1;
+ x >>= 2 - t; // x = [0 - 3]
+ r += t; // r = [0 - 30] and is even
+ // return r + clz(x)
+// switch (x)
+// {
+// case 0:
+// return r + 2;
+// case 1:
+// return r + 1;
+// case 2:
+// case 3:
+// return r;
+// }
+ return r + ((2 - x) & -((x & 2) == 0));
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c
new file mode 100644
index 0000000000..c0e18977ec
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c
@@ -0,0 +1,111 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/** @file
+ Compiler intrinsic to return the number of trailing zeros, ported from LLVM code.
+
+ Copyright (c) 2008, Apple, Inc.
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+// Returns: the number of trailing 0-bits
+
+// Precondition: a != 0
+
+INT32
+__ctzsi2(INT32 a)
+{
+ UINT32 x = (UINT32)a;
+ INT32 t = ((x & 0x0000FFFF) == 0) << 4; // if (x has no small bits) t = 16 else 0
+ x >>= t; // x = [0 - 0xFFFF] + higher garbage bits
+ UINT32 r = t; // r = [0, 16]
+ // return r + ctz(x)
+ t = ((x & 0x00FF) == 0) << 3;
+ x >>= t; // x = [0 - 0xFF] + higher garbage bits
+ r += t; // r = [0, 8, 16, 24]
+ // return r + ctz(x)
+ t = ((x & 0x0F) == 0) << 2;
+ x >>= t; // x = [0 - 0xF] + higher garbage bits
+ r += t; // r = [0, 4, 8, 12, 16, 20, 24, 28]
+ // return r + ctz(x)
+ t = ((x & 0x3) == 0) << 1;
+ x >>= t;
+ x &= 3; // x = [0 - 3]
+ r += t; // r = [0 - 30] and is even
+ // return r + ctz(x)
+// The branch-less return statement below is equivalent
+// to the following switch statement:
+// switch (x)
+// {
+// case 0:
+// return r + 2;
+// case 2:
+// return r + 1;
+// case 1:
+// case 3:
+// return r;
+// }
+ return r + ((2 - (x >> 1)) & -((x & 1) == 0));
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm
new file mode 100644
index 0000000000..f6f9bc2d56
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm
@@ -0,0 +1,155 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_uidiv
+ EXPORT __aeabi_uidivmod
+ EXPORT __aeabi_idiv
+ EXPORT __aeabi_idivmod
+
+ AREA Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uidivmode (
+; IN UINT32 Dividen
+; IN UINT32 Divisor
+; );
+;
+
+__aeabi_uidiv
+__aeabi_uidivmod
+ RSBS r12, r1, r0, LSR #4
+ MOV r2, #0
+ BCC __arm_div4
+ RSBS r12, r1, r0, LSR #8
+ BCC __arm_div8
+ MOV r3, #0
+ B __arm_div_large
+
+;
+;INT32
+;EFIAPI
+;__aeabi_idivmode (
+; IN INT32 Dividen
+; IN INT32 Divisor
+; );
+;
+__aeabi_idiv
+__aeabi_idivmod
+ ORRS r12, r0, r1
+ BMI __arm_div_negative
+ RSBS r12, r1, r0, LSR #1
+ MOV r2, #0
+ BCC __arm_div1
+ RSBS r12, r1, r0, LSR #4
+ BCC __arm_div4
+ RSBS r12, r1, r0, LSR #8
+ BCC __arm_div8
+ MOV r3, #0
+ B __arm_div_large
+__arm_div8
+ RSBS r12, r1, r0, LSR #7
+ SUBCS r0, r0, r1, LSL #7
+ ADC r2, r2, r2
+ RSBS r12, r1, r0,LSR #6
+ SUBCS r0, r0, r1, LSL #6
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #5
+ SUBCS r0, r0, r1, LSL #5
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #4
+ SUBCS r0, r0, r1, LSL #4
+ ADC r2, r2, r2
+__arm_div4
+ RSBS r12, r1, r0, LSR #3
+ SUBCS r0, r0, r1, LSL #3
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #2
+ SUBCS r0, r0, r1, LSL #2
+ ADCS r2, r2, r2
+ RSBS r12, r1, r0, LSR #1
+ SUBCS r0, r0, r1, LSL #1
+ ADC r2, r2, r2
+__arm_div1
+ SUBS r1, r0, r1
+ MOVCC r1, r0
+ ADC r0, r2, r2
+ BX r14
+__arm_div_negative
+ ANDS r2, r1, #0x80000000
+ RSBMI r1, r1, #0
+ EORS r3, r2, r0, ASR #32
+ RSBCS r0, r0, #0
+ RSBS r12, r1, r0, LSR #4
+ BCC label1
+ RSBS r12, r1, r0, LSR #8
+ BCC label2
+__arm_div_large
+ LSL r1, r1, #6
+ RSBS r12, r1, r0, LSR #8
+ ORR r2, r2, #0xfc000000
+ BCC label2
+ LSL r1, r1, #6
+ RSBS r12, r1, r0, LSR #8
+ ORR r2, r2, #0x3f00000
+ BCC label2
+ LSL r1, r1, #6
+ RSBS r12, r1, r0, LSR #8
+ ORR r2, r2, #0xfc000
+ ORRCS r2, r2, #0x3f00
+ LSLCS r1, r1, #6
+ RSBS r12, r1, #0
+ BCS __aeabi_idiv0
+label3
+ LSRCS r1, r1, #6
+label2
+ RSBS r12, r1, r0, LSR #7
+ SUBCS r0, r0, r1, LSL #7
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #6
+ SUBCS r0, r0, r1, LSL #6
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #5
+ SUBCS r0, r0, r1, LSL #5
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #4
+ SUBCS r0, r0, r1, LSL #4
+ ADC r2, r2, r2
+label1
+ RSBS r12, r1, r0, LSR #3
+ SUBCS r0, r0, r1, LSL #3
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #2
+ SUBCS r0, r0, r1, LSL #2
+ ADCS r2, r2, r2
+ BCS label3
+ RSBS r12, r1, r0, LSR #1
+ SUBCS r0, r0, r1, LSL #1
+ ADC r2, r2, r2
+ SUBS r1, r0, r1
+ MOVCC r1, r0
+ ADC r0, r2, r2
+ ASRS r3, r3, #31
+ RSBMI r0, r0, #0
+ RSBCS r1, r1, #0
+ BX r14
+
+ ; What to do about division by zero? For now, just return.
+__aeabi_idiv0
+ BX r14
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
new file mode 100644
index 0000000000..b7d946ecc7
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
@@ -0,0 +1,48 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___divdi3
+___divdi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r4, r3, asr #31
+ add r7, sp, #8
+ stmfd sp!, {r10, r11}
+ mov r10, r1, asr #31
+ sub sp, sp, #8
+ mov r11, r10
+ mov r5, r4
+ eor r0, r0, r10
+ eor r1, r1, r10
+ eor r2, r2, r4
+ eor r3, r3, r4
+ subs r2, r2, r4
+ sbc r3, r3, r5
+ mov ip, #0
+ subs r0, r0, r10
+ sbc r1, r1, r11
+ str ip, [sp, #0]
+ bl ___udivmoddi4
+ eor r2, r10, r4
+ eor r3, r10, r4
+ eor r0, r0, r2
+ eor r1, r1, r3
+ subs r0, r0, r2
+ sbc r1, r1, r3
+ sub sp, r7, #16
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c
new file mode 100644
index 0000000000..286a504b49
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c
@@ -0,0 +1,77 @@
+/** @file
+ Compiler intrinsic for 64-bit compare, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
+
+// Returns: a / b
+
+INT64
+__divdi3(INT64 a, INT64 b)
+{
+ const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
+ INT64 s_a = a >> bits_in_dword_m1; // s_a = a < 0 ? -1 : 0
+ INT64 s_b = b >> bits_in_dword_m1; // s_b = b < 0 ? -1 : 0
+ a = (a ^ s_a) - s_a; // negate if s_a == -1
+ b = (b ^ s_b) - s_b; // negate if s_b == -1
+ s_a ^= s_b; // sign of quotient
+ return (__udivmoddi4(a, b, (UINT64*)0) ^ s_a) - s_a; // negate if s_a == -1
+}
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
new file mode 100644
index 0000000000..2651572222
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___divsi3
+___divsi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ eor r3, r0, r0, asr #31
+ eor r2, r1, r1, asr #31
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r5, r0, asr #31
+ add r7, sp, #8
+ mov r4, r1, asr #31
+ sub r0, r3, r0, asr #31
+ sub r1, r2, r1, asr #31
+ bl ___udivsi3
+ eor r1, r5, r4
+ eor r0, r0, r1
+ rsb r0, r1, r0
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c
new file mode 100644
index 0000000000..56d731ca8e
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c
@@ -0,0 +1,78 @@
+/** @file
+ Compiler intrinsic for 32--bit unsigned division, ported from LLVM code.
+
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT32 __udivsi3(UINT32 n, UINT32 d);
+
+// Returns: a / b
+
+INT32
+__divsi3(INT32 a, INT32 b)
+{
+ const int bits_in_word_m1 = (int)(sizeof(INT32) * CHAR_BIT) - 1;
+ INT32 s_a = a >> bits_in_word_m1; // s_a = a < 0 ? -1 : 0
+ INT32 s_b = b >> bits_in_word_m1; // s_b = b < 0 ? -1 : 0
+ a = (a ^ s_a) - s_a; // negate if s_a == -1
+ b = (b ^ s_b) - s_b; // negate if s_b == -1
+ s_a ^= s_b; // sign of quotient
+ return (__udivsi3(a, b) ^ s_a) - s_a; // negate if s_a == -1
+}
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm
new file mode 100644
index 0000000000..9956d064c2
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm
@@ -0,0 +1,41 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_lasr
+
+ AREA Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_lasr (
+; IN UINT32 Dividen
+; IN UINT32 Divisor
+; );
+;
+__aeabi_lasr
+ SUBS r3,r2,#0x20
+ BPL {pc} + 0x18 ; 0x1c
+ RSB r3,r2,#0x20
+ LSR r0,r0,r2
+ ORR r0,r0,r1,LSL r3
+ ASR r1,r1,r2
+ BX lr
+ ASR r0,r1,r3
+ ASR r1,r1,#31
+ BX lr
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm
new file mode 100644
index 0000000000..cb81608b01
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm
@@ -0,0 +1,54 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_ldivmod
+ EXTERN __aeabi_uldivmod
+
+ AREA Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uidivmode (
+; IN UINT32 Dividen
+; IN UINT32 Divisor
+; );
+;
+
+__aeabi_ldivmod
+ PUSH {r4,lr}
+ ASRS r4,r1,#1
+ EOR r4,r4,r3,LSR #1
+ BPL {pc} + 0xc ; 0x18
+ RSBS r0,r0,#0
+ RSC r1,r1,#0
+ TST r3,r3
+ BPL {pc} + 0xc ; 0x28
+ RSBS r2,r2,#0
+ RSC r3,r3,#0
+ BL __aeabi_uldivmod ;
+ TST r4,#0x40000000
+ BEQ {pc} + 0xc ; 0x3c
+ RSBS r0,r0,#0
+ RSC r1,r1,#0
+ TST r4,#0x80000000
+ BEQ {pc} + 0xc ; 0x4c
+ RSBS r2,r2,#0
+ RSC r3,r3,#0
+ POP {r4,pc}
+
+ END
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm
new file mode 100644
index 0000000000..745b984085
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm
@@ -0,0 +1,43 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_llsl
+
+ AREA Math, CODE, READONLY
+
+;
+;VOID
+;EFIAPI
+;__aeabi_llsl (
+; IN VOID *Destination,
+; IN VOID *Source,
+; IN UINT32 Size
+; );
+;
+
+__aeabi_llsl
+ SUBS r3,r2,#0x20
+ BPL {pc} + 0x18 ; 0x1c
+ RSB r3,r2,#0x20
+ LSL r1,r1,r2
+ ORR r1,r1,r0,LSR r3
+ LSL r0,r0,r2
+ BX lr
+ LSL r1,r0,r3
+ MOV r0,#0
+ BX lr
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm
new file mode 100644
index 0000000000..630b542c70
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm
@@ -0,0 +1,44 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_llsr
+
+ AREA Math, CODE, READONLY
+
+;
+;VOID
+;EFIAPI
+;__aeabi_llsr (
+; IN VOID *Destination,
+; IN VOID *Source,
+; IN UINT32 Size
+; );
+;
+__aeabi_llsr
+ SUBS r3,r2,#0x20
+ BPL {pc} + 0x18 ; 0x1c
+ RSB r3,r2,#0x20
+ LSR r0,r0,r2
+ ORR r0,r0,r1,LSL r3
+ LSR r1,r1,r2
+ BX lr
+ LSR r0,r1,r3
+ MOV r1,#0
+ BX lr
+
+ END
+
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
new file mode 100644
index 0000000000..2257deef97
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___lshrdi3
+___lshrdi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 0, uses_anonymous_args = 0
+ @ link register save eliminated.
+ cmp r2, #31
+ @ lr needed for prologue
+ bls L2
+ cmp r2, #63
+ subls r2, r2, #32
+ movls r2, r1, lsr r2
+ movhi r2, #0
+ mov r0, r2
+ mov r1, #0
+ bx lr
+L2:
+ cmp r2, #0
+ rsbne r3, r2, #32
+ movne r3, r1, asl r3
+ movne r1, r1, lsr r2
+ orrne r0, r3, r0, lsr r2
+ bx lr
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c
new file mode 100644
index 0000000000..14b3c8f00a
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c
@@ -0,0 +1,83 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+#include "Llvm_int_lib.h"
+
+// Returns: logical a >> b
+
+// Precondition: 0 <= b < bits_in_dword
+
+INT64
+__lshrdi3(INT64 a, INT32 b)
+{
+ const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
+ udwords input;
+ udwords result;
+ input.all = a;
+ if (b & bits_in_word) // bits_in_word <= b < bits_in_dword
+ {
+ result.high = 0;
+ result.low = input.high >> (b - bits_in_word);
+ }
+ else // 0 <= b < bits_in_word
+ {
+ if (b == 0)
+ return a;
+ result.high = input.high >> b;
+ result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
+ }
+ return result.all;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
new file mode 100644
index 0000000000..2582a81f90
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl _memcpy
+_memcpy:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r7, lr}
+ mov ip, #0
+ add r7, sp, #0
+ mov lr, r0
+ b L4
+L5:
+ ldrb r3, [r1], #1 @ zero_extendqisi2
+ add ip, ip, #1
+ and r3, r3, #255
+ strb r3, [lr], #1
+L4:
+ cmp ip, r2
+ bne L5
+ ldmfd sp!, {r7, pc}
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm
new file mode 100644
index 0000000000..60dbcf2ab5
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_memcpy
+
+ AREA Memcpy, CODE, READONLY
+
+;
+;VOID
+;EFIAPI
+;__aeabi_memcpy (
+; IN VOID *Destination,
+; IN VOID *Source,
+; IN UINT32 Size
+; );
+;
+__aeabi_memcpy
+ CMP r2, #0
+ BXEQ r14
+loop
+ LDRB r3, [r1], #1
+ STRB r3, [r0], #1
+ SUBS r2, r2, #1
+ BXEQ r14
+ B loop
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm
new file mode 100644
index 0000000000..fb251c1eaa
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm
@@ -0,0 +1,61 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_memcpy4
+
+ AREA Memcpy4, CODE, READONLY
+
+;
+;VOID
+;EFIAPI
+;__aeabi_memcpy (
+; IN VOID *Destination,
+; IN VOID *Source,
+; IN UINT32 Size
+; );
+;
+__aeabi_memcpy4
+ stmdb sp!, {r4, lr}
+ subs r2, r2, #32 ; 0x20
+ bcc memcpy4_label2
+memcpy4_label1
+ ldmcsia r1!, {r3, r4, ip, lr}
+ stmcsia r0!, {r3, r4, ip, lr}
+ ldmcsia r1!, {r3, r4, ip, lr}
+ stmcsia r0!, {r3, r4, ip, lr}
+ subcss r2, r2, #32 ; 0x20
+ bcs memcpy4_label1
+memcpy4_label2
+ movs ip, r2, lsl #28
+ ldmcsia r1!, {r3, r4, ip, lr}
+ stmcsia r0!, {r3, r4, ip, lr}
+ ldmmiia r1!, {r3, r4}
+ stmmiia r0!, {r3, r4}
+ ldmia sp!, {r4, lr}
+ movs ip, r2, lsl #30
+ ldrcs r3, [r1], #4
+ strcs r3, [r0], #4
+ bxeq lr
+
+_memcpy4_lastbytes_aligned
+ movs r2, r2, lsl #31
+ ldrcsh r3, [r1], #2
+ ldrmib r2, [r1], #1
+ strcsh r3, [r0], #2
+ strmib r2, [r0], #1
+ bx lr
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
new file mode 100644
index 0000000000..f88464483b
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+
+ .text
+ .align 2
+ .globl _memset
+_memset:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r7, lr}
+ mov ip, #0
+ add r7, sp, #0
+ mov lr, r0
+ b L9
+L10:
+ and r3, r1, #255
+ add ip, ip, #1
+ strb r3, [lr], #1
+L9:
+ cmp ip, r2
+ bne L10
+ ldmfd sp!, {r7, pc}
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
new file mode 100644
index 0000000000..7af8d21683
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S
@@ -0,0 +1,47 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___moddi3
+___moddi3:
+ @ args = 0, pretend = 0, frame = 8
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r4, r1, asr #31
+ add r7, sp, #8
+ stmfd sp!, {r10, r11}
+ mov r10, r3, asr #31
+ sub sp, sp, #16
+ mov r5, r4
+ mov r11, r10
+ eor r0, r0, r4
+ eor r1, r1, r4
+ eor r2, r2, r10
+ eor r3, r3, r10
+ add ip, sp, #8
+ subs r0, r0, r4
+ sbc r1, r1, r5
+ subs r2, r2, r10
+ sbc r3, r3, r11
+ str ip, [sp, #0]
+ bl ___udivmoddi4
+ ldrd r0, [sp, #8]
+ eor r0, r0, r4
+ eor r1, r1, r4
+ subs r0, r0, r4
+ sbc r1, r1, r5
+ sub sp, r7, #16
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.c
new file mode 100644
index 0000000000..796b179dd3
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.c
@@ -0,0 +1,77 @@
+/** @file
+ Compiler intrinsic for 64-bit mod, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
+
+// Returns: a % b
+
+INT64
+__moddi3(INT64 a, INT64 b)
+{
+ const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
+ INT64 s = b >> bits_in_dword_m1; // s = b < 0 ? -1 : 0
+ b = (b ^ s) - s; // negate if s == -1
+ s = a >> bits_in_dword_m1; // s = a < 0 ? -1 : 0
+ a = (a ^ s) - s; // negate if s == -1
+ INT64 r;
+ __udivmoddi4(a, b, (UINT64*)&r);
+ return (r ^ s) - s; // negate if s == -1
+}
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
new file mode 100644
index 0000000000..14d8542198
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S
@@ -0,0 +1,28 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___modsi3
+___modsi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r7, lr}
+ add r7, sp, #8
+ mov r5, r0
+ mov r4, r1
+ bl ___divsi3
+ mul r0, r4, r0
+ rsb r0, r0, r5
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.c
new file mode 100644
index 0000000000..45e0afd0d1
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.c
@@ -0,0 +1,70 @@
+/** @file
+ Compiler intrinsic for 32-bit mod, ported from LLVM code.
+
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+// Returns: a % b
+
+INT32
+__modsi3(INT32 a, INT32 b)
+{
+ return a - (a / b) * b;
+}
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
new file mode 100644
index 0000000000..a36dbff8c3
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S
@@ -0,0 +1,59 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___muldi3
+___muldi3:
+ @ args = 0, pretend = 0, frame = 8
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r8, r10, r11}
+ ldr r11, L4
+ mov r4, r0, lsr #16
+ and r8, r0, r11
+ and ip, r2, r11
+ mul lr, ip, r8
+ mul ip, r4, ip
+ sub sp, sp, #8
+ add r10, ip, lr, lsr #16
+ and ip, r10, r11
+ and lr, lr, r11
+ mov r6, r2, lsr #16
+ str r4, [sp, #4]
+ add r4, lr, ip, asl #16
+ mul ip, r8, r6
+ mov r5, r10, lsr #16
+ add r10, ip, r4, lsr #16
+ and ip, r10, r11
+ and lr, r4, r11
+ add r4, lr, ip, asl #16
+ mul r0, r3, r0
+ add ip, r5, r10, lsr #16
+ ldr r5, [sp, #4]
+ mla r0, r2, r1, r0
+ mla r5, r6, r5, ip
+ mov r10, r4
+ add r11, r0, r5
+ mov r1, r11
+ mov r0, r4
+ sub sp, r7, #24
+ ldmfd sp!, {r8, r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+ .p2align 2
+L5:
+ .align 2
+L4:
+ .long 65535
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.c
new file mode 100644
index 0000000000..88c88cec2d
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.c
@@ -0,0 +1,98 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+#include
+#include "Llvm_int_lib.h"
+
+
+// Returns: a * b
+
+static
+INT64
+__muldsi3(UINT32 a, UINT32 b)
+{
+ dwords r;
+ const int bits_in_word_2 = (int)(sizeof(INT32) * CHAR_BIT) / 2;
+ const UINT32 lower_mask = (UINT32)~0 >> bits_in_word_2;
+ r.low = (a & lower_mask) * (b & lower_mask);
+ UINT32 t = r.low >> bits_in_word_2;
+ r.low &= lower_mask;
+ t += (a >> bits_in_word_2) * (b & lower_mask);
+ r.low += (t & lower_mask) << bits_in_word_2;
+ r.high = t >> bits_in_word_2;
+ t = r.low >> bits_in_word_2;
+ r.low &= lower_mask;
+ t += (b >> bits_in_word_2) * (a & lower_mask);
+ r.low += (t & lower_mask) << bits_in_word_2;
+ r.high += t >> bits_in_word_2;
+ r.high += (a >> bits_in_word_2) * (b >> bits_in_word_2);
+ return r.all;
+}
+
+// Returns: a * b
+
+INT64
+__muldi3(INT64 a, INT64 b)
+{
+ dwords x;
+ x.all = a;
+ dwords y;
+ y.all = b;
+ dwords r;
+ r.all = __muldsi3(x.low, y.low);
+ r.high += x.high * y.low + x.low * y.high;
+ return r.all;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
new file mode 100644
index 0000000000..baf7caa006
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
@@ -0,0 +1,49 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __ARM_ll_mullu
+ EXPORT __aeabi_lmul
+
+ AREA Math, CODE, READONLY
+
+;
+;INT64
+;EFIAPI
+;__aeabi_lmul (
+; IN INT64 Multiplicand
+; IN INT32 Multiplier
+; );
+;
+__ARM_ll_mullu
+ mov r3, #0
+// Make upper part of INT64 Multiplier 0 and use __aeabi_lmul
+
+;
+;INT64
+;EFIAPI
+;__aeabi_lmul (
+; IN INT64 Multiplicand
+; IN INT64 Multiplier
+; );
+;
+__aeabi_lmul
+ stmdb sp!, {lr}
+ mov lr, r0
+ umull r0, ip, r2, lr
+ mla r1, r2, r1, ip
+ mla r1, r3, lr, r1
+ ldmia sp!, {pc}
+
+ END
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
new file mode 100644
index 0000000000..2e26160363
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
@@ -0,0 +1,29 @@
+///------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+
+ EXPORT __ARM_switch8
+
+ AREA ArmSwitch, CODE, READONLY
+
+__ARM_switch8
+ LDRB r12,[lr,#-1]
+ CMP r3,r12
+ LDRBCC r3,[lr,r3]
+ LDRBCS r3,[lr,r12]
+ ADD r12,lr,r3,LSL #1
+ BX r12
+
+ END
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch16.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch16.S
new file mode 100644
index 0000000000..48e2ab74df
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch16.S
@@ -0,0 +1,46 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008, Apple, Inc.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http)://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
+#
+#**/
+#
+
+.text
+.p2align 2
+
+.globl ASM_PFX(__switch16)
+
+
+ASM_PFX(__switch16):
+ ldrh ip, [lr, #-1]
+ cmp r0, ip
+ add r0, lr, r0, lsl #1
+ ldrccsh r0, [r0, #1]
+ add ip, lr, ip, lsl #1
+ ldrcssh r0, [ip, #1]
+ add ip, lr, r0, lsl #1
+ bx ip
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch32.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch32.S
new file mode 100644
index 0000000000..5ecffa6fee
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch32.S
@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008, Apple, Inc.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http)://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
+#
+#**/
+#
+
+.text
+.p2align 2
+
+.globl ASM_PFX(__switch32)
+
+
+ASM_PFX(__switch32):
+ ldr ip, [lr, #-1]
+ cmp r0, ip
+ add r0, lr, r0, lsl #2
+ ldrcc r0, [r0, #3]
+ add ip, lr, ip, lsl #2
+ ldrcs r0, [ip, #3]
+ add ip, lr, r0
+ bx ip
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch8.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch8.S
new file mode 100644
index 0000000000..947156ee57
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch8.S
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008, Apple, Inc.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http)://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
+#
+#**/
+#
+
+.text
+.p2align 2
+
+.globl ASM_PFX(__switch8)
+
+
+ASM_PFX(__switch8):
+ ldrb ip, [lr, #-1]
+ cmp r0, ip
+ ldrccsb r0, [lr, r0]
+ ldrcssb r0, [lr, ip]
+ add ip, lr, r0, lsl #1
+ bx ip
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S
new file mode 100644
index 0000000000..e49204fdd4
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S
@@ -0,0 +1,43 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008, Apple, Inc.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http)://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.;
+#
+#**/
+#
+
+.text
+.p2align 2
+
+.globl ASM_PFX(__switchu8)
+
+
+ASM_PFX(__switchu8):
+ ldrb ip,[lr,#-1]
+ cmp r3,ip
+ ldrccb r3,[lr,r3]
+ ldrcsb r3,[lr,ip]
+ add ip,lr,r3,LSL #1
+ bx ip
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.c
new file mode 100644
index 0000000000..0cf1404b32
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.c
@@ -0,0 +1,82 @@
+/** @file
+ Compiler intrinsic for 64-bit compare, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+
+// Returns: if (a < b) returns 0
+// if (a == b) returns 1
+// if (a > b) returns 2
+
+UINT32
+__ucmpdi2(UINT64 a, UINT64 b)
+{
+ udwords x;
+ x.all = a;
+ udwords y;
+ y.all = b;
+ if (x.high < y.high)
+ return 0;
+ if (x.high > y.high)
+ return 2;
+ if (x.low < y.low)
+ return 0;
+ if (x.low > y.low)
+ return 2;
+ return 1;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
new file mode 100644
index 0000000000..fd7715da66
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S
@@ -0,0 +1,28 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___udivdi3
+___udivdi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ sub sp, sp, #8
+ mov ip, #0
+ str ip, [sp, #0]
+ bl ___udivmoddi4
+ sub sp, r7, #0
+ ldmfd sp!, {r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.c
new file mode 100644
index 0000000000..1a04ea7dd1
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.c
@@ -0,0 +1,71 @@
+/** @file
+ Compiler intrinsic for 64-bit unisigned div, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT64 __udivmoddi4 (UINT64 a, UINT64 b, UINT64 *rem);
+
+// Returns: a / b
+
+UINT64
+__udivdi3(UINT64 a, UINT64 b)
+{
+ return __udivmoddi4(a, b, 0);
+}
+
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
new file mode 100644
index 0000000000..1e54baec24
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S
@@ -0,0 +1,243 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___udivmoddi4
+___udivmoddi4:
+ @ args = 8, pretend = 0, frame = 16
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r10, r11}
+ sub sp, sp, #20
+ stmia sp, {r2-r3}
+ ldr r6, [sp, #48]
+ orrs r2, r2, r3
+ mov r10, r0
+ mov r11, r1
+ beq L2
+ subs ip, r1, #0
+ bne L4
+ cmp r3, #0
+ bne L6
+ cmp r6, #0
+ beq L8
+ mov r1, r2
+ bl ___umodsi3
+ mov r1, #0
+ stmia r6, {r0-r1}
+L8:
+ ldr r1, [sp, #0]
+ mov r0, r10
+ b L45
+L6:
+ cmp r6, #0
+ movne r1, #0
+ stmneia r6, {r0-r1}
+ b L2
+L4:
+ ldr r1, [sp, #0]
+ cmp r1, #0
+ bne L12
+ ldr r2, [sp, #4]
+ cmp r2, #0
+ bne L14
+ cmp r6, #0
+ beq L16
+ mov r1, r2
+ mov r0, r11
+ bl ___umodsi3
+ mov r1, #0
+ stmia r6, {r0-r1}
+L16:
+ ldr r1, [sp, #4]
+ mov r0, r11
+L45:
+ bl ___udivsi3
+L46:
+ mov r10, r0
+ mov r11, #0
+ b L10
+L14:
+ subs r1, r0, #0
+ bne L18
+ cmp r6, #0
+ beq L16
+ ldr r1, [sp, #4]
+ mov r0, r11
+ bl ___umodsi3
+ mov r4, r10
+ mov r5, r0
+ stmia r6, {r4-r5}
+ b L16
+L18:
+ sub r3, r2, #1
+ tst r2, r3
+ bne L22
+ cmp r6, #0
+ movne r4, r0
+ andne r5, ip, r3
+ stmneia r6, {r4-r5}
+L24:
+ rsb r3, r2, #0
+ and r3, r2, r3
+ clz r3, r3
+ rsb r3, r3, #31
+ mov r0, ip, lsr r3
+ b L46
+L22:
+ clz r2, r2
+ clz r3, ip
+ rsb r3, r3, r2
+ cmp r3, #30
+ bhi L48
+ rsb r2, r3, #31
+ add lr, r3, #1
+ mov r3, r1, asl r2
+ str r3, [sp, #12]
+ mov r3, r1, lsr lr
+ ldr r0, [sp, #0]
+ mov r5, ip, lsr lr
+ orr r4, r3, ip, asl r2
+ str r0, [sp, #8]
+ b L29
+L12:
+ ldr r3, [sp, #4]
+ cmp r3, #0
+ bne L30
+ sub r3, r1, #1
+ tst r1, r3
+ bne L32
+ cmp r6, #0
+ andne r3, r3, r0
+ movne r2, r3
+ movne r3, #0
+ stmneia r6, {r2-r3}
+L34:
+ cmp r1, #1
+ beq L10
+ rsb r3, r1, #0
+ and r3, r1, r3
+ clz r3, r3
+ rsb r0, r3, #31
+ mov r1, ip, lsr r0
+ rsb r3, r0, #32
+ mov r0, r10, lsr r0
+ orr ip, r0, ip, asl r3
+ str r1, [sp, #12]
+ str ip, [sp, #8]
+ ldrd r10, [sp, #8]
+ b L10
+L32:
+ clz r2, r1
+ clz r3, ip
+ rsb r3, r3, r2
+ rsb r4, r3, #31
+ mov r2, r0, asl r4
+ mvn r1, r3
+ and r2, r2, r1, asr #31
+ add lr, r3, #33
+ str r2, [sp, #8]
+ add r2, r3, #1
+ mov r3, r3, asr #31
+ and r0, r3, r0, asl r1
+ mov r3, r10, lsr r2
+ orr r3, r3, ip, asl r4
+ and r3, r3, r1, asr #31
+ orr r0, r0, r3
+ mov r3, ip, lsr lr
+ str r0, [sp, #12]
+ mov r0, r10, lsr lr
+ and r5, r3, r2, asr #31
+ rsb r3, lr, #31
+ mov r3, r3, asr #31
+ orr r0, r0, ip, asl r1
+ and r3, r3, ip, lsr r2
+ and r0, r0, r2, asr #31
+ orr r4, r3, r0
+ b L29
+L30:
+ clz r2, r3
+ clz r3, ip
+ rsb r3, r3, r2
+ cmp r3, #31
+ bls L37
+L48:
+ cmp r6, #0
+ stmneia r6, {r10-r11}
+ b L2
+L37:
+ rsb r1, r3, #31
+ mov r0, r0, asl r1
+ add lr, r3, #1
+ mov r2, #0
+ str r0, [sp, #12]
+ mov r0, r10, lsr lr
+ str r2, [sp, #8]
+ sub r2, r3, #31
+ and r0, r0, r2, asr #31
+ mov r3, ip, lsr lr
+ orr r4, r0, ip, asl r1
+ and r5, r3, r2, asr #31
+L29:
+ mov ip, #0
+ mov r10, ip
+ b L40
+L41:
+ ldr r1, [sp, #12]
+ ldr r2, [sp, #8]
+ mov r3, r4, lsr #31
+ orr r5, r3, r5, asl #1
+ mov r3, r1, lsr #31
+ orr r4, r3, r4, asl #1
+ mov r3, r2, lsr #31
+ orr r0, r3, r1, asl #1
+ orr r1, ip, r2, asl #1
+ ldmia sp, {r2-r3}
+ str r0, [sp, #12]
+ subs r2, r2, r4
+ sbc r3, r3, r5
+ str r1, [sp, #8]
+ subs r0, r2, #1
+ sbc r1, r3, #0
+ mov r2, r1, asr #31
+ ldmia sp, {r0-r1}
+ mov r3, r2
+ and ip, r2, #1
+ and r3, r3, r1
+ and r2, r2, r0
+ subs r4, r4, r2
+ sbc r5, r5, r3
+ add r10, r10, #1
+L40:
+ cmp r10, lr
+ bne L41
+ ldrd r0, [sp, #8]
+ adds r0, r0, r0
+ adc r1, r1, r1
+ cmp r6, #0
+ orr r10, r0, ip
+ mov r11, r1
+ stmneia r6, {r4-r5}
+ b L10
+L2:
+ mov r10, #0
+ mov r11, #0
+L10:
+ mov r0, r10
+ mov r1, r11
+ sub sp, r7, #20
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.c
new file mode 100644
index 0000000000..58f7554cc3
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.c
@@ -0,0 +1,287 @@
+/** @file
+ Compiler intrinsic for 64-bit compare, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+// Effects: if rem != 0, *rem = a % b
+// Returns: a / b
+
+// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide
+
+UINT64
+__udivmoddi4 (UINT64 a, UINT64 b, UINT64* rem)
+{
+ const unsigned n_uword_bits = sizeof(UINT32) * CHAR_BIT;
+ const unsigned n_udword_bits = sizeof(UINT64) * CHAR_BIT;
+ udwords n;
+ n.all = a;
+ udwords d;
+ d.all = b;
+ udwords q;
+ udwords r;
+ unsigned sr;
+
+ if (b == 0) {
+// ASSERT (FALSE);
+ return 0;
+ }
+
+ // special cases, X is unknown, K != 0
+ if (n.high == 0)
+ {
+ if (d.high == 0)
+ {
+ // 0 X
+ // ---
+ // 0 X
+ if (rem)
+ *rem = n.low % d.low;
+ return n.low / d.low;
+ }
+ // 0 X
+ // ---
+ // K X
+ if (rem)
+ *rem = n.low;
+ return 0;
+ }
+ // n.high != 0
+ if (d.low == 0)
+ {
+ if (d.high == 0)
+ {
+ // K X
+ // ---
+ // 0 0
+ if (rem)
+ *rem = n.high % d.low;
+ return n.high / d.low;
+ }
+ // d.high != 0
+ if (n.low == 0)
+ {
+ // K 0
+ // ---
+ // K 0
+ if (rem)
+ {
+ r.high = n.high % d.high;
+ r.low = 0;
+ *rem = r.all;
+ }
+ return n.high / d.high;
+ }
+ // K K
+ // ---
+ // K 0
+ if ((d.high & (d.high - 1)) == 0) // if d is a power of 2
+ {
+ if (rem)
+ {
+ r.low = n.low;
+ r.high = n.high & (d.high - 1);
+ *rem = r.all;
+ }
+ return n.high >> COUNT_TRAILING_ZEROS(d.high);
+ }
+ // K K
+ // ---
+ // K 0
+ sr = COUNT_LEADING_ZEROS(d.high) - COUNT_LEADING_ZEROS(n.high);
+ // 0 <= sr <= n_uword_bits - 2 or sr large
+ if (sr > n_uword_bits - 2)
+ {
+ if (rem)
+ *rem = n.all;
+ return 0;
+ }
+ ++sr;
+ // 1 <= sr <= n_uword_bits - 1
+ // q.all = n.all << (n_udword_bits - sr);
+ q.low = 0;
+ q.high = n.low << (n_uword_bits - sr);
+ // r.all = n.all >> sr;
+ r.high = n.high >> sr;
+ r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
+ }
+ else // d.low != 0
+ {
+ if (d.high == 0)
+ {
+ // K X
+ // ---
+ // 0 K
+ if ((d.low & (d.low - 1)) == 0) // if d is a power of 2
+ {
+ if (rem)
+ *rem = n.low & (d.low - 1);
+ if (d.low == 1)
+ return n.all;
+ unsigned sr = COUNT_TRAILING_ZEROS(d.low);
+ q.high = n.high >> sr;
+ q.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
+ return q.all;
+ }
+ // K X
+ // ---
+ // 0 K
+ sr = 1 + n_uword_bits + COUNT_LEADING_ZEROS(d.low) - COUNT_LEADING_ZEROS(n.high);
+ // 2 <= sr <= n_udword_bits - 1
+ // q.all = n.all << (n_udword_bits - sr);
+ // r.all = n.all >> sr;
+ // if (sr == n_uword_bits)
+ // {
+ // q.low = 0;
+ // q.high = n.low;
+ // r.high = 0;
+ // r.low = n.high;
+ // }
+ // else if (sr < n_uword_bits) // 2 <= sr <= n_uword_bits - 1
+ // {
+ // q.low = 0;
+ // q.high = n.low << (n_uword_bits - sr);
+ // r.high = n.high >> sr;
+ // r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
+ // }
+ // else // n_uword_bits + 1 <= sr <= n_udword_bits - 1
+ // {
+ // q.low = n.low << (n_udword_bits - sr);
+ // q.high = (n.high << (n_udword_bits - sr)) |
+ // (n.low >> (sr - n_uword_bits));
+ // r.high = 0;
+ // r.low = n.high >> (sr - n_uword_bits);
+ // }
+ q.low = (n.low << (n_udword_bits - sr)) &
+ ((INT32)(n_uword_bits - sr) >> (n_uword_bits-1));
+ q.high = ((n.low << ( n_uword_bits - sr)) &
+ ((INT32)(sr - n_uword_bits - 1) >> (n_uword_bits-1))) |
+ (((n.high << (n_udword_bits - sr)) |
+ (n.low >> (sr - n_uword_bits))) &
+ ((INT32)(n_uword_bits - sr) >> (n_uword_bits-1)));
+ r.high = (n.high >> sr) &
+ ((INT32)(sr - n_uword_bits) >> (n_uword_bits-1));
+ r.low = ((n.high >> (sr - n_uword_bits)) &
+ ((INT32)(n_uword_bits - sr - 1) >> (n_uword_bits-1))) |
+ (((n.high << (n_uword_bits - sr)) |
+ (n.low >> sr)) &
+ ((INT32)(sr - n_uword_bits) >> (n_uword_bits-1)));
+ }
+ else
+ {
+ // K X
+ // ---
+ // K K
+ sr = COUNT_LEADING_ZEROS(d.high) - COUNT_LEADING_ZEROS(n.high);
+ // 0 <= sr <= n_uword_bits - 1 or sr large
+ if (sr > n_uword_bits - 1)
+ {
+ if (rem)
+ *rem = n.all;
+ return 0;
+ }
+ ++sr;
+ // 1 <= sr <= n_uword_bits
+ // q.all = n.all << (n_udword_bits - sr);
+ q.low = 0;
+ q.high = n.low << (n_uword_bits - sr);
+ // r.all = n.all >> sr;
+ // if (sr < n_uword_bits)
+ // {
+ // r.high = n.high >> sr;
+ // r.low = (n.high << (n_uword_bits - sr)) | (n.low >> sr);
+ // }
+ // else
+ // {
+ // r.high = 0;
+ // r.low = n.high;
+ // }
+ r.high = (n.high >> sr) &
+ ((INT32)(sr - n_uword_bits) >> (n_uword_bits-1));
+ r.low = (n.high << (n_uword_bits - sr)) |
+ ((n.low >> sr) &
+ ((INT32)(sr - n_uword_bits) >> (n_uword_bits-1)));
+ }
+ }
+ // Not a special case
+ // q and r are initialized with:
+ // q.all = n.all << (n_udword_bits - sr);
+ // r.all = n.all >> sr;
+ // 1 <= sr <= n_udword_bits - 1
+ UINT32 carry = 0;
+ for (; sr > 0; --sr)
+ {
+ // r:q = ((r:q) << 1) | carry
+ r.high = (r.high << 1) | (r.low >> (n_uword_bits - 1));
+ r.low = (r.low << 1) | (q.high >> (n_uword_bits - 1));
+ q.high = (q.high << 1) | (q.low >> (n_uword_bits - 1));
+ q.low = (q.low << 1) | carry;
+ // carry = 0;
+ // if (r.all >= d.all)
+ // {
+ // r.all -= d.all;
+ // carry = 1;
+ // }
+ const INT64 s = (INT64)(d.all - r.all - 1) >> (n_udword_bits - 1);
+ carry = s & 1;
+ r.all -= d.all & s;
+ }
+ q.all = (q.all << 1) | carry;
+ if (rem)
+ *rem = r.all;
+ return q.all;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
new file mode 100644
index 0000000000..e5a0afa053
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S
@@ -0,0 +1,57 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___udivsi3
+___udivsi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ cmp r1, #0
+ cmpne r0, #0
+ stmfd sp!, {r4, r5, r7, lr}
+ add r7, sp, #8
+ beq L2
+ clz r2, r1
+ clz r3, r0
+ rsb r3, r3, r2
+ cmp r3, #31
+ bhi L2
+ ldmeqfd sp!, {r4, r5, r7, pc}
+ add r5, r3, #1
+ rsb r3, r3, #31
+ mov lr, #0
+ mov r2, r0, asl r3
+ mov ip, r0, lsr r5
+ mov r4, lr
+ b L8
+L9:
+ mov r0, r2, lsr #31
+ orr ip, r0, ip, asl #1
+ orr r2, r3, lr
+ rsb r3, ip, r1
+ sub r3, r3, #1
+ and r0, r1, r3, asr #31
+ mov lr, r3, lsr #31
+ rsb ip, r0, ip
+ add r4, r4, #1
+L8:
+ cmp r4, r5
+ mov r3, r2, asl #1
+ bne L9
+ orr r0, r3, lr
+ ldmfd sp!, {r4, r5, r7, pc}
+L2:
+ mov r0, #0
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.c
new file mode 100644
index 0000000000..59d5b23643
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.c
@@ -0,0 +1,111 @@
+/** @file
+ Compiler intrinsic for 32-bit unsigned div, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+
+// Returns: n / d
+
+// Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide
+
+UINT32
+__udivsi3(UINT32 n, UINT32 d)
+{
+ const unsigned n_uword_bits = sizeof(UINT32) * CHAR_BIT;
+ UINT32 q;
+ UINT32 r;
+ unsigned sr;
+
+ // special cases
+ if (d == 0) {
+// ASSERT (FALSE);
+ return 0; // ?!
+ }
+ if (n == 0)
+ return 0;
+
+ sr = COUNT_LEADING_ZEROS(d) - COUNT_LEADING_ZEROS(n);
+ // 0 <= sr <= n_uword_bits - 1 or sr large
+ if (sr > n_uword_bits - 1) // d > r
+ return 0;
+ if (sr == n_uword_bits - 1) // d == 1
+ return n;
+ ++sr;
+ // 1 <= sr <= n_uword_bits - 1
+ // Not a special case
+ q = n << (n_uword_bits - sr);
+ r = n >> sr;
+ UINT32 carry = 0;
+ for (; sr > 0; --sr)
+ {
+ // r:q = ((r:q) << 1) | carry
+ r = (r << 1) | (q >> (n_uword_bits - 1));
+ q = (q << 1) | carry;
+ // carry = 0;
+ // if (r.all >= d.all)
+ // {
+ // r.all -= d.all;
+ // carry = 1;
+ // }
+ const INT32 s = (INT32)(d - r - 1) >> (n_uword_bits - 1);
+ carry = s & 1;
+ r -= d & s;
+ }
+ q = (q << 1) | carry;
+ return q;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm
new file mode 100644
index 0000000000..a26ac762a4
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm
@@ -0,0 +1,268 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+
+ EXPORT __aeabi_uldivmod
+
+ AREA Uldivmod, CODE, READONLY
+
+;
+;UINT64
+;EFIAPI
+;__aeabi_uldivmod (
+; IN UINT64 Dividend
+; IN UINT64 Divisor
+; )
+;
+__aeabi_uldivmod
+ stmdb sp!, {r4, r5, r6, lr}
+ mov r4, r1
+ mov r5, r0
+ mov r6, #0 ; 0x0
+ orrs ip, r3, r2, lsr #31
+ bne __aeabi_uldivmod_label1
+ tst r2, r2
+ beq _ll_div0
+ movs ip, r2, lsr #15
+ addeq r6, r6, #16 ; 0x10
+ mov ip, r2, lsl r6
+ movs lr, ip, lsr #23
+ moveq ip, ip, lsl #8
+ addeq r6, r6, #8 ; 0x8
+ movs lr, ip, lsr #27
+ moveq ip, ip, lsl #4
+ addeq r6, r6, #4 ; 0x4
+ movs lr, ip, lsr #29
+ moveq ip, ip, lsl #2
+ addeq r6, r6, #2 ; 0x2
+ movs lr, ip, lsr #30
+ moveq ip, ip, lsl #1
+ addeq r6, r6, #1 ; 0x1
+ b _ll_udiv_small
+__aeabi_uldivmod_label1
+ tst r3, #-2147483648 ; 0x80000000
+ bne __aeabi_uldivmod_label2
+ movs ip, r3, lsr #15
+ addeq r6, r6, #16 ; 0x10
+ mov ip, r3, lsl r6
+ movs lr, ip, lsr #23
+ moveq ip, ip, lsl #8
+ addeq r6, r6, #8 ; 0x8
+ movs lr, ip, lsr #27
+ moveq ip, ip, lsl #4
+ addeq r6, r6, #4 ; 0x4
+ movs lr, ip, lsr #29
+ moveq ip, ip, lsl #2
+ addeq r6, r6, #2 ; 0x2
+ movs lr, ip, lsr #30
+ addeq r6, r6, #1 ; 0x1
+ rsb r3, r6, #32 ; 0x20
+ moveq ip, ip, lsl #1
+ orr ip, ip, r2, lsr r3
+ mov lr, r2, lsl r6
+ b _ll_udiv_big
+__aeabi_uldivmod_label2
+ mov ip, r3
+ mov lr, r2
+ b _ll_udiv_ginormous
+
+_ll_udiv_small
+ cmp r4, ip, lsl #1
+ mov r3, #0 ; 0x0
+ subcs r4, r4, ip, lsl #1
+ addcs r3, r3, #2 ; 0x2
+ cmp r4, ip
+ subcs r4, r4, ip
+ adcs r3, r3, #0 ; 0x0
+ add r2, r6, #32 ; 0x20
+ cmp r2, #32 ; 0x20
+ rsb ip, ip, #0 ; 0x0
+ bcc _ll_udiv_small_label1
+ orrs r0, r4, r5, lsr #30
+ moveq r4, r5
+ moveq r5, #0 ; 0x0
+ subeq r2, r2, #32 ; 0x20
+_ll_udiv_small_label1
+ mov r1, #0 ; 0x0
+ cmp r2, #16 ; 0x10
+ bcc _ll_udiv_small_label2
+ movs r0, r4, lsr #14
+ moveq r4, r4, lsl #16
+ addeq r1, r1, #16 ; 0x10
+_ll_udiv_small_label2
+ sub lr, r2, r1
+ cmp lr, #8 ; 0x8
+ bcc _ll_udiv_small_label3
+ movs r0, r4, lsr #22
+ moveq r4, r4, lsl #8
+ addeq r1, r1, #8 ; 0x8
+_ll_udiv_small_label3
+ rsb r0, r1, #32 ; 0x20
+ sub r2, r2, r1
+ orr r4, r4, r5, lsr r0
+ mov r5, r5, lsl r1
+ cmp r2, #1 ; 0x1
+ bcc _ll_udiv_small_label5
+ sub r2, r2, #1 ; 0x1
+ and r0, r2, #7 ; 0x7
+ eor r0, r0, #7 ; 0x7
+ adds r0, r0, r0, lsl #1
+ add pc, pc, r0, lsl #2
+ nop ; (mov r0,r0)
+_ll_udiv_small_label4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ sub r2, r2, #8 ; 0x8
+ tst r2, r2
+ rsbcc r4, ip, r4
+ bpl _ll_udiv_small_label4
+_ll_udiv_small_label5
+ mov r2, r4, lsr r6
+ bic r4, r4, r2, lsl r6
+ adcs r0, r5, r5
+ adc r1, r4, r4
+ add r1, r1, r3, lsl r6
+ mov r3, #0 ; 0x0
+ ldmia sp!, {r4, r5, r6, pc}
+
+_ll_udiv_big
+ subs r0, r5, lr
+ mov r3, #0 ; 0x0
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 ; 0x0
+ subs r0, r5, lr
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 ; 0x0
+ subs r0, r5, lr
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 ; 0x0
+ mov r1, #0 ; 0x0
+ rsbs lr, lr, #0 ; 0x0
+ rsc ip, ip, #0 ; 0x0
+ cmp r6, #16 ; 0x10
+ bcc _ll_udiv_big_label1
+ movs r0, r4, lsr #14
+ moveq r4, r4, lsl #16
+ addeq r1, r1, #16 ; 0x10
+_ll_udiv_big_label1
+ sub r2, r6, r1
+ cmp r2, #8 ; 0x8
+ bcc _ll_udiv_big_label2
+ movs r0, r4, lsr #22
+ moveq r4, r4, lsl #8
+ addeq r1, r1, #8 ; 0x8
+_ll_udiv_big_label2
+ rsb r0, r1, #32 ; 0x20
+ sub r2, r6, r1
+ orr r4, r4, r5, lsr r0
+ mov r5, r5, lsl r1
+ cmp r2, #1 ; 0x1
+ bcc _ll_udiv_big_label4
+ sub r2, r2, #1 ; 0x1
+ and r0, r2, #3 ; 0x3
+ rsb r0, r0, #3 ; 0x3
+ adds r0, r0, r0, lsl #1
+ add pc, pc, r0, lsl #3
+ nop ; (mov r0,r0)
+_ll_udiv_big_label3
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ sub r2, r2, #4 ; 0x4
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ tst r2, r2
+ movcs r5, r0
+ movcs r4, r1
+ bpl _ll_udiv_big_label3
+_ll_udiv_big_label4
+ mov r1, #0 ; 0x0
+ mov r2, r5, lsr r6
+ bic r5, r5, r2, lsl r6
+ adcs r0, r5, r5
+ adc r1, r1, #0 ; 0x0
+ movs lr, r3, lsl r6
+ mov r3, r4, lsr r6
+ bic r4, r4, r3, lsl r6
+ adc r1, r1, #0 ; 0x0
+ adds r0, r0, lr
+ orr r2, r2, r4, ror r6
+ adc r1, r1, #0 ; 0x0
+ ldmia sp!, {r4, r5, r6, pc}
+
+_ll_udiv_ginormous
+ subs r2, r5, lr
+ mov r1, #0 ; 0x0
+ sbcs r3, r4, ip
+ adc r0, r1, r1
+ movcc r2, r5
+ movcc r3, r4
+ ldmia sp!, {r4, r5, r6, pc}
+
+_ll_div0
+ ldmia sp!, {r4, r5, r6, lr}
+ mov r0, #0 ; 0x0
+ mov r1, #0 ; 0x0
+ b __aeabi_ldiv0
+
+__aeabi_ldiv0
+ BX r14
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
new file mode 100644
index 0000000000..6396036c04
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S
@@ -0,0 +1,30 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___umoddi3
+___umoddi3:
+ @ args = 0, pretend = 0, frame = 8
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ sub sp, sp, #16
+ add ip, sp, #8
+ str ip, [sp, #0]
+ bl ___udivmoddi4
+ ldrd r0, [sp, #8]
+ sub sp, r7, #0
+ ldmfd sp!, {r7, pc}
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.c
new file mode 100644
index 0000000000..73d796e499
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.c
@@ -0,0 +1,72 @@
+/** @file
+ Compiler intrinsic for 64-bit unsigned mod, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
+
+// Returns: a % b
+
+UINT64
+__umoddi3(UINT64 a, UINT64 b)
+{
+ UINT64 r;
+ __udivmoddi4(a, b, &r);
+ return r;
+}
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
new file mode 100644
index 0000000000..4cde76beb5
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S
@@ -0,0 +1,40 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+ .text
+ .align 2
+ .globl ___umodsi3
+___umodsi3:
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r7, lr}
+ add r7, sp, #8
+ mov r5, r0
+ mov r4, r1
+ bl L___udivsi3$stub
+ mul r0, r4, r0
+ rsb r0, r0, r5
+ ldmfd sp!, {r4, r5, r7, pc}
+ .section __TEXT,__symbol_stub4,symbol_stubs,none,12
+ .align 2
+L___udivsi3$stub:
+ .indirect_symbol ___udivsi3
+ ldr ip, L___udivsi3$slp
+ ldr pc, [ip, #0]
+L___udivsi3$slp:
+ .long L___udivsi3$lazy_ptr
+ .lazy_symbol_pointer
+L___udivsi3$lazy_ptr:
+ .indirect_symbol ___udivsi3
+ .long dyld_stub_binding_helper
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.c b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.c
new file mode 100644
index 0000000000..09d4008e78
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.c
@@ -0,0 +1,68 @@
+/** @file
+ Compiler intrinsic for 32-bit unsigned mod, ported from LLVM code.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+ University of Illinois/NCSA
+ Open Source License
+
+ Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+ All rights reserved.
+
+ Developed by:
+
+ LLVM Team
+
+ University of Illinois at Urbana-Champaign
+
+ http://llvm.org
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy of
+ this software and associated documentation files (the "Software"), to deal with
+ the Software without restriction, including without limitation the rights to
+ use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ of the Software, and to permit persons to whom the Software is furnished to do
+ so, subject to the following conditions:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimers.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimers in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the names of the LLVM Team, University of Illinois at
+ Urbana-Champaign, nor the names of its contributors may be used to
+ endorse or promote products derived from this Software without specific
+ prior written permission.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+ SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+
+// Returns: a % b
+
+UINT32
+__umodsi3(UINT32 a, UINT32 b)
+{
+ return a - (a / b) * b;
+}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm
new file mode 100644
index 0000000000..1d3d192821
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm
@@ -0,0 +1,38 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+
+ EXPORT __aeabi_uread4
+
+ AREA Uread4, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uread4 (
+; IN VOID *Pointer
+; );
+;
+__aeabi_uread4
+ ldrb r2, [r0, #1]
+ ldrb r1, [r0]
+ ldrb r3, [r0, #2]
+ ldrb r0, [r0, #3]
+ orr r1, r1, r2, lsl #8
+ orr r1, r1, r3, lsl #16
+ orr r0, r1, r0, lsl #24
+ bx lr
+
+ END
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm
new file mode 100644
index 0000000000..d6a1e2fb00
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_uwrite4
+
+ AREA Uwrite4, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uwrite4 (
+; IN UINT32 Data,
+; IN VOID *Pointer
+; );
+;
+;
+__aeabi_uwrite4
+ mov r2, r0, lsr #8
+ strb r0, [r1]
+ strb r2, [r1, #1]
+ mov r2, r0, lsr #16
+ strb r2, [r1, #2]
+ mov r2, r0, lsr #24
+ strb r2, [r1, #3]
+ bx lr
+
+ END
+
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
new file mode 100644
index 0000000000..b1429737c7
--- /dev/null
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
@@ -0,0 +1,92 @@
+#%HEADER%
+#/** @file
+# Base Library implementation.
+#
+# Copyright (c) 2009, Apple, Inc.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CompilerIntrinsicsLib
+ FILE_GUID = 855274FA-3575-4C20-9709-C031DC5589FA
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CompilerIntrinsicsLib
+
+
+[Sources.common]
+
+
+[Sources.ARM]
+ Arm/mullu.asm | RVCT
+ Arm/switch.asm | RVCT
+ Arm/llsr.asm | RVCT
+ Arm/memcpy.asm | RVCT
+ Arm/memcpy4.asm | RVCT
+ Arm/uread.asm | RVCT
+ Arm/uwrite.asm | RVCT
+ Arm/lasr.asm | RVCT
+ Arm/llsl.asm | RVCT
+ Arm/div.asm | RVCT
+ Arm/uldiv.asm | RVCT
+ Arm/ldivmod.asm | RVCT
+
+
+#
+# Move .c to .s to work around LLVM issues
+#
+# Arm/ashrdi3.c | GCC
+# Arm/ashldi3.c | GCC
+# Arm/divdi3.c | GCC
+# Arm/divsi3.c | GCC
+# Arm/lshrdi3.c | GCC
+ Arm/ashrdi3.S | GCC
+ Arm/ashldi3.S | GCC
+ Arm/divdi3.S | GCC
+ Arm/divsi3.S | GCC
+ Arm/lshrdi3.S | GCC
+
+ Arm/memcpy.S | GCC
+ Arm/memset.S | GCC
+
+# Arm/modsi3.c | GCC
+# Arm/moddi3.c | GCC
+# Arm/muldi3.c | GCC
+ Arm/modsi3.S | GCC
+ Arm/moddi3.S | GCC
+ Arm/muldi3.S | GCC
+
+# Arm/udivsi3.c | GCC
+# Arm/umodsi3.c | GCC
+# Arm/udivdi3.c | GCC
+# Arm/umoddi3.c | GCC
+# Arm/udivmoddi4.c | GCC
+ Arm/udivsi3.S | GCC
+ Arm/umodsi3.S | GCC
+ Arm/udivdi3.S | GCC
+ Arm/umoddi3.S | GCC
+ Arm/udivmoddi4.S | GCC
+
+# Arm/clzsi2.c | GCC
+# Arm/ctzsi2.c | GCC
+# Arm/ucmpdi2.c | GCC
+ Arm/switch8.S | GCC
+ Arm/switchu8.S | GCC
+ Arm/switch16.S | GCC
+ Arm/switch32.S | GCC
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+
diff --git a/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c b/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c
new file mode 100644
index 0000000000..61e3aac3c2
--- /dev/null
+++ b/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c
@@ -0,0 +1,258 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/** @file
+ UEFI Debug Library that uses PrintLib to send messages to STDERR.
+
+ Copyright (c) 2006 - 2007, Intel Corporation
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+//
+// Define the maximum debug and assert message length that this library supports
+//
+#define MAX_DEBUG_MESSAGE_LENGTH 0x100
+
+/**
+
+ Prints a debug message to the debug output device if the specified error level is enabled.
+
+ If any bit in ErrorLevel is also set in PcdDebugPrintErrorLevel, then print
+ the message specified by Format and the associated variable argument list to
+ the debug output device.
+
+ If Format is NULL, then ASSERT().
+
+ @param ErrorLevel The error level of the debug message.
+ @param Format Format string for the debug message to print.
+
+**/
+VOID
+EFIAPI
+DebugPrint (
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ ...
+ )
+{
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
+ VA_LIST Marker;
+
+ //
+ // If Format is NULL, then ASSERT().
+ //
+ ASSERT (Format != NULL);
+
+ //
+ // Check driver debug mask value and global mask
+ //
+ if ((ErrorLevel & PcdGet32(PcdDebugPrintErrorLevel)) == 0) {
+ return;
+ }
+
+ //
+ // Convert the DEBUG() message to a Unicode String
+ //
+ VA_START (Marker, Format);
+ AsciiVSPrint (AsciiBuffer, sizeof (AsciiBuffer), Format, Marker);
+ VA_END (Marker);
+
+ SemihostWriteString (AsciiBuffer);
+}
+
+
+/**
+
+ Prints an assert message containing a filename, line number, and description.
+ This may be followed by a breakpoint or a dead loop.
+
+ Print a message of the form "ASSERT (): \n"
+ to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
+ PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+ CpuDeadLoop() is called. If neither of these bits are set, then this function
+ returns immediately after the message is printed to the debug output device.
+ DebugAssert() must actively prevent recusrsion. If DebugAssert() is called while
+ processing another DebugAssert(), then DebugAssert() must return immediately.
+
+ If FileName is NULL, then a string of "(NULL) Filename" is printed.
+
+ If Description is NULL, then a string of "(NULL) Description" is printed.
+
+ @param FileName Pointer to the name of the source file that generated the assert condition.
+ @param LineNumber The line number in the source file that generated the assert condition
+ @param Description Pointer to the description of the assert condition.
+
+**/
+VOID
+EFIAPI
+DebugAssert (
+ IN CONST CHAR8 *FileName,
+ IN UINTN LineNumber,
+ IN CONST CHAR8 *Description
+ )
+{
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
+
+ //
+ // Generate the ASSERT() message in Unicode format
+ //
+ AsciiSPrint (AsciiBuffer, sizeof (AsciiBuffer), "ASSERT %a(%d): %a\n", FileName, LineNumber, Description);
+
+ SemihostWriteString (AsciiBuffer);
+
+ //
+ // Generate a Breakpoint, DeadLoop, or NOP based on PCD settings
+ //
+ if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
+ CpuBreakpoint ();
+ } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
+ CpuDeadLoop ();
+ }
+}
+
+
+/**
+
+ Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
+
+ This function fills Length bytes of Buffer with the value specified by
+ PcdDebugClearMemoryValue, and returns Buffer.
+
+ If Buffer is NULL, then ASSERT().
+
+ If Length is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT().
+
+ @param Buffer Pointer to the target buffer to fill with PcdDebugClearMemoryValue.
+ @param Length Number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
+
+ @return Buffer
+
+**/
+VOID *
+EFIAPI
+DebugClearMemory (
+ OUT VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ //
+ // If Buffer is NULL, then ASSERT().
+ //
+ ASSERT (Buffer != NULL);
+
+ //
+ // SetMem() checks for the the ASSERT() condition on Length and returns Buffer
+ //
+ return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
+}
+
+
+/**
+
+ Returns TRUE if ASSERT() macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugAssertEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
+}
+
+
+/**
+
+ Returns TRUE if DEBUG()macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugPrintEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
+}
+
+
+/**
+
+ Returns TRUE if DEBUG_CODE()macros are enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugCodeEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
+}
+
+
+/**
+
+ Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
+
+ This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of
+ PcdDebugProperyMask is set. Otherwise FALSE is returned.
+
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
+
+**/
+BOOLEAN
+EFIAPI
+DebugClearMemoryEnabled (
+ VOID
+ )
+{
+ return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
+}
diff --git a/ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf b/ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
new file mode 100644
index 0000000000..683f03f2f3
--- /dev/null
+++ b/ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
@@ -0,0 +1,46 @@
+#%HEADER%
+#/** @file
+# Debug Library for UEFI drivers
+#
+# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification
+# Copyright (c) 2007, Intel Corporation.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SemiHostingDebugLib
+ FILE_GUID = 2A8D3FC4-8DB1-4D27-A3F3-780AF03CF848
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = DebugLib|BASE SEC DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+
+
+[Sources.common]
+ DebugLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ PcdLib
+ PrintLib
+ SemihostLib
+
+[Pcd.common]
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask
+
diff --git a/ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf b/ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
new file mode 100644
index 0000000000..c0a540342a
--- /dev/null
+++ b/ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
@@ -0,0 +1,35 @@
+#%HEADER%
+#/** @file
+# Semihosting serail port lib
+#
+# Copyright (c) 2008, Apple Inc.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SemiHostingSerialPortLib
+ FILE_GUID = E9FB2D1E-05D9-421C-8C35-6100BB0093B7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+
+[Sources.common]
+ SerialPortLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ SemihostLib
diff --git a/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c b/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c
new file mode 100644
index 0000000000..df43f31413
--- /dev/null
+++ b/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c
@@ -0,0 +1,144 @@
+/** @file
+ Serial I/O Port library functions with no library constructor/destructor
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+
+
+/*
+
+ Programmed hardware of Serial port.
+
+ @return Always return EFI_UNSUPPORTED.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ if (SemihostConnectionSupported ()) {
+ return RETURN_SUCCESS;
+ } else {
+ return RETURN_UNSUPPORTED;
+ }
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be writed.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes writed to serial device.
+
+**/
+
+#define PRINT_BUFFER_SIZE 512
+#define PRINT_BUFFER_THRESHOLD (PRINT_BUFFER_SIZE - 4)
+
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINT8 PrintBuffer[PRINT_BUFFER_SIZE];
+ UINTN SourceIndex = 0;
+ UINTN DestinationIndex = 0;
+ UINT8 CurrentCharacter;
+
+ while (SourceIndex < NumberOfBytes)
+ {
+ CurrentCharacter = Buffer[SourceIndex++];
+
+ switch (CurrentCharacter)
+ {
+ case '\r':
+ continue;
+
+ case '\n':
+ PrintBuffer[DestinationIndex++] = ' ';
+ // fall through
+
+ default:
+ PrintBuffer[DestinationIndex++] = CurrentCharacter;
+ break;
+ }
+
+ if (DestinationIndex > PRINT_BUFFER_THRESHOLD)
+ {
+ PrintBuffer[DestinationIndex] = '\0';
+ SemihostWriteString ((CHAR8 *) PrintBuffer);
+
+ DestinationIndex = 0;
+ }
+ }
+
+ if (DestinationIndex > 0)
+ {
+ PrintBuffer[DestinationIndex] = '\0';
+ SemihostWriteString ((CHAR8 *) PrintBuffer);
+ }
+
+ return 0;
+}
+
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ @param Buffer Point of data buffer which need to be writed.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Aactual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ *Buffer = SemihostReadCharacter ();
+ return 1;
+}
+
+
+
+/**
+ Check to see if any data is avaiable to be read from the debug device.
+
+ @retval TRUE At least one byte of data is avaiable to be read
+ @retval FALS No data is avaiable to be read
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ // Since SemiHosting read character is blocking always say we have a char ready?
+ return SemihostConnectionSupported ();
+}
+
diff --git a/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c b/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c
new file mode 100644
index 0000000000..e1a515ef21
--- /dev/null
+++ b/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c
@@ -0,0 +1,221 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include
+
+#include
+#include
+
+#include "SemihostPrivate.h"
+
+BOOLEAN
+SemihostConnectionSupported (
+ VOID
+ )
+{
+ return SEMIHOST_SUPPORTED;
+}
+
+EFI_STATUS
+SemihostFileOpen (
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINT32 *FileHandle
+ )
+{
+ SEMIHOST_FILE_OPEN_BLOCK OpenBlock;
+ INT32 Result;
+
+ if (FileHandle == NULL)
+ return EFI_INVALID_PARAMETER;
+
+ OpenBlock.FileName = FileName;
+ OpenBlock.Mode = Mode;
+ OpenBlock.NameLength = AsciiStrLen(FileName);
+
+ Result = Semihost_SYS_OPEN(&OpenBlock);
+
+ if (Result == -1)
+ {
+ return EFI_NOT_FOUND;
+ }
+ else
+ {
+ *FileHandle = Result;
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+SemihostFileSeek (
+ IN UINT32 FileHandle,
+ IN UINT32 Offset
+ )
+{
+ SEMIHOST_FILE_SEEK_BLOCK SeekBlock;
+ INT32 Result;
+
+ SeekBlock.Handle = FileHandle;
+ SeekBlock.Location = Offset;
+
+ Result = Semihost_SYS_SEEK(&SeekBlock);
+
+ if (Result == 0)
+ return EFI_SUCCESS;
+ else
+ return EFI_ABORTED;
+}
+
+EFI_STATUS
+SemihostFileRead (
+ IN UINT32 FileHandle,
+ IN OUT UINT32 *Length,
+ OUT VOID *Buffer
+ )
+{
+ SEMIHOST_FILE_READ_WRITE_BLOCK ReadBlock;
+ UINT32 Result;
+
+ if ((Length == NULL) || (Buffer == NULL))
+ return EFI_INVALID_PARAMETER;
+
+ ReadBlock.Handle = FileHandle;
+ ReadBlock.Buffer = Buffer;
+ ReadBlock.Length = *Length;
+
+ Result = Semihost_SYS_READ(&ReadBlock);
+
+ if (Result == *Length)
+ {
+ return EFI_ABORTED;
+ }
+ else
+ {
+ *Length -= Result;
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+SemihostFileWrite (
+ IN UINT32 FileHandle,
+ IN OUT UINT32 *Length,
+ IN VOID *Buffer
+ )
+{
+ SEMIHOST_FILE_READ_WRITE_BLOCK WriteBlock;
+
+ if ((Length == NULL) || (Buffer == NULL))
+ return EFI_INVALID_PARAMETER;
+
+ WriteBlock.Handle = FileHandle;
+ WriteBlock.Buffer = Buffer;
+ WriteBlock.Length = *Length;
+
+ *Length = Semihost_SYS_WRITE(&WriteBlock);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SemihostFileClose (
+ IN UINT32 FileHandle
+ )
+{
+ INT32 Result = Semihost_SYS_CLOSE(&FileHandle);
+
+ if (Result == -1)
+ return EFI_INVALID_PARAMETER;
+ else
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SemihostFileLength (
+ IN UINT32 FileHandle,
+ OUT UINT32 *Length
+ )
+{
+ INT32 Result;
+
+ if (Length == NULL)
+ return EFI_INVALID_PARAMETER;
+
+ Result = Semihost_SYS_FLEN(&FileHandle);
+
+ if (Result == -1)
+ {
+ return EFI_ABORTED;
+ }
+ else
+ {
+ *Length = Result;
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+SemihostFileRemove (
+ IN CHAR8 *FileName
+ )
+{
+ SEMIHOST_FILE_REMOVE_BLOCK RemoveBlock;
+ UINT32 Result;
+
+ RemoveBlock.FileName = FileName;
+ RemoveBlock.NameLength = AsciiStrLen(FileName);
+
+ Result = Semihost_SYS_REMOVE(&RemoveBlock);
+
+ if (Result == 0)
+ return EFI_SUCCESS;
+ else
+ return EFI_ABORTED;
+}
+
+CHAR8
+SemihostReadCharacter (
+ VOID
+ )
+{
+ return Semihost_SYS_READC();
+}
+
+VOID
+SemihostWriteCharacter (
+ IN CHAR8 Character
+ )
+{
+ Semihost_SYS_WRITEC(&Character);
+}
+
+VOID
+SemihostWriteString (
+ IN CHAR8 *String
+ )
+{
+ Semihost_SYS_WRITE0(String);
+}
+
+UINT32
+SemihostSystem (
+ IN CHAR8 *CommandLine
+ )
+{
+ SEMIHOST_SYSTEM_BLOCK SystemBlock;
+
+ SystemBlock.CommandLine = CommandLine;
+ SystemBlock.CommandLength = AsciiStrLen(CommandLine);
+
+ return Semihost_SYS_SYSTEM(&SystemBlock);
+}
diff --git a/ArmPkg/Library/SemihostLib/Arm/SemihostPrivate.h b/ArmPkg/Library/SemihostLib/Arm/SemihostPrivate.h
new file mode 100644
index 0000000000..e82111430a
--- /dev/null
+++ b/ArmPkg/Library/SemihostLib/Arm/SemihostPrivate.h
@@ -0,0 +1,162 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SEMIHOST_PRIVATE_H__
+#define __SEMIHOST_PRIVATE_H__
+
+typedef struct {
+ CHAR8 *FileName;
+ UINT32 Mode;
+ UINT32 NameLength;
+} SEMIHOST_FILE_OPEN_BLOCK;
+
+typedef struct {
+ UINT32 Handle;
+ VOID *Buffer;
+ UINT32 Length;
+} SEMIHOST_FILE_READ_WRITE_BLOCK;
+
+typedef struct {
+ UINT32 Handle;
+ UINT32 Location;
+} SEMIHOST_FILE_SEEK_BLOCK;
+
+typedef struct {
+ CHAR8 *FileName;
+ UINT32 NameLength;
+} SEMIHOST_FILE_REMOVE_BLOCK;
+
+typedef struct {
+ CHAR8 *CommandLine;
+ UINT32 CommandLength;
+} SEMIHOST_SYSTEM_BLOCK;
+
+#ifdef __CC_ARM
+
+#if defined(__thumb__)
+#define SWI 0xAB
+#else
+#define SWI 0x123456
+#endif
+
+#define SEMIHOST_SUPPORTED TRUE
+
+__swi(SWI)
+INT32
+_Semihost_SYS_OPEN(
+ IN UINTN SWI_0x01,
+ IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock
+ );
+
+__swi(SWI)
+INT32
+_Semihost_SYS_CLOSE(
+ IN UINTN SWI_0x02,
+ IN UINT32 *Handle
+ );
+
+__swi(SWI)
+VOID
+_Semihost_SYS_WRITEC(
+ IN UINTN SWI_0x03,
+ IN CHAR8 *Character
+ );
+
+__swi(SWI)
+VOID
+_Semihost_SYS_WRITE0(
+ IN UINTN SWI_0x04,
+ IN CHAR8 *String
+ );
+
+__swi(SWI)
+UINT32
+_Semihost_SYS_WRITE(
+ IN UINTN SWI_0x05,
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock
+ );
+
+__swi(SWI)
+UINT32
+_Semihost_SYS_READ(
+ IN UINTN SWI_0x06,
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock
+ );
+
+__swi(SWI)
+CHAR8
+_Semihost_SYS_READC(
+ IN UINTN SWI_0x07,
+ IN UINTN Zero
+ );
+
+__swi(SWI)
+INT32
+_Semihost_SYS_SEEK(
+ IN UINTN SWI_0x0A,
+ IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock
+ );
+
+__swi(SWI)
+INT32
+_Semihost_SYS_FLEN(
+ IN UINTN SWI_0x0C,
+ IN UINT32 *Handle
+ );
+
+__swi(SWI)
+UINT32
+_Semihost_SYS_REMOVE(
+ IN UINTN SWI_0x0E,
+ IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock
+ );
+
+__swi(SWI)
+UINT32
+_Semihost_SYS_SYSTEM(
+ IN UINTN SWI_0x12,
+ IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
+ );
+
+#define Semihost_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)
+#define Semihost_SYS_CLOSE(Handle) _Semihost_SYS_CLOSE(0x02, Handle)
+#define Semihost_SYS_WRITE0(String) _Semihost_SYS_WRITE0(0x04, String)
+#define Semihost_SYS_WRITEC(Character) _Semihost_SYS_WRITEC(0x03, Character)
+#define Semihost_SYS_WRITE(WriteBlock) _Semihost_SYS_WRITE(0x05, WriteBlock)
+#define Semihost_SYS_READ(ReadBlock) _Semihost_SYS_READ(0x06, ReadBlock)
+#define Semihost_SYS_READC() _Semihost_SYS_READC(0x07, 0)
+#define Semihost_SYS_SEEK(SeekBlock) _Semihost_SYS_SEEK(0x0A, SeekBlock)
+#define Semihost_SYS_FLEN(Handle) _Semihost_SYS_FLEN(0x0C, Handle)
+#define Semihost_SYS_REMOVE(RemoveBlock) _Semihost_SYS_REMOVE(0x0E, RemoveBlock)
+#define Semihost_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)
+
+#else // __CC_ARM
+
+#define SEMIHOST_SUPPORTED FALSE
+
+#define Semihost_SYS_OPEN(OpenBlock) (-1)
+#define Semihost_SYS_CLOSE(Handle) (-1)
+#define Semihost_SYS_WRITE0(String)
+#define Semihost_SYS_WRITEC(Character)
+#define Semihost_SYS_WRITE(WriteBlock) (0)
+#define Semihost_SYS_READ(ReadBlock) ((ReadBlock)->Length)
+#define Semihost_SYS_READC() ('x')
+#define Semihost_SYS_SEEK(SeekBlock) (-1)
+#define Semihost_SYS_FLEN(Handle) (-1)
+#define Semihost_SYS_REMOVE(RemoveBlock) (-1)
+#define Semihost_SYS_SYSTEM(SystemBlock) (-1)
+
+#endif // __CC_ARM
+
+#endif //__SEMIHOST_PRIVATE_H__
diff --git a/ArmPkg/Library/SemihostLib/SemihostLib.inf b/ArmPkg/Library/SemihostLib/SemihostLib.inf
new file mode 100644
index 0000000000..cb278083c0
--- /dev/null
+++ b/ArmPkg/Library/SemihostLib/SemihostLib.inf
@@ -0,0 +1,32 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SemihostLib
+ FILE_GUID = C40D08BA-DB7B-4F07-905A-C5FE4B5AF987
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SemihostLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = ARM
+#
+[Sources.ARM]
+ Arm/SemihostLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ BaseLib
+
+[Protocols]
+
+[Guids]
+
+[Pcd]
+
\ No newline at end of file
diff --git a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
new file mode 100644
index 0000000000..060ba6bf98
--- /dev/null
+++ b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
@@ -0,0 +1,626 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+EFI_PHYSICAL_ADDRESS
+ConvertToPhysicalAddress (
+ IN VOID *VirtualAddress
+ )
+{
+ UINTN UncachedMemoryMask = (UINTN)PcdGet64(PcdArmUncachedMemoryMask);
+ UINTN PhysicalAddress;
+
+ PhysicalAddress = (UINTN)VirtualAddress & ~UncachedMemoryMask;
+
+ return (EFI_PHYSICAL_ADDRESS)PhysicalAddress;
+}
+
+VOID *
+ConvertToCachedAddress (
+ IN VOID *Address
+ )
+{
+ return (VOID *)(UINTN)ConvertToPhysicalAddress(Address);
+}
+
+VOID *
+ConvertToUncachedAddress (
+ IN VOID *Address
+ )
+{
+ UINTN UncachedMemoryMask = (UINTN)PcdGet64(PcdArmUncachedMemoryMask);
+ UINTN UncachedAddress;
+
+ UncachedAddress = (UINTN)Address | UncachedMemoryMask;
+
+ return (VOID *)UncachedAddress;
+}
+
+VOID
+FlushCache (
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINTN Size
+ )
+{
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = Cpu->FlushDataCache(Cpu, Address, Size, EfiCpuFlushTypeWriteBackInvalidate);
+ ASSERT_EFI_ERROR(Status);
+}
+
+VOID *
+UncachedInternalAllocatePages (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS Memory;
+
+ if (Pages == 0) {
+ return NULL;
+ }
+
+ Status = gBS->AllocatePages (AllocateAnyPages, MemoryType, Pages, &Memory);
+ if (EFI_ERROR (Status)) {
+ Memory = 0;
+ }
+
+ if (Memory != 0) {
+ FlushCache(Memory, EFI_PAGES_TO_SIZE(Pages));
+ Memory = (EFI_PHYSICAL_ADDRESS)(UINTN)ConvertToUncachedAddress((VOID *)(UINTN)Memory);
+ }
+
+ return (VOID *) (UINTN) Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocatePages (
+ IN UINTN Pages
+ )
+{
+ return UncachedInternalAllocatePages (EfiBootServicesData, Pages);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimePages (
+ IN UINTN Pages
+ )
+{
+ return UncachedInternalAllocatePages (EfiRuntimeServicesData, Pages);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedPages (
+ IN UINTN Pages
+ )
+{
+ return UncachedInternalAllocatePages (EfiReservedMemoryType, Pages);
+}
+
+VOID
+EFIAPI
+UncachedFreePages (
+ IN VOID *Buffer,
+ IN UINTN Pages
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT (Pages != 0);
+
+ Buffer = ConvertToCachedAddress(Buffer);
+
+ Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);
+ ASSERT_EFI_ERROR (Status);
+}
+
+VOID *
+UncachedInternalAllocateAlignedPages (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ IN UINTN Alignment
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS Memory;
+ UINTN AlignedMemory;
+ UINTN AlignmentMask;
+ UINTN UnalignedPages;
+ UINTN RealPages;
+
+ //
+ // Alignment must be a power of two or zero.
+ //
+ ASSERT ((Alignment & (Alignment - 1)) == 0);
+
+ if (Pages == 0) {
+ return NULL;
+ }
+ if (Alignment > EFI_PAGE_SIZE) {
+ //
+ // Caculate the total number of pages since alignment is larger than page size.
+ //
+ AlignmentMask = Alignment - 1;
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
+ //
+ // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
+ //
+ ASSERT (RealPages > Pages);
+
+ Status = gBS->AllocatePages (AllocateAnyPages, MemoryType, RealPages, &Memory);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+ AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
+ if (UnalignedPages > 0) {
+ //
+ // Free first unaligned page(s).
+ //
+ Status = gBS->FreePages (Memory, UnalignedPages);
+ ASSERT_EFI_ERROR (Status);
+ }
+ Memory = (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_TO_SIZE (Pages));
+ UnalignedPages = RealPages - Pages - UnalignedPages;
+ if (UnalignedPages > 0) {
+ //
+ // Free last unaligned page(s).
+ //
+ Status = gBS->FreePages (Memory, UnalignedPages);
+ ASSERT_EFI_ERROR (Status);
+ }
+ } else {
+ //
+ // Do not over-allocate pages in this case.
+ //
+ Status = gBS->AllocatePages (AllocateAnyPages, MemoryType, Pages, &Memory);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+ AlignedMemory = (UINTN) Memory;
+ }
+
+ if (AlignedMemory != 0) {
+ FlushCache(AlignedMemory, EFI_PAGES_TO_SIZE(Pages));
+ AlignedMemory = (UINTN)ConvertToUncachedAddress((VOID *)AlignedMemory);
+ }
+
+ return (VOID *) AlignedMemory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedPages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedPages (EfiBootServicesData, Pages, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedPages (EfiRuntimeServicesData, Pages, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPages (
+ IN UINTN Pages,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedPages (EfiReservedMemoryType, Pages, Alignment);
+}
+
+VOID
+EFIAPI
+UncachedFreeAlignedPages (
+ IN VOID *Buffer,
+ IN UINTN Pages
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT (Pages != 0);
+
+ Buffer = ConvertToCachedAddress(Buffer);
+
+ Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);
+ ASSERT_EFI_ERROR (Status);
+}
+
+VOID *
+UncachedInternalAllocateAlignedPool (
+ IN EFI_MEMORY_TYPE PoolType,
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ VOID *RawAddress;
+ UINTN AlignedAddress;
+ UINTN AlignmentMask;
+ UINTN OverAllocationSize;
+ UINTN RealAllocationSize;
+ VOID **FreePointer;
+ UINTN DataCacheLineLength;
+ EFI_STATUS Status;
+
+ //
+ // Alignment must be a power of two or zero.
+ //
+ ASSERT ((Alignment & (Alignment - 1)) == 0);
+
+ DataCacheLineLength = ArmDataCacheLineLength();
+
+ // Alignment must be at least cache-line aligned
+ if (Alignment < DataCacheLineLength) {
+ Alignment = DataCacheLineLength;
+ }
+
+ if (Alignment == 0) {
+ AlignmentMask = Alignment;
+ } else {
+ AlignmentMask = Alignment - 1;
+ }
+
+ //
+ // Calculate the extra memory size, over-allocate memory pool and get the aligned memory address.
+ //
+ OverAllocationSize = sizeof (RawAddress) + AlignmentMask;
+ RealAllocationSize = AllocationSize + OverAllocationSize;
+ //
+ // Make sure that AllocationSize plus OverAllocationSize does not overflow.
+ //
+ ASSERT (RealAllocationSize > AllocationSize);
+
+ Status = gBS->AllocatePool (PoolType, RealAllocationSize, &RawAddress);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ AlignedAddress = ((UINTN) RawAddress + OverAllocationSize) & ~AlignmentMask;
+ //
+ // Save the original memory address just before the aligned address.
+ //
+ FreePointer = (VOID **)(AlignedAddress - sizeof (RawAddress));
+ *FreePointer = RawAddress;
+
+ if (AlignedAddress != 0) {
+ FlushCache(AlignedAddress, AllocationSize);
+ AlignedAddress = (UINTN)ConvertToUncachedAddress((VOID *)AlignedAddress);
+ }
+
+ return (VOID *) AlignedAddress;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedPool (EfiBootServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedPool (EfiRuntimeServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedPool (EfiReservedMemoryType, AllocationSize, Alignment);
+}
+
+VOID *
+UncachedInternalAllocateAlignedZeroPool (
+ IN EFI_MEMORY_TYPE PoolType,
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ VOID *Memory;
+ Memory = UncachedInternalAllocateAlignedPool (PoolType, AllocationSize, Alignment);
+ if (Memory != NULL) {
+ Memory = ZeroMem (Memory, AllocationSize);
+ }
+ return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedZeroPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedZeroPool (EfiBootServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeZeroPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedZeroPool (EfiRuntimeServicesData, AllocationSize, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedZeroPool (
+ IN UINTN AllocationSize,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedZeroPool (EfiReservedMemoryType, AllocationSize, Alignment);
+}
+
+VOID *
+UncachedInternalAllocateAlignedCopyPool (
+ IN EFI_MEMORY_TYPE PoolType,
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ )
+{
+ VOID *Memory;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));
+
+ Memory = UncachedInternalAllocateAlignedPool (PoolType, AllocationSize, Alignment);
+ if (Memory != NULL) {
+ Memory = CopyMem (Memory, Buffer, AllocationSize);
+ }
+ return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedCopyPool (EfiBootServicesData, AllocationSize, Buffer, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedCopyPool (EfiRuntimeServicesData, AllocationSize, Buffer, Alignment);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer,
+ IN UINTN Alignment
+ )
+{
+ return UncachedInternalAllocateAlignedCopyPool (EfiReservedMemoryType, AllocationSize, Buffer, Alignment);
+}
+
+VOID
+EFIAPI
+UncachedFreeAlignedPool (
+ IN VOID *Buffer
+ )
+{
+ VOID *RawAddress;
+ VOID **FreePointer;
+ EFI_STATUS Status;
+
+ Buffer = ConvertToCachedAddress(Buffer);
+
+ //
+ // Get the pre-saved original address in the over-allocate pool.
+ //
+ FreePointer = (VOID **)((UINTN) Buffer - sizeof (RawAddress));
+ RawAddress = *FreePointer;
+
+ Status = gBS->FreePool (RawAddress);
+ ASSERT_EFI_ERROR (Status);
+}
+
+VOID *
+UncachedInternalAllocatePool (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN AllocationSize
+ )
+{
+ UINTN CacheLineLength = ArmDataCacheLineLength();
+ return UncachedInternalAllocateAlignedPool(MemoryType, AllocationSize, CacheLineLength);
+}
+
+VOID *
+EFIAPI
+UncachedAllocatePool (
+ IN UINTN AllocationSize
+ )
+{
+ return UncachedInternalAllocatePool (EfiBootServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimePool (
+ IN UINTN AllocationSize
+ )
+{
+ return UncachedInternalAllocatePool (EfiRuntimeServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedPool (
+ IN UINTN AllocationSize
+ )
+{
+ return UncachedInternalAllocatePool (EfiReservedMemoryType, AllocationSize);
+}
+
+VOID *
+UncachedInternalAllocateZeroPool (
+ IN EFI_MEMORY_TYPE PoolType,
+ IN UINTN AllocationSize
+ )
+{
+ VOID *Memory;
+
+ Memory = UncachedInternalAllocatePool (PoolType, AllocationSize);
+ if (Memory != NULL) {
+ Memory = ZeroMem (Memory, AllocationSize);
+ }
+ return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateZeroPool (
+ IN UINTN AllocationSize
+ )
+{
+ return UncachedInternalAllocateZeroPool (EfiBootServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimeZeroPool (
+ IN UINTN AllocationSize
+ )
+{
+ return UncachedInternalAllocateZeroPool (EfiRuntimeServicesData, AllocationSize);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedZeroPool (
+ IN UINTN AllocationSize
+ )
+{
+ return UncachedInternalAllocateZeroPool (EfiReservedMemoryType, AllocationSize);
+}
+
+VOID *
+UncachedInternalAllocateCopyPool (
+ IN EFI_MEMORY_TYPE PoolType,
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ )
+{
+ VOID *Memory;
+
+ ASSERT (Buffer != NULL);
+ ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));
+
+ Memory = UncachedInternalAllocatePool (PoolType, AllocationSize);
+ if (Memory != NULL) {
+ Memory = CopyMem (Memory, Buffer, AllocationSize);
+ }
+ return Memory;
+}
+
+VOID *
+EFIAPI
+UncachedAllocateCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ )
+{
+ return UncachedInternalAllocateCopyPool (EfiBootServicesData, AllocationSize, Buffer);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateRuntimeCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ )
+{
+ return UncachedInternalAllocateCopyPool (EfiRuntimeServicesData, AllocationSize, Buffer);
+}
+
+VOID *
+EFIAPI
+UncachedAllocateReservedCopyPool (
+ IN UINTN AllocationSize,
+ IN CONST VOID *Buffer
+ )
+{
+ return UncachedInternalAllocateCopyPool (EfiReservedMemoryType, AllocationSize, Buffer);
+}
+
+VOID
+EFIAPI
+UncachedFreePool (
+ IN VOID *Buffer
+ )
+{
+ UncachedFreeAlignedPool(Buffer);
+}
+
+VOID
+EFIAPI
+UncachedSafeFreePool (
+ IN VOID *Buffer
+ )
+{
+ if (Buffer != NULL) {
+ UncachedFreePool (Buffer);
+ Buffer = NULL;
+ }
+}
+
diff --git a/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
new file mode 100644
index 0000000000..1a62eb4231
--- /dev/null
+++ b/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
@@ -0,0 +1,25 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UncachedMemoryAllocationLib
+ FILE_GUID = DC101A1A-7525-429B-84AF-EEAA630E576C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = UncachedMemoryAllocationLib
+
+[Sources.common]
+ UncachedMemoryAllocationLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+
+[Protocols]
+ gEfiCpuArchProtocolGuid
+
+[LibraryClasses]
+ ArmLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask
+
\ No newline at end of file
diff --git a/BeagleBoardPkg/AppleBeagleBoardPkg.dsc b/BeagleBoardPkg/AppleBeagleBoardPkg.dsc
new file mode 100644
index 0000000000..251e8d563e
--- /dev/null
+++ b/BeagleBoardPkg/AppleBeagleBoardPkg.dsc
@@ -0,0 +1,366 @@
+#/** @file
+# Beagle board package.
+#
+# Copyright (c) 2009, Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = AppleBeagleBoardPkg
+ PLATFORM_GUID = 1C1D4FD7-703A-4DD5-A97B-FB794921859E
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/AppleBeagleBoard
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = BeagleBoardPkg/AppleBeagleBoardPkg.fdf
+
+
+[LibraryClasses.common]
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ BeagleBoardSystemLib|BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf
+ EfiResetSystemLib|BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
+
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
+ EblCmdLib|BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf
+
+ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+
+
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+
+ SerialPortLib|BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+ RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
+
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+
+#
+# Assume everything is fixed at build
+#
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ UsbLib|AppleCommonPkg/Library/AppleUsbLib/AppleUsbDxeLib.inf
+ EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+ TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
+ OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
+ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+ GdbSerialLib|BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[BuildOptions]
+ XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv6 -march=armv6
+ XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv6
+ XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv6
+
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ #
+ # Control what commands are supported from the UI
+ # Turn these on and off to add features or save size
+ #
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+
+ #
+ # Beagle board Specific PCDs
+ #
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"AppleEFI"
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0
+ gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0
+ gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
+
+#
+# Optional feature to help prevent EFI memory map fragments
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+# Values are in EFI Pages (4K). DXE Core will make sure that
+# at least this much of each type of memory can be allocated
+# from a single memory range. This way you only end up with
+# maximum of two fragements for each type in the memory map
+# (the memory used, and the free memory that was prereserved
+# but not used).
+#
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+
+#
+# Beagle board Specific PCDs
+#
+ gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
+ gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
+ gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
+
+ gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x6E000000
+ gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x4809C000
+
+ # Console
+ gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3
+
+ # Timers
+# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3
+ gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3
+# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4
+ gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|77
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|13000000
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+#
+# SEC
+#
+ BeagleBoardPkg/Sec/Sec.inf
+
+#
+# DXE
+#
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ EnhancedFat/FatDxe/FatDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB
+ #
+ BeagleBoardPkg/PciEmulation/PciEmulation.inf
+ AppleCommonPkg/Bus/Pci/EhciDxe/Ehci.inf
+ AppleCommonPkg/Bus/Usb/UsbBotDxe/UsbBot.inf
+ AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi0/UsbCbi0.inf
+ AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi1/UsbCbi1.inf
+ AppleCommonPkg/Bus/Usb/UsbBusDxe/UsbBus.inf
+ AppleCommonPkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorage.inf
+
+ #NOTE: Open source EHCI stack doesn't work on Beagleboard.
+ #NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
+ #MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ #MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ #MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Nand Flash
+ #
+ BeagleBoardPkg/Flash/Flash.inf
+
+ #
+ # MMC/SD
+ #
+ BeagleBoardPkg/MMCHSDxe/MMCHS.inf
+
+ #
+ # I2C
+ #
+ BeagleBoardPkg/SmbusDxe/Smbus.inf
+
+ #
+ # SoC Drivers
+ #
+ BeagleBoardPkg/Gpio/Gpio.inf
+ BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
+ BeagleBoardPkg/TimerDxe/TimerDxe.inf
+
+ #
+ # Power IC
+ #
+ BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
+
+ #
+ # Application
+ #
+ EmbeddedPkg/Ebl/Ebl.inf
+
+ #
+ # Bds
+ #
+ BeagleBoardPkg/Bds/Bds.inf
+
+ #
+ # Gdb Stub
+ #
+ EmbeddedPkg/GdbStub/GdbStub.inf
+ ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
+
diff --git a/BeagleBoardPkg/AppleBeagleBoardPkg.fdf b/BeagleBoardPkg/AppleBeagleBoardPkg.fdf
new file mode 100644
index 0000000000..9852dfdd3f
--- /dev/null
+++ b/BeagleBoardPkg/AppleBeagleBoardPkg.fdf
@@ -0,0 +1,303 @@
+# FLASH layout file for Beagle board.
+#
+# Copyright (c) 2009, Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+
+[FD.BeagleBoard_EFI]
+BaseAddress = 0x80008000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00080000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x40
+NumBlocks = 0x2000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType
+#
+################################################################################
+
+# 512 bytes of configuration header & 8 bytes of image header
+0x00000000|0x00000208
+
+0x00000208|0x0007FDF8
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0x9000
+FvAlignment = 8 #FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Nand Flash
+ #
+ INF BeagleBoardPkg/Flash/Flash.inf
+
+ #
+ # MMC/SD
+ #
+ INF BeagleBoardPkg/MMCHSDxe/MMCHS.inf
+
+ #
+ # I2C
+ #
+ INF BeagleBoardPkg/SmbusDxe/Smbus.inf
+
+ #
+ # SoC Drivers
+ #
+ INF BeagleBoardPkg/Gpio/Gpio.inf
+ INF BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
+ INF BeagleBoardPkg/TimerDxe/TimerDxe.inf
+
+ #
+ # Power IC
+ #
+ INF BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF EnhancedFat/FatDxe/FatDxe.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB Support
+ #
+
+ INF BeagleBoardPkg/PciEmulation/PciEmulation.inf
+ INF AppleCommonPkg/Bus/Pci/EhciDxe/Ehci.inf
+ INF AppleCommonPkg/Bus/Usb/UsbBotDxe/UsbBot.inf
+ INF AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi0/UsbCbi0.inf
+ INF AppleCommonPkg/Bus/Usb/UsbCbiDxe/Cbi1/UsbCbi1.inf
+ INF AppleCommonPkg/Bus/Usb/UsbBusDxe/UsbBus.inf
+ INF AppleCommonPkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorage.inf
+
+
+ #NOTE: Open source EHCI stack doesn't work on Beagleboard.
+ #NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
+ #INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ #INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ #INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+
+ #
+ # Bds
+ #
+ INF BeagleBoardPkg/Bds/Bds.inf
+
+ #
+ # Gdb Stub
+ #
+ #INF ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
+ #INF ApplePkg/Universal/GdbStub/GdbStub.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF BeagleBoardPkg/Sec/Sec.inf
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional |.depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 |.efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 8 |.efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE |.efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 |.efi
+ }
diff --git a/BeagleBoardPkg/Bds/Bds.inf b/BeagleBoardPkg/Bds/Bds.inf
new file mode 100644
index 0000000000..18e019147b
--- /dev/null
+++ b/BeagleBoardPkg/Bds/Bds.inf
@@ -0,0 +1,70 @@
+#%HEADER%
+#/** @file
+#
+# Component discription file for Bds module
+#
+# Copyright (c) 2009 Apple, Inc. All rights reserved.
+#
+# This document is the property of Apple, Inc.
+# It is considered confidential and proprietary.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Apple, Inc.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardBds
+ FILE_GUID = 934431fe-5745-402e-913d-17b4434eb0f3
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = BdsInitialize
+
+[Sources.common]
+ BdsEntry.c
+ FirmwareVolume.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ DevicePathLib
+ BaseLib
+ HobLib
+ UefiRuntimeServicesTableLib
+ ReportStatusCodeLib
+ PerformanceLib
+ DxeServicesTableLib
+ MemoryAllocationLib
+ UefiLib
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ PrintLib
+ UefiDriverEntryPoint
+
+[Guids]
+
+
+[Protocols]
+ gEfiBdsArchProtocolGuid
+ gEfiSimpleTextInProtocolGuid
+ gEfiSimpleTextOutProtocolGuid
+ gEfiSerialIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiSimpleFileSystemProtocolGuid
+ gEfiUsbIoProtocolGuid
+ gEfiFirmwareVolume2ProtocolGuid
+
+
+[FeaturePcd]
+
+[FixedPcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
+
+[Depex]
+ TRUE
diff --git a/BeagleBoardPkg/Bds/BdsEntry.c b/BeagleBoardPkg/Bds/BdsEntry.c
new file mode 100644
index 0000000000..05afd190dd
--- /dev/null
+++ b/BeagleBoardPkg/Bds/BdsEntry.c
@@ -0,0 +1,240 @@
+/** @file
+ The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements
+ of the UEFI specification as it is designed to implement an embedded systmes
+ propriatary boot scheme.
+
+ This template assume a DXE driver produces a SerialIo protocol not using the EFI
+ driver module and it will attempt to connect a console on top of this.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "BdsEntry.h"
+
+
+BOOLEAN gConsolePresent = FALSE;
+
+
+EFI_HANDLE mBdsImageHandle = NULL;
+EFI_BDS_ARCH_PROTOCOL gBdsProtocol = {
+ BdsEntry,
+};
+
+
+
+
+/**
+ This function uses policy data from the platform to determine what operating
+ system or system utility should be loaded and invoked. This function call
+ also optionally make the use of user input to determine the operating system
+ or system utility to be loaded and invoked. When the DXE Core has dispatched
+ all the drivers on the dispatch queue, this function is called. This
+ function will attempt to connect the boot devices required to load and invoke
+ the selected operating system or system utility. During this process,
+ additional firmware volumes may be discovered that may contain addition DXE
+ drivers that can be dispatched by the DXE Core. If a boot device cannot be
+ fully connected, this function calls the DXE Service Dispatch() to allow the
+ DXE drivers from any newly discovered firmware volumes to be dispatched.
+ Then the boot device connection can be attempted again. If the same boot
+ device connection operation fails twice in a row, then that boot device has
+ failed, and should be skipped. This function should never return.
+
+ @param This The EFI_BDS_ARCH_PROTOCOL instance.
+
+ @return None.
+
+**/
+VOID
+EFIAPI
+BdsEntry (
+ IN EFI_BDS_ARCH_PROTOCOL *This
+ )
+{
+ EFI_STATUS Status;
+ UINTN NoHandles;
+ EFI_HANDLE *Buffer;
+ EFI_HANDLE FvHandle;
+ EFI_HANDLE ImageHandle;
+ EFI_HANDLE UsbDeviceHandle;
+ EFI_GUID NameGuid;
+ UINTN Size;
+ UINTN HandleCount;
+ UINTN OldHandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ EFI_DEVICE_PATH_PROTOCOL *LoadImageDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *FileSystemDevicePath;
+
+ //
+ // Now do the EFI stuff
+ //
+ Size = 0x100;
+ gST->FirmwareVendor = AllocateRuntimePool (Size);
+ ASSERT (gST->FirmwareVendor != NULL);
+
+ UnicodeSPrint (gST->FirmwareVendor, Size, L"BeagleBoard EFI %a %a", __DATE__, __TIME__);
+
+ //
+ // Now we need to setup the EFI System Table with information about the console devices.
+ // This code is normally in the console spliter driver on platforms that support multiple
+ // consoles at the same time
+ //
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextOutProtocolGuid, NULL, &NoHandles, &Buffer);
+ if (!EFI_ERROR (Status)) {
+ // Use the first SimpleTextOut we find and update the EFI System Table
+ gST->ConsoleOutHandle = Buffer[0];
+ gST->StandardErrorHandle = Buffer[0];
+ Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextOutProtocolGuid, (VOID **)&gST->ConOut);
+ ASSERT_EFI_ERROR (Status);
+
+ gST->StdErr = gST->ConOut;
+
+ gST->ConOut->OutputString (gST->ConOut, L"BDS: Console Started!!!!\n\r");
+ FreePool (Buffer);
+
+ gConsolePresent = TRUE;
+ }
+
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextInProtocolGuid, NULL, &NoHandles, &Buffer);
+ if (!EFI_ERROR (Status)) {
+ // Use the first SimpleTextIn we find and update the EFI System Table
+ gST->ConsoleInHandle = Buffer[0];
+ Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextInProtocolGuid, (VOID **)&gST->ConIn);
+ ASSERT_EFI_ERROR (Status);
+
+ FreePool (Buffer);
+ }
+
+ //
+ // We now have EFI Consoles up and running. Print () will work now. DEBUG () and ASSERT () worked
+ // prior to this point as they were configured to use a more primative output scheme.
+ //
+
+ //
+ //Perform Connect
+ //
+ HandleCount = 0;
+ while (1) {
+ OldHandleCount = HandleCount;
+ Status = gBS->LocateHandleBuffer (
+ AllHandles,
+ NULL,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ if (HandleCount == OldHandleCount) {
+ break;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
+ }
+ }
+
+ //Locate handles for SimpleFileSystem protocol
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiSimpleFileSystemProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (!EFI_ERROR(Status)) {
+ for (Index = 0; Index < HandleCount; Index++) {
+ //Get the device path
+ FileSystemDevicePath = DevicePathFromHandle(HandleBuffer[Index]);
+ if (FileSystemDevicePath == NULL) {
+ continue;
+ }
+
+ //Check if UsbIo is on any handles in the device path.
+ Status = gBS->LocateDevicePath(&gEfiUsbIoProtocolGuid, &FileSystemDevicePath, &UsbDeviceHandle);
+ if (EFI_ERROR(Status)) {
+ continue;
+ }
+
+ //Check if Usb stick has a magic EBL file.
+ LoadImageDevicePath = FileDevicePath(HandleBuffer[Index], L"Ebl.efi");
+ Status = gBS->LoadImage (TRUE, gImageHandle, LoadImageDevicePath, NULL, 0, &ImageHandle);
+ if (EFI_ERROR(Status)) {
+ continue;
+ }
+
+ //Boot to Shell on USB stick.
+ Status = gBS->StartImage (ImageHandle, NULL, NULL);
+ if (EFI_ERROR(Status)) {
+ continue;
+ }
+ }
+ }
+
+ //
+ // Normal UEFI behavior is to process Globally Defined Variables as defined in Chapter 3
+ // (Boot Manager) of the UEFI specification. For this embedded system we don't do this.
+ //
+
+ //
+ // Search all the FVs for an application with a UI Section of Ebl. A .FDF file can be used
+ // to control the names of UI sections in an FV.
+ //
+ Status = FindApplicationMatchingUiSection (L"Ebl", &FvHandle, &NameGuid);
+ if (!EFI_ERROR (Status)) {
+
+ //Boot to Shell.
+ Status = LoadPeCoffSectionFromFv (FvHandle, &NameGuid);
+
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Boot from Shell failed. Status: %r\n", Status));
+ }
+ }
+
+ //
+ // EFI does not define the behaviour if all boot attemps fail and the last one returns.
+ // So we make a policy choice to reset the system since this BDS does not have a UI.
+ //
+ gRT->ResetSystem (EfiResetShutdown, Status, 0, NULL);
+
+ return ;
+}
+
+
+EFI_STATUS
+EFIAPI
+BdsInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mBdsImageHandle = ImageHandle;
+
+ //
+ // Install protocol interface
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mBdsImageHandle,
+ &gEfiBdsArchProtocolGuid, &gBdsProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
diff --git a/BeagleBoardPkg/Bds/BdsEntry.h b/BeagleBoardPkg/Bds/BdsEntry.h
new file mode 100644
index 0000000000..21e49498cf
--- /dev/null
+++ b/BeagleBoardPkg/Bds/BdsEntry.h
@@ -0,0 +1,65 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BDS_ENTRY_H__
+#define __BDS_ENTRY_H__
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+EFI_STATUS
+LoadPeCoffSectionFromFv (
+ IN EFI_HANDLE FvHandle,
+ IN EFI_GUID *NameGuid
+ );
+
+EFI_STATUS
+FindApplicationMatchingUiSection (
+ IN CHAR16 *UiString,
+ OUT EFI_HANDLE *FvHandle,
+ OUT EFI_GUID *NameGuid
+ );
+
+VOID
+EFIAPI
+BdsEntry (
+ IN EFI_BDS_ARCH_PROTOCOL *This
+ );
+
+#endif
+
diff --git a/BeagleBoardPkg/Bds/FirmwareVolume.c b/BeagleBoardPkg/Bds/FirmwareVolume.c
new file mode 100644
index 0000000000..f08de5767a
--- /dev/null
+++ b/BeagleBoardPkg/Bds/FirmwareVolume.c
@@ -0,0 +1,150 @@
+/** @file
+ The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements
+ of the UEFI specification as it is designed to implement an embedded systmes
+ propriatary boot scheme.
+
+ This template assume a DXE driver produces a SerialIo protocol not using the EFI
+ driver module and it will attempt to connect a console on top of this.
+
+
+ Copyright (c) 2009 Apple, Inc. All rights reserved.
+ Portions copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+
+ This document is the property of Apple, Inc.
+ It is considered confidential and proprietary.
+
+ This document may not be reproduced or transmitted in any form,
+ in whole or in part, without the express written permission of
+ Apple, Inc.
+
+**/
+
+#include "BdsEntry.h"
+
+
+EFI_STATUS
+FindApplicationMatchingUiSection (
+ IN CHAR16 *UiString,
+ OUT EFI_HANDLE *FvHandle,
+ OUT EFI_GUID *NameGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_STATUS NextStatus;
+ UINTN NoHandles;
+ EFI_HANDLE *Buffer;
+ UINTN Index;
+ EFI_FV_FILETYPE FileType;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ VOID *Key;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN UiStringLen;
+ CHAR16 *UiSection;
+ UINT32 Authentication;
+
+
+ UiStringLen = 0;
+ if (UiString != NULL) {
+ DEBUG ((DEBUG_ERROR, "UiString %s\n", UiString));
+ UiStringLen = StrLen (UiString);
+ }
+
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Buffer);
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < NoHandles; Index++) {
+ Status = gBS->HandleProtocol (Buffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **)&Fv);
+ if (!EFI_ERROR (Status)) {
+ Key = AllocatePool (Fv->KeySize);
+ ASSERT (Key != NULL);
+ ZeroMem (Key, Fv->KeySize);
+
+ FileType = EFI_FV_FILETYPE_APPLICATION;
+
+ do {
+ NextStatus = Fv->GetNextFile (Fv, Key, &FileType, NameGuid, &Attributes, &Size);
+ if (!EFI_ERROR (NextStatus)) {
+ if (UiString == NULL) {
+ //
+ // If UiString is NULL match first application we find.
+ //
+ *FvHandle = Buffer[Index];
+ FreePool (Key);
+ return Status;
+ }
+
+ UiSection = NULL;
+ Status = Fv->ReadSection (
+ Fv,
+ NameGuid,
+ EFI_SECTION_USER_INTERFACE,
+ 0,
+ (VOID **)&UiSection,
+ &Size,
+ &Authentication
+ );
+ if (!EFI_ERROR (Status)) {
+ if (StrnCmp (UiString, UiSection, UiStringLen) == 0) {
+ //
+ // We found a UiString match.
+ //
+ *FvHandle = Buffer[Index];
+ FreePool (Key);
+ FreePool (UiSection);
+ return Status;
+ }
+ FreePool (UiSection);
+ }
+ }
+ } while (!EFI_ERROR (NextStatus));
+
+ FreePool (Key);
+ }
+ }
+
+ FreePool (Buffer);
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+
+EFI_DEVICE_PATH *
+FvFileDevicePath (
+ IN EFI_HANDLE FvHandle,
+ IN EFI_GUID *NameGuid
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH NewNode;
+
+ DevicePath = DevicePathFromHandle (FvHandle);
+
+ EfiInitializeFwVolDevicepathNode (&NewNode, NameGuid);
+
+ return AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&NewNode);
+}
+
+
+
+EFI_STATUS
+LoadPeCoffSectionFromFv (
+ IN EFI_HANDLE FvHandle,
+ IN EFI_GUID *NameGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_HANDLE ImageHandle;
+
+ DevicePath = FvFileDevicePath (FvHandle, NameGuid);
+
+ Status = gBS->LoadImage (TRUE, gImageHandle, DevicePath, NULL, 0, &ImageHandle);
+ if (!EFI_ERROR (Status)) {
+ Status = gBS->StartImage (ImageHandle, NULL, NULL);
+ }
+
+ return Status;
+}
+
diff --git a/BeagleBoardPkg/BeagleBoardPkg.dec b/BeagleBoardPkg/BeagleBoardPkg.dec
new file mode 100644
index 0000000000..7a92f94a21
--- /dev/null
+++ b/BeagleBoardPkg/BeagleBoardPkg.dec
@@ -0,0 +1,65 @@
+#%HEADER%
+#/** @file
+# Beagle board package.
+#
+# Copyright (c) 2009, Apple Inc.
+#
+# All rights reserved.
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = BeagleBoardPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gBeagleBoardTokenSpaceGuid = { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } }
+
+#[PcdsEnumerations.common]
+# OMAP3530_GPTIMER:
+# OMAP3530_GPTIMER1|1
+# OMAP3530_GPTIMER2|2
+# OMAP3530_GPTIMER3|3
+# OMAP3530_GPTIMER4|4
+# OMAP3530_GPTIMER5|5
+# OMAP3530_GPTIMER6|6
+# OMAP3530_GPTIMER7|7
+# OMAP3530_GPTIMER8|8
+# OMAP3530_GPTIMER9|9
+# OMAP3530_GPTIMER10|10
+# OMAP3530_GPTIMER11|11
+# OMAP3530_GPTIMER12|12
+
+[PcdsFeatureFlag.common]
+
+[PcdsFixedAtBuild.common]
+ gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000|UINT32|0x00000201
+ gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3|UINT32|0x00000202
+ gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x00000000|UINT32|0x00000203
+ gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x00000000|UINT32|0x00000204
+# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3|OMAP3530_GPTIMER|0x00000205
+ gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3|UINT32|0x00000205
+# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4|OMAP3530_GPTIMER|0x00000206
+ gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4|UINT32|0x00000206
+
diff --git a/BeagleBoardPkg/BeagleBoardPkg.dsc b/BeagleBoardPkg/BeagleBoardPkg.dsc
new file mode 100644
index 0000000000..a0d7a77172
--- /dev/null
+++ b/BeagleBoardPkg/BeagleBoardPkg.dsc
@@ -0,0 +1,415 @@
+#/** @file
+# Beagle board package.
+#
+# Copyright (c) 2009, Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = BeagleBoardPkg
+ PLATFORM_GUID = 91fa6c28-33df-46ac-aee6-292d6811ea31
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/BeagleBoard
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = BeagleBoardPkg/BeagleBoardPkg.fdf
+ DEFINE TARGET_HACK = DEBUG
+
+
+[LibraryClasses.common]
+!if TARGET_HACK == DEBUG
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ BeagleBoardSystemLib|BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf
+ EfiResetSystemLib|BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
+
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
+ EblCmdLib|BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf
+
+ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+
+
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+
+ SerialPortLib|BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+
+ RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
+
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+
+#
+# Assume everything is fixed at build
+#
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+ TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
+ OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
+ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+ GdbSerialLib|BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
+
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[BuildOptions]
+ XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv6 -march=armv6
+ XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv6
+ XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv6
+
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ #
+ # Control what commands are supported from the UI
+ # Turn these on and off to add features or save size
+ #
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+
+ #
+ # Beagle board Specific PCDs
+ #
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"BeagleEdk2"
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+# DEBUG_ASSERT_ENABLED 0x01
+
+# DEBUG_PRINT_ENABLED 0x02
+
+# DEBUG_CODE_ENABLED 0x04
+
+# CLEAR_MEMORY_ENABLED 0x08
+
+# ASSERT_BREAKPOINT_ENABLED 0x10
+
+# ASSERT_DEADLOOP_ENABLED 0x20
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+
+# DEBUG_INIT 0x00000001 // Initialization
+
+# DEBUG_WARN 0x00000002 // Warnings
+
+# DEBUG_LOAD 0x00000004 // Load events
+
+# DEBUG_FS 0x00000008 // EFI File system
+
+# DEBUG_POOL 0x00000010 // Alloc & Free's
+
+# DEBUG_PAGE 0x00000020 // Alloc & Free's
+
+# DEBUG_INFO 0x00000040 // Verbose
+
+# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+
+# DEBUG_VARIABLE 0x00000100 // Variable
+
+# DEBUG_BM 0x00000400 // Boot Manager
+
+# DEBUG_BLKIO 0x00001000 // BlkIo Driver
+
+# DEBUG_NET 0x00004000 // SNI Driver
+
+# DEBUG_UNDI 0x00010000 // UNDI Driver
+
+# DEBUG_LOADFILE 0x00020000 // UNDI Driver
+
+# DEBUG_EVENT 0x00080000 // Event messages
+
+# DEBUG_ERROR 0x80000000 // Error
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0
+ gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0
+ gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
+
+#
+# Optional feature to help prevent EFI memory map fragments
+# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+# Values are in EFI Pages (4K). DXE Core will make sure that
+# at least this much of each type of memory can be allocated
+# from a single memory range. This way you only end up with
+# maximum of two fragements for each type in the memory map
+# (the memory used, and the free memory that was prereserved
+# but not used).
+#
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+
+#
+# Beagle board Specific PCDs
+#
+ gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
+ gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
+ gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
+ gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
+
+ gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x6E000000
+ gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x4809C000
+
+ # Console
+ gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3
+
+ # Timers
+# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3
+ gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3
+# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4
+ gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|77
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|13000000
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+#
+# SEC
+#
+ BeagleBoardPkg/Sec/Sec.inf
+
+#
+# DXE
+#
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB
+ #
+ BeagleBoardPkg/PciEmulation/PciEmulation.inf
+
+ #NOTE: Open source EHCI stack doesn't work on Beagleboard.
+ #NOTE: UsbBus and UsbMassStorage don't work using iPhone SDK tool chain.
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf {
+
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800fffff
+ }
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Nand Flash
+ #
+ BeagleBoardPkg/Flash/Flash.inf
+
+ #
+ # MMC/SD
+ #
+ BeagleBoardPkg/MMCHSDxe/MMCHS.inf
+
+ #
+ # I2C
+ #
+ BeagleBoardPkg/SmbusDxe/Smbus.inf
+
+ #
+ # SoC Drivers
+ #
+ BeagleBoardPkg/Gpio/Gpio.inf
+ BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
+ BeagleBoardPkg/TimerDxe/TimerDxe.inf
+
+ #
+ # Power IC
+ #
+ BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
+
+ #
+ # Application
+ #
+ EmbeddedPkg/Ebl/Ebl.inf
+
+ #
+ # Bds
+ #
+ BeagleBoardPkg/Bds/Bds.inf
+
+ #
+ # Gdb Stub
+ #
+ EmbeddedPkg/GdbStub/GdbStub.inf
+ ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
+
diff --git a/BeagleBoardPkg/BeagleBoardPkg.fdf b/BeagleBoardPkg/BeagleBoardPkg.fdf
new file mode 100644
index 0000000000..d29650497e
--- /dev/null
+++ b/BeagleBoardPkg/BeagleBoardPkg.fdf
@@ -0,0 +1,296 @@
+# FLASH layout file for Beagle board.
+#
+# Copyright (c) 2009, Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+
+[FD.BeagleBoard_EFI]
+BaseAddress = 0x80008000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00080000|gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x40
+NumBlocks = 0x2000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType
+#
+################################################################################
+
+# 512 bytes of configuration header & 8 bytes of image header
+0x00000000|0x00000208
+
+0x00000208|0x0007FDF8
+gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0x9000
+FvAlignment = 8 #FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Nand Flash
+ #
+ INF BeagleBoardPkg/Flash/Flash.inf
+
+ #
+ # MMC/SD
+ #
+ INF BeagleBoardPkg/MMCHSDxe/MMCHS.inf
+
+ #
+ # I2C
+ #
+ INF BeagleBoardPkg/SmbusDxe/Smbus.inf
+
+ #
+ # SoC Drivers
+ #
+ INF BeagleBoardPkg/Gpio/Gpio.inf
+ INF BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
+ INF BeagleBoardPkg/TimerDxe/TimerDxe.inf
+
+ #
+ # Power IC
+ #
+ INF BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # USB Support
+ #
+
+ INF BeagleBoardPkg/PciEmulation/PciEmulation.inf
+
+ #NOTE: Open source EHCI stack doesn't work on Beagleboard.
+ #NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF EmbeddedPkg/Ebl/Ebl.inf
+
+
+ #
+ # Bds
+ #
+ INF BeagleBoardPkg/Bds/Bds.inf
+
+ #
+ # Gdb Stub
+ #
+ #INF ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
+ #INF ApplePkg/Universal/GdbStub/GdbStub.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF BeagleBoardPkg/Sec/Sec.inf
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional |.depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 |.efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 8 |.efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE |.efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional |.depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 |.efi
+ }
diff --git a/BeagleBoardPkg/ConfigurationHeader.dat b/BeagleBoardPkg/ConfigurationHeader.dat
new file mode 100644
index 0000000000..5f6897e306
--- /dev/null
+++ b/BeagleBoardPkg/ConfigurationHeader.dat
@@ -0,0 +1,41 @@
+PRM_CLKSRC_CTRL=0x00000080
+PRM_CLKSEL=0x00000003
+CM_CLKSEL1_EMU=0x03020A50
+CM_CLKSEL_CORE=0x0000030A
+CM_CLKSEL_WKUP=0x00000015
+CM_CLKEN_PLL_DPLL3=0x00370037
+CM_AUTOIDLE_PLL_DPLL3=0x00000000
+CM_CLKSEL1_PLL=0x094C0C00
+CM_CLKEN_PLL_DPLL4=0x00370037
+CM_AUTOIDLE_PLL_DPLL4=0x00000000
+CM_CLKSEL2_PLL=0x0001B00C
+CM_CLKSEL3_PLL=0x00000009
+CM_CLKEN_PLL_MPU=0x00000037
+CM_AUTOIDLE_PLL_MPU=0x00000000
+CM_CLKSEL1_PLL_MPU=0x0011F40C
+CM_CLKSEL2_PLL_MPU=0x00000001
+CM_CLKSTCTRL_MPU=0x00000000
+SDRC_SYSCONFIG_LSB=0x0000
+SDRC_CS_CFG_LSB=0x0001
+SDRC_SHARING_LSB=0x0100
+SDRC_ERR_TYPE_LSB=0x0000
+SDRC_DLLA_CTRL=0x0000000A
+SDRC_POWER=0x00000081
+MEMORY_TYPE_CS0=0x0003
+SDRC_MCFG_0=0x02D04011
+SDRC_MR_0_LSB=0x0032
+SDRC_EMR1_0_LSB=0x0000
+SDRC_EMR2_0_LSB=0x0000
+SDRC_EMR3_0_LSB=0x0000
+SDRC_ACTIM_CTRLA_0=0xBA9DC4C6
+SDRC_ACTIM_CTRLB_0=0x00012522
+SDRC_RFRCTRL_0=0x0004E201
+MEMORY_TYPE_CS1=0x0003
+SDRC_MCFG_1=0x02D04011
+SDRC_MR_1_LSB=0x0032
+SDRC_EMR1_1_LSB=0x0000
+SDRC_EMR2_1_LSB=0x0000
+SDRC_EMR3_1_LSB=0x0000
+SDRC_ACTIM_CTRLA_1=0xBA9DC4C6
+SDRC_ACTIM_CTRLB_1=0x00012522
+SDRC_RFRCTRL_1=0x0004E201
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc b/BeagleBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc
new file mode 100644
index 0000000000..72c0fd75dd
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc
@@ -0,0 +1,21 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+error = continue
+unload
+error = abort
+
+setreg @CP15_CONTROL = 0x0005107E
+setreg @pc=0x80008208
+setreg @cpsr=0x000000D3
+dis/D
+readfile,raw,nowarn "ZZZZZZ/FV/BEAGLEBOARD_EFI.fd"=0x80008000
+
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_convert_symbols.sh b/BeagleBoardPkg/Debugger_scripts/rvi_convert_symbols.sh
new file mode 100755
index 0000000000..72947cc1c1
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/rvi_convert_symbols.sh
@@ -0,0 +1,23 @@
+#!/bin/sh
+#
+# Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http:#opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+
+IN=`/usr/bin/cygpath -u $1`
+OUT=`/usr/bin/cygpath -u $2`
+
+/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \
+ -e 's:\\:/:g' \
+ -e "s/^/load\/a\/ni\/np \"/g" \
+ -e "s/dll /dll\" \&/g" \
+ $IN | /usr/bin/sort.exe --key=3 --output=$OUT
+
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_dummy.axf b/BeagleBoardPkg/Debugger_scripts/rvi_dummy.axf
new file mode 100755
index 0000000000..17fabaa6cc
Binary files /dev/null and b/BeagleBoardPkg/Debugger_scripts/rvi_dummy.axf differ
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc b/BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc
new file mode 100644
index 0000000000..eb5ce57aa3
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc
@@ -0,0 +1,67 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+error = continue
+unload
+error = abort
+
+setreg @CP15_CONTROL = 0x0005107E
+setreg @cpsr=0x000000D3
+
+; General clock settings.
+setmem /32 0x48307270=0x00000080
+setmem /32 0x48306D40=0x00000003
+setmem /32 0x48005140=0x03020A50
+
+;Clock configuration
+setmem /32 0x48004A40=0x0000030A
+setmem /32 0x48004C40=0x00000015
+
+;DPLL3 (Core) settings
+setmem /32 0x48004D00=0x00370037
+setmem /32 0x48004D30=0x00000000
+setmem /32 0x48004D40=0x094C0C00
+
+;DPLL4 (Peripheral) settings
+setmem /32 0x48004D00=0x00370037
+setmem /32 0x48004D30=0x00000000
+setmem /32 0x48004D44=0x0001B00C
+setmem /32 0x48004D48=0x00000009
+
+;DPLL1 (MPU) settings
+setmem /32 0x48004904=0x00000037
+setmem /32 0x48004934=0x00000000
+setmem /32 0x48004940=0x0011F40C
+setmem /32 0x48004944=0x00000001
+setmem /32 0x48004948=0x00000000
+
+;RAM setup.
+setmem /16 0x6D000010=0x0000
+setmem /16 0x6D000040=0x0001
+setmem /16 0x6D000044=0x0100
+setmem /16 0x6D000048=0x0000
+setmem /32 0x6D000060=0x0000000A
+setmem /32 0x6D000070=0x00000081
+setmem /16 0x6D000040=0x0003
+setmem /32 0x6D000080=0x02D04011
+setmem /16 0x6D000084=0x0032
+setmem /16 0x6D00008C=0x0000
+setmem /32 0x6D00009C=0xBA9DC4C6
+setmem /32 0x6D0000A0=0x00012522
+setmem /32 0x6D0000A4=0x0004E201
+setmem /16 0x6D000040=0x0003
+setmem /32 0x6D0000B0=0x02D04011
+setmem /16 0x6D0000B4=0x0032
+setmem /16 0x6D0000BC=0x0000
+setmem /32 0x6D0000C4=0xBA9DC4C6
+setmem /32 0x6D0000C8=0x00012522
+setmem /32 0x6D0000D4=0x0004E201
\ No newline at end of file
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_load_symbols.inc b/BeagleBoardPkg/Debugger_scripts/rvi_load_symbols.inc
new file mode 100644
index 0000000000..27d4007d1c
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/rvi_load_symbols.inc
@@ -0,0 +1,23 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+include 'ZZZZZZ/rvi_symbols_macros.inc'
+
+macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000)
+
+host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc"
+include 'ZZZZZZ/rvi_symbols.inc'
+load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata
+unload rvi_dummy.axf
+delfile rvi_dummy.axf
+
+
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_symbols_macros.inc b/BeagleBoardPkg/Debugger_scripts/rvi_symbols_macros.inc
new file mode 100755
index 0000000000..ccd1ea068f
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/rvi_symbols_macros.inc
@@ -0,0 +1,194 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+define /R int compare_guid(guid1, guid2)
+ unsigned char *guid1;
+ unsigned char *guid2;
+{
+ return strncmp(guid1, guid2, 16);
+}
+.
+
+define /R unsigned char * find_system_table(mem_start, mem_size)
+ unsigned char *mem_start;
+ unsigned long mem_size;
+{
+ unsigned char *mem_ptr;
+
+ mem_ptr = mem_start + mem_size;
+
+ do
+ {
+ mem_ptr -= 0x400000; // 4 MB
+
+ if (strncmp(mem_ptr, "IBI SYST", 8) == 0)
+ {
+ return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase
+ }
+
+ } while (mem_ptr > mem_start);
+
+ return 0;
+}
+.
+
+define /R unsigned char * find_debug_info_table_header(system_table)
+ unsigned char *system_table;
+{
+ unsigned long configuration_table_entries;
+ unsigned char *configuration_table;
+ unsigned long index;
+ unsigned char debug_table_guid[16];
+
+ // Fill in the debug table's guid
+ debug_table_guid[ 0] = 0x77;
+ debug_table_guid[ 1] = 0x2E;
+ debug_table_guid[ 2] = 0x15;
+ debug_table_guid[ 3] = 0x49;
+ debug_table_guid[ 4] = 0xDA;
+ debug_table_guid[ 5] = 0x1A;
+ debug_table_guid[ 6] = 0x64;
+ debug_table_guid[ 7] = 0x47;
+ debug_table_guid[ 8] = 0xB7;
+ debug_table_guid[ 9] = 0xA2;
+ debug_table_guid[10] = 0x7A;
+ debug_table_guid[11] = 0xFE;
+ debug_table_guid[12] = 0xFE;
+ debug_table_guid[13] = 0xD9;
+ debug_table_guid[14] = 0x5E;
+ debug_table_guid[15] = 0x8B;
+
+ configuration_table_entries = *(unsigned long *)(system_table + 64);
+ configuration_table = *(unsigned long *)(system_table + 68);
+
+ for (index = 0; index < configuration_table_entries; index++)
+ {
+ if (compare_guid(configuration_table, debug_table_guid) == 0)
+ {
+ return *(unsigned long *)(configuration_table + 16);
+ }
+
+ configuration_table += 20;
+ }
+
+ return 0;
+}
+.
+
+define /R int valid_pe_header(header)
+ unsigned char *header;
+{
+ if ((header[0x00] == 'M') &&
+ (header[0x01] == 'Z') &&
+ (header[0x80] == 'P') &&
+ (header[0x81] == 'E'))
+ {
+ return 1;
+ }
+
+ return 0;
+}
+.
+
+define /R unsigned long pe_headersize(header)
+ unsigned char *header;
+{
+ unsigned long *size;
+
+ size = header + 0x00AC;
+
+ return *size;
+}
+.
+
+define /R unsigned char *pe_filename(header)
+ unsigned char *header;
+{
+ unsigned long *debugOffset;
+ unsigned char *stringOffset;
+
+ if (valid_pe_header(header))
+ {
+ debugOffset = header + 0x0128;
+ stringOffset = header + *debugOffset + 0x002C;
+
+ return stringOffset;
+ }
+
+ return 0;
+}
+.
+
+define /R int char_is_valid(c)
+ unsigned char c;
+{
+ if (c >= 32 && c < 127)
+ return 1;
+
+ return 0;
+}
+.
+
+define /R write_symbols_file(filename, mem_start, mem_size)
+ unsigned char *filename;
+ unsigned char *mem_start;
+ unsigned long mem_size;
+{
+ unsigned char *system_table;
+ unsigned char *debug_info_table_header;
+ unsigned char *debug_info_table;
+ unsigned long debug_info_table_size;
+ unsigned long index;
+ unsigned char *debug_image_info;
+ unsigned char *loaded_image_protocol;
+ unsigned char *image_base;
+ unsigned char *debug_filename;
+ unsigned long header_size;
+ int status;
+
+ system_table = find_system_table(mem_start, mem_size);
+ if (system_table == 0)
+ {
+ return;
+ }
+
+ status = fopen(88, filename, "w");
+
+ debug_info_table_header = find_debug_info_table_header(system_table);
+
+ debug_info_table = *(unsigned long *)(debug_info_table_header + 8);
+ debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4);
+
+ for (index = 0; index < (debug_info_table_size * 4); index += 4)
+ {
+ debug_image_info = *(unsigned long *)(debug_info_table + index);
+
+ if (debug_image_info == 0)
+ {
+ break;
+ }
+
+ loaded_image_protocol = *(unsigned long *)(debug_image_info + 4);
+
+ image_base = *(unsigned long *)(loaded_image_protocol + 32);
+
+ debug_filename = pe_filename(image_base);
+ header_size = pe_headersize(image_base);
+
+ $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$;
+ }
+
+
+ fclose(88);
+}
+.
+
diff --git a/BeagleBoardPkg/Debugger_scripts/rvi_unload_symbols.inc b/BeagleBoardPkg/Debugger_scripts/rvi_unload_symbols.inc
new file mode 100755
index 0000000000..9d28582fcb
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/rvi_unload_symbols.inc
@@ -0,0 +1,118 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+error = continue
+
+unload
+
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+delfile 1
+
+error = abort
diff --git a/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols.cmm b/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols.cmm
new file mode 100644
index 0000000000..0dffaa461a
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols.cmm
@@ -0,0 +1,211 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+ ENTRY &ram_start &ram_size
+
+ ;If system is running then stop the execution so we can load symbols.
+ break
+
+ ;Reset all windows
+ WINPAGE.RESET
+
+ ;Create AREA to display the symbols we are loading.
+ AREA.Reset
+ AREA.Create SYMBOL 300. 100.
+ AREA.View SYMBOL
+ AREA.Select SYMBOL
+ SYS.Option BE OFF
+
+ ;Added based on suggestion from Lauterbach support.
+ MMU.TABLEWALK ON
+ MMU.ON
+
+ ;Load symbols.
+ GOSUB load_symbols &ram_start &ram_size
+
+ ;Open some windows and enable semihosting.
+ TOOLBAR ON
+ STATUSBAR ON
+ WINPAGE.RESET
+
+ WINCLEAR
+ WINPOS 0.0 17.0 72. 13. 0. 0. W000
+ SYStem
+
+ WINPOS 0.0 0.0 110. 55. 13. 1. W001
+ WINTABS 10. 10. 25. 62.
+ Data.List
+
+ WINPAGE.SELECT P000
+
+ //Enable semihosting
+ System.Option.BigEndian OFF
+
+ tronchip.set swi on // ARM9/10/11 variant
+
+ // configure and open semihosting channel
+ winpos 50% 50% 50% 50%
+ term.heapinfo 0 0x20000 0x30000 0x20000
+ term.method armswi
+ term.mode string
+ term.gate
+
+ WINPOS 115.0 0. 70. 35. 0. 1. W002
+ Var.Local %HEX
+
+ WINPOS 115.10 45. 48. 9. 0. 0. W003
+ Register
+
+ END
+
+find_system_table:
+ ENTRY &mem_start &mem_size
+ &mem_ptr=&mem_start+&mem_size
+ RPT
+ (
+ &mem_ptr=&mem_ptr-0x400000 // 4 MB
+ &word1=Data.LONG(D:&mem_ptr)
+ &word2=Data.LONG(D:&mem_ptr+0x04)
+ IF &word1==0x20494249
+ (
+ IF &word2==0x54535953
+ (
+ &result=Data.LONG(D:&mem_ptr+0x08)
+ RETURN &result
+ )
+ )
+ )
+ WHILE &mem_ptr>&mem_start
+ &result=0
+ RETURN &result
+
+compare_guid:
+ ENTRY &guid
+ IF Data.LONG(D:&guid)==0x49152E77
+ (
+ IF Data.LONG(D:&guid+0x04)==0x47641ADA
+ (
+ IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
+ (
+ IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
+ (
+ RETURN 0
+ )
+ )
+ )
+ )
+ RETURN 1
+
+find_debug_info_table_header:
+ ENTRY &system_table
+ &config_table_entries=Data.LONG(D:&system_table+0x40)
+ &config_table_pointer=Data.LONG(D:&system_table+0x44)
+ RPT &config_table_entries
+ (
+ GOSUB compare_guid &config_table_pointer
+ ENTRY &result
+ IF &result==0
+ (
+ &result=Data.LONG(D:&config_table_pointer+0x10)
+ RETURN &result
+ )
+ &config_table_pointer=&config_table_pointer+0x14
+ )
+ RETURN 0;
+
+valid_pe_header:
+ ENTRY &header
+ IF Data.BYTE(D:&header+0x00)==0x4D
+ (
+ IF Data.BYTE(D:&header+0x01)==0x5A
+ (
+ IF Data.BYTE(D:&header+0x80)==0x50
+ (
+ IF Data.BYTE(D:&header+0x81)==0x45
+ (
+ RETURN 1
+ )
+ )
+ )
+ )
+ RETURN 0
+
+get_file_string:
+ ENTRY &stringOffset
+
+ local &string
+
+ &more_string=data.string(d:&stringOffset)
+
+ if (string.len("&more_string")>=128.)
+ (
+ &string="&string"+"&more_string"
+ &stringOffset=&stringOffset+string.len("&more_string")
+
+ //Get remaining file string
+ GOSUB get_file_string &stringOffset
+ ENTRY &more_string
+ &string="&string"+"&more_string"
+ )
+ else
+ (
+ &string="&string"+"&more_string"
+ &more_string=""
+ )
+ RETURN &string
+
+load_symbol_file:
+ ENTRY &header &load_address
+ GOSUB valid_pe_header &header
+ ENTRY &result
+
+ IF &result==1
+ (
+ &debugOffset=Data.LONG(D:&header+0x0128)
+ &stringOffset=&header+&debugOffset+0x002C
+
+ GOSUB get_file_string &stringOffset
+ ENTRY &filestring
+
+ PRINT "&filestring 0x" &load_address
+ TDIAG Data.load.elf &filestring &load_address /nocode /noclear
+ )
+ RETURN
+
+pe_headersize:
+ ENTRY &header;
+ RETURN Data.LONG(D:&header+0x00AC)
+
+load_symbols:
+ ENTRY &mem_start &mem_size
+ GOSUB find_system_table &mem_start &mem_size
+ ENTRY &system_table
+ GOSUB find_debug_info_table_header &system_table
+ ENTRY &debug_info_table_header
+ &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
+ &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
+ &index=0
+ RPT &debug_info_table_size
+ (
+ &debug_image_info=Data.LONG(D:&debug_info_table+&index)
+ IF &debug_image_info==0
+ RETURN
+ &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
+ &image_base=Data.LONG(D:&loaded_image_protocol+0x20);
+ GOSUB pe_headersize &image_base
+ ENTRY &header_size
+ &image_load_address=&image_base+&header_size
+ GOSUB load_symbol_file &image_base &image_load_address
+ &index=&index+0x4
+ )
+
+ RETURN
diff --git a/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm b/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm
new file mode 100644
index 0000000000..011df5254d
--- /dev/null
+++ b/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm
@@ -0,0 +1,188 @@
+//
+// Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+
+ ENTRY &ram_start &ram_size
+
+ ;If system is running then stop the execution so we can load symbols.
+ break
+
+ ;Reset all windows
+ WINPAGE.RESET
+
+ AREA.Reset
+ AREA.Create SYMBOL 300. 100.
+ AREA.View SYMBOL
+ AREA.Select SYMBOL
+ SYS.Option BE OFF
+
+ ; Added based on suggestion from Lauterbach support.
+ MMU.TABLEWALK ON
+ MMU.ON
+
+ GOSUB load_symbols &ram_start &ram_size
+
+ ;Open some windows.
+ WINPOS 83.125 29.063 48. 9. 0. 0. W003
+ Register
+
+ WINPOS 83.25 10. 48. 9. 0. 1. W002
+ Var.Local
+
+ END
+
+find_system_table:
+ ENTRY &mem_start &mem_size
+ &mem_ptr=&mem_start+&mem_size
+ RPT
+ (
+ &mem_ptr=&mem_ptr-0x400000 // 4 MB
+ &word1=Data.LONG(D:&mem_ptr)
+ &word2=Data.LONG(D:&mem_ptr+0x04)
+ IF &word1==0x20494249
+ (
+ IF &word2==0x54535953
+ (
+ &result=Data.LONG(D:&mem_ptr+0x08)
+ RETURN &result
+ )
+ )
+ )
+ WHILE &mem_ptr>&mem_start
+ &result=0
+ RETURN &result
+
+compare_guid:
+ ENTRY &guid
+ IF Data.LONG(D:&guid)==0x49152E77
+ (
+ IF Data.LONG(D:&guid+0x04)==0x47641ADA
+ (
+ IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7
+ (
+ IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE
+ (
+ RETURN 0
+ )
+ )
+ )
+ )
+ RETURN 1
+
+find_debug_info_table_header:
+ ENTRY &system_table
+ &config_table_entries=Data.LONG(D:&system_table+0x40)
+ &config_table_pointer=Data.LONG(D:&system_table+0x44)
+ RPT &config_table_entries
+ (
+ GOSUB compare_guid &config_table_pointer
+ ENTRY &result
+ IF &result==0
+ (
+ &result=Data.LONG(D:&config_table_pointer+0x10)
+ RETURN &result
+ )
+ &config_table_pointer=&config_table_pointer+0x14
+ )
+ RETURN 0;
+
+valid_pe_header:
+ ENTRY &header
+ IF Data.BYTE(D:&header+0x00)==0x4D
+ (
+ IF Data.BYTE(D:&header+0x01)==0x5A
+ (
+ IF Data.BYTE(D:&header+0x80)==0x50
+ (
+ IF Data.BYTE(D:&header+0x81)==0x45
+ (
+ RETURN 1
+ )
+ )
+ )
+ )
+ RETURN 0
+
+get_file_string:
+ ENTRY &stringOffset
+
+ local &string
+
+ &more_string=data.string(d:&stringOffset)
+
+ if (string.len("&more_string")>=128.)
+ (
+ &string="&string"+"&more_string"
+ &stringOffset=&stringOffset+string.len("&more_string")
+
+ //Get remaining file string
+ GOSUB get_file_string &stringOffset
+ ENTRY &more_string
+ &string="&string"+"&more_string"
+ )
+ else
+ (
+ &string="&string"+"&more_string"
+ &more_string=""
+ )
+ RETURN &string
+
+load_symbol_file:
+ ENTRY &header &load_address
+ GOSUB valid_pe_header &header
+ ENTRY &result
+
+ IF &result==1
+ (
+ &debugOffset=Data.LONG(D:&header+0x0128)
+ &stringOffset=&header+&debugOffset+0x002C
+
+ &stringOffset=&stringOffset+11.
+
+ GOSUB get_file_string &stringOffset
+ ENTRY &filestring
+
+ &filestring="c:"+"&filestring"
+
+ PRINT "&filestring 0x" &load_address
+ Data.load.elf &filestring &load_address /nocode /noclear
+ )
+ RETURN
+
+pe_headersize:
+ ENTRY &header;
+ RETURN Data.LONG(D:&header+0x00AC)
+
+load_symbols:
+ ENTRY &mem_start &mem_size
+ GOSUB find_system_table &mem_start &mem_size
+ ENTRY &system_table
+ GOSUB find_debug_info_table_header &system_table
+ ENTRY &debug_info_table_header
+ &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08)
+ &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04)
+ &index=0
+ RPT &debug_info_table_size
+ (
+ &debug_image_info=Data.LONG(D:&debug_info_table+&index)
+ IF &debug_image_info==0
+ RETURN
+ &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04);
+ &image_base=Data.LONG(D:&loaded_image_protocol+0x20);
+ GOSUB pe_headersize &image_base
+ ENTRY &header_size
+ &image_load_address=&image_base+&header_size
+ GOSUB load_symbol_file &image_base &image_load_address
+ &index=&index+0x4
+ )
+
+ RETURN
+
\ No newline at end of file
diff --git a/BeagleBoardPkg/Flash/Flash.c b/BeagleBoardPkg/Flash/Flash.c
new file mode 100644
index 0000000000..26a381aa2a
--- /dev/null
+++ b/BeagleBoardPkg/Flash/Flash.c
@@ -0,0 +1,748 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "Flash.h"
+
+NAND_PART_INFO_TABLE gNandPartInfoTable[1] = {
+ { 0x2C, 0xBA, 17, 11 }
+};
+
+NAND_FLASH_INFO *gNandFlashInfo = NULL;
+UINT8 *gEccCode;
+UINTN gNum512BytesChunks = 0;
+
+//
+// Device path for SemiHosting. It contains our autogened Caller ID GUID.
+//
+typedef struct {
+ VENDOR_DEVICE_PATH Guid;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} FLASH_DEVICE_PATH;
+
+FLASH_DEVICE_PATH gDevicePath = {
+ {
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
+ EFI_CALLER_ID_GUID
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
+};
+
+
+//Actual page address = Column address + Page address + Block address.
+UINTN
+GetActualPageAddressInBytes (
+ UINTN BlockIndex,
+ UINTN PageIndex
+)
+{
+ //BlockAddressStart = Start of the Block address in actual NAND
+ //PageAddressStart = Start of the Page address in actual NAND
+ return ((BlockIndex << gNandFlashInfo->BlockAddressStart) + (PageIndex << gNandFlashInfo->PageAddressStart));
+}
+
+VOID
+NandSendCommand (
+ UINT8 Command
+)
+{
+ MmioWrite16(GPMC_NAND_COMMAND_0, Command);
+}
+
+VOID
+NandSendAddress (
+ UINT8 Address
+)
+{
+ MmioWrite16(GPMC_NAND_ADDRESS_0, Address);
+}
+
+UINT16
+NandReadStatus (
+ VOID
+ )
+{
+ //Send READ STATUS command
+ NandSendCommand(READ_STATUS_CMD);
+
+ //Read status.
+ return MmioRead16(GPMC_NAND_DATA_0);
+}
+
+VOID
+NandSendAddressCycles (
+ UINTN Address
+)
+{
+ //Column address
+ NandSendAddress(Address & 0xff);
+ Address >>= 8;
+
+ //Column address
+ NandSendAddress(Address & 0x07);
+ Address >>= 3;
+
+ //Page and Block address
+ NandSendAddress(Address & 0xff);
+ Address >>= 8;
+
+ //Block address
+ NandSendAddress(Address & 0xff);
+ Address >>= 8;
+
+ //Block address
+ NandSendAddress(Address & 0x01);
+}
+
+VOID
+GpmcInit (
+ VOID
+ )
+{
+ //Enable Smart-idle mode.
+ MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE);
+
+ //Set IRQSTATUS and IRQENABLE to the reset value
+ MmioWrite32(GPMC_IRQSTATUS, 0x0);
+ MmioWrite32(GPMC_IRQENABLE, 0x0);
+
+ //Disable GPMC timeout control.
+ MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
+
+ //Set WRITEPROTECT bit to enable write access.
+ MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH);
+
+ //NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
+ MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
+ MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
+ MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
+ MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
+ MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
+ MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
+ MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
+}
+
+EFI_STATUS
+NandDetectPart (
+ VOID
+)
+{
+ UINT8 NandInfo = 0;
+ UINT8 PartInfo[5];
+ UINTN Index;
+ BOOLEAN Found = FALSE;
+
+ //Send READ ID command
+ NandSendCommand(READ_ID_CMD);
+
+ //Send one address cycle.
+ NandSendAddress(0);
+
+ //Read 5-bytes to idenfity code programmed into the NAND flash devices.
+ //BYTE 0 = Manufacture ID
+ //Byte 1 = Device ID
+ //Byte 2, 3, 4 = Nand part specific information (Page size, Block size etc)
+ for (Index = 0; Index < sizeof(PartInfo); Index++) {
+ PartInfo[Index] = MmioRead16(GPMC_NAND_DATA_0);
+ }
+
+ //Check if the ManufactureId and DeviceId are part of the currently supported nand parts.
+ for (Index = 0; Index < sizeof(gNandPartInfoTable)/sizeof(NAND_PART_INFO_TABLE); Index++) {
+ if (gNandPartInfoTable[Index].ManufactureId == PartInfo[0] && gNandPartInfoTable[Index].DeviceId == PartInfo[1]) {
+ gNandFlashInfo->BlockAddressStart = gNandPartInfoTable[Index].BlockAddressStart;
+ gNandFlashInfo->PageAddressStart = gNandPartInfoTable[Index].PageAddressStart;
+ Found = TRUE;
+ break;
+ }
+ }
+
+ if (Found == FALSE) {
+ DEBUG ((EFI_D_ERROR, "Nand part is not currently supported. Manufacture id: %x, Device id: %x\n", PartInfo[0], PartInfo[1]));
+ return EFI_NOT_FOUND;
+ }
+
+ //Populate NAND_FLASH_INFO based on the result of READ ID command.
+ gNandFlashInfo->ManufactureId = PartInfo[0];
+ gNandFlashInfo->DeviceId = PartInfo[1];
+ NandInfo = PartInfo[3];
+
+ if (PAGE_SIZE(NandInfo) == PAGE_SIZE_2K_VAL) {
+ gNandFlashInfo->PageSize = PAGE_SIZE_2K;
+ } else {
+ DEBUG ((EFI_D_ERROR, "Unknown Page size.\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (SPARE_AREA_SIZE(NandInfo) == SPARE_AREA_SIZE_64B_VAL) {
+ gNandFlashInfo->SparePageSize = SPARE_AREA_SIZE_64B;
+ } else {
+ DEBUG ((EFI_D_ERROR, "Unknown Spare area size.\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (BLOCK_SIZE(NandInfo) == BLOCK_SIZE_128K_VAL) {
+ gNandFlashInfo->BlockSize = BLOCK_SIZE_128K;
+ } else {
+ DEBUG ((EFI_D_ERROR, "Unknown Block size.\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (ORGANIZATION(NandInfo) == ORGANIZATION_X8) {
+ gNandFlashInfo->Organization = 0;
+ } else if (ORGANIZATION(NandInfo) == ORGANIZATION_X16) {
+ gNandFlashInfo->Organization = 1;
+ }
+
+ //Calculate total number of blocks.
+ gNandFlashInfo->NumPagesPerBlock = DivU64x32(gNandFlashInfo->BlockSize, gNandFlashInfo->PageSize);
+
+ return EFI_SUCCESS;
+}
+
+VOID
+NandConfigureEcc (
+ VOID
+ )
+{
+ //Define ECC size 0 and size 1 to 512 bytes
+ MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
+}
+
+VOID
+NandEnableEcc (
+ VOID
+ )
+{
+ //Clear all the ECC result registers and select ECC result register 1
+ MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
+
+ //Enable ECC engine on CS0
+ MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
+}
+
+VOID
+NandDisableEcc (
+ VOID
+ )
+{
+ //Turn off ECC engine.
+ MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE);
+}
+
+VOID
+NandCalculateEcc (
+ VOID
+ )
+{
+ UINTN Index;
+ UINTN EccResultRegister;
+ UINTN EccResult;
+
+ //Capture 32-bit ECC result for each 512-bytes chunk.
+ //In our case PageSize is 2K so read ECC1-ECC4 result registers and
+ //generate total of 12-bytes of ECC code for the particular page.
+
+ EccResultRegister = GPMC_ECC1_RESULT;
+
+ for (Index = 0; Index < gNum512BytesChunks; Index++) {
+
+ EccResult = MmioRead32(EccResultRegister);
+
+ //Calculate ECC code from 32-bit ECC result value.
+ //NOTE: Following calculation is not part of TRM. We got this information
+ //from Beagleboard mailing list.
+ gEccCode[Index * 3] = EccResult & 0xFF;
+ gEccCode[(Index * 3) + 1] = (EccResult >> 16) & 0xFF;
+ gEccCode[(Index * 3) + 2] = (((EccResult >> 20) & 0xF0) | ((EccResult >> 8) & 0x0F));
+
+ //Point to next ECC result register.
+ EccResultRegister += 4;
+ }
+}
+
+EFI_STATUS
+NandReadPage (
+ IN UINTN BlockIndex,
+ IN UINTN PageIndex,
+ OUT VOID *Buffer,
+ OUT UINT8 *SpareBuffer
+)
+{
+ UINTN Address;
+ UINTN Index;
+ UINTN NumMainAreaWords = (gNandFlashInfo->PageSize/2);
+ UINTN NumSpareAreaWords = (gNandFlashInfo->SparePageSize/2);
+ UINT16 *MainAreaWordBuffer = Buffer;
+ UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
+ UINTN Timeout = MAX_RETRY_COUNT;
+
+ //Generate device address in bytes to access specific block and page index
+ Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
+
+ //Send READ command
+ NandSendCommand(PAGE_READ_CMD);
+
+ //Send 5 Address cycles to access specific device address
+ NandSendAddressCycles(Address);
+
+ //Send READ CONFIRM command
+ NandSendCommand(PAGE_READ_CONFIRM_CMD);
+
+ //Poll till device is busy.
+ while (Timeout) {
+ if ((NandReadStatus() & NAND_READY) == NAND_READY) {
+ break;
+ }
+ Timeout--;
+ }
+
+ if (Timeout == 0) {
+ DEBUG ((EFI_D_ERROR, "Read page timed out.\n"));
+ return EFI_TIMEOUT;
+ }
+
+ //Reissue READ command
+ NandSendCommand(PAGE_READ_CMD);
+
+ //Enable ECC engine.
+ NandEnableEcc();
+
+ //Read data into the buffer.
+ for (Index = 0; Index < NumMainAreaWords; Index++) {
+ *MainAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
+ }
+
+ //Read spare area into the buffer.
+ for (Index = 0; Index < NumSpareAreaWords; Index++) {
+ *SpareAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
+ }
+
+ //Calculate ECC.
+ NandCalculateEcc();
+
+ //Turn off ECC engine.
+ NandDisableEcc();
+
+ //Perform ECC correction.
+ //Need to implement..
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NandWritePage (
+ IN UINTN BlockIndex,
+ IN UINTN PageIndex,
+ OUT VOID *Buffer,
+ IN UINT8 *SpareBuffer
+)
+{
+ UINTN Address;
+ UINT16 *MainAreaWordBuffer = Buffer;
+ UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
+ UINTN Index;
+ UINTN NandStatus;
+ UINTN Timeout = MAX_RETRY_COUNT;
+
+ //Generate device address in bytes to access specific block and page index
+ Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
+
+ //Send SERIAL DATA INPUT command
+ NandSendCommand(PROGRAM_PAGE_CMD);
+
+ //Send 5 Address cycles to access specific device address
+ NandSendAddressCycles(Address);
+
+ //Enable ECC engine.
+ NandEnableEcc();
+
+ //Data input from Buffer
+ for (Index = 0; Index < (gNandFlashInfo->PageSize/2); Index++) {
+ MmioWrite16(GPMC_NAND_DATA_0, *MainAreaWordBuffer++);
+
+ //After each write access, device has to wait to accept data.
+ //Currently we may not be programming proper timing parameters to
+ //the GPMC_CONFIGi_0 registers and we would need to figure that out.
+ //Without following delay, page programming fails.
+ gBS->Stall(1);
+ }
+
+ //Calculate ECC.
+ NandCalculateEcc();
+
+ //Turn off ECC engine.
+ NandDisableEcc();
+
+ //Prepare Spare area buffer with ECC codes.
+ SetMem(SpareBuffer, gNandFlashInfo->SparePageSize, 0xFF);
+ CopyMem(&SpareBuffer[ECC_POSITION], gEccCode, gNum512BytesChunks * 3);
+
+ //Program spare area with calculated ECC.
+ for (Index = 0; Index < (gNandFlashInfo->SparePageSize/2); Index++) {
+ MmioWrite16(GPMC_NAND_DATA_0, *SpareAreaWordBuffer++);
+ }
+
+ //Send PROGRAM command
+ NandSendCommand(PROGRAM_PAGE_CONFIRM_CMD);
+
+ //Poll till device is busy.
+ while (Timeout) {
+ NandStatus = NandReadStatus();
+ if ((NandStatus & NAND_READY) == NAND_READY) {
+ break;
+ }
+ Timeout--;
+ }
+
+ if (Timeout == 0) {
+ DEBUG ((EFI_D_ERROR, "Program page timed out.\n"));
+ return EFI_TIMEOUT;
+ }
+
+ //Bit0 indicates Pass/Fail status
+ if (NandStatus & NAND_FAILURE) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NandEraseBlock (
+ IN UINTN BlockIndex
+)
+{
+ UINTN Address;
+ UINTN NandStatus;
+ UINTN Timeout = MAX_RETRY_COUNT;
+
+ //Generate device address in bytes to access specific block and page index
+ Address = GetActualPageAddressInBytes(BlockIndex, 0);
+
+ //Send ERASE SETUP command
+ NandSendCommand(BLOCK_ERASE_CMD);
+
+ //Send 3 address cycles to device to access Page address and Block address
+ Address >>= 11; //Ignore column addresses
+
+ NandSendAddress(Address & 0xff);
+ Address >>= 8;
+
+ NandSendAddress(Address & 0xff);
+ Address >>= 8;
+
+ NandSendAddress(Address & 0xff);
+
+ //Send ERASE CONFIRM command
+ NandSendCommand(BLOCK_ERASE_CONFIRM_CMD);
+
+ //Poll till device is busy.
+ while (Timeout) {
+ NandStatus = NandReadStatus();
+ if ((NandStatus & NAND_READY) == NAND_READY) {
+ break;
+ }
+ Timeout--;
+ gBS->Stall(1);
+ }
+
+ if (Timeout == 0) {
+ DEBUG ((EFI_D_ERROR, "Erase block timed out for Block: %d.\n", BlockIndex));
+ return EFI_TIMEOUT;
+ }
+
+ //Bit0 indicates Pass/Fail status
+ if (NandStatus & NAND_FAILURE) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NandReadBlock (
+ IN UINTN StartBlockIndex,
+ IN UINTN EndBlockIndex,
+ OUT VOID *Buffer,
+ OUT VOID *SpareBuffer
+)
+{
+ UINTN BlockIndex;
+ UINTN PageIndex;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
+ //For each block read number of pages
+ for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
+ Status = NandReadPage(BlockIndex, PageIndex, Buffer, SpareBuffer);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
+ }
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+NandWriteBlock (
+ IN UINTN StartBlockIndex,
+ IN UINTN EndBlockIndex,
+ OUT VOID *Buffer,
+ OUT VOID *SpareBuffer
+ )
+{
+ UINTN BlockIndex;
+ UINTN PageIndex;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
+ //Page programming.
+ for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
+ Status = NandWritePage(BlockIndex, PageIndex, Buffer, SpareBuffer);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
+ }
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+NandFlashReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ )
+{
+ UINTN BusyStall = 50; // microSeconds
+ UINTN ResetBusyTimeout = (1000000 / BusyStall); // 1 Second
+
+ //Send RESET command to device.
+ NandSendCommand(RESET_CMD);
+
+ //Wait for 1ms before we check status register.
+ gBS->Stall(1000);
+
+ //Check BIT#5 & BIT#6 in Status register to make sure RESET is done.
+ while ((NandReadStatus() & NAND_RESET_STATUS) != NAND_RESET_STATUS) {
+
+ //In case of extended verification, wait for extended amount of time
+ //to make sure device is reset.
+ if (ExtendedVerification) {
+ if (ResetBusyTimeout == 0) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ gBS->Stall(BusyStall);
+ ResetBusyTimeout--;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+NandFlashReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ UINTN NumBlocks;
+ UINTN EndBlockIndex;
+ EFI_STATUS Status;
+ UINT8 *SpareBuffer = NULL;
+
+ if (Buffer == NULL) {
+ Status = EFI_INVALID_PARAMETER;
+ goto exit;
+ }
+
+ if (Lba > LAST_BLOCK) {
+ Status = EFI_INVALID_PARAMETER;
+ goto exit;
+ }
+
+ if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
+ Status = EFI_BAD_BUFFER_SIZE;
+ goto exit;
+ }
+
+ NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
+ EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
+
+ SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
+ if (SpareBuffer == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto exit;
+ }
+
+ //Read block
+ Status = NandReadBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Read block fails: %x\n", Status));
+ goto exit;
+ }
+
+exit:
+ if (SpareBuffer != NULL) {
+ FreePool (SpareBuffer);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+NandFlashWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ )
+{
+ UINTN BlockIndex;
+ UINTN NumBlocks;
+ UINTN EndBlockIndex;
+ EFI_STATUS Status;
+ UINT8 *SpareBuffer = NULL;
+
+ if (Buffer == NULL) {
+ Status = EFI_INVALID_PARAMETER;
+ goto exit;
+ }
+
+ if (Lba > LAST_BLOCK) {
+ Status = EFI_INVALID_PARAMETER;
+ goto exit;
+ }
+
+ if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
+ Status = EFI_BAD_BUFFER_SIZE;
+ goto exit;
+ }
+
+ NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
+ EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
+
+ SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
+ if (SpareBuffer == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto exit;
+ }
+
+ // Erase block
+ for (BlockIndex = (UINTN)Lba; BlockIndex <= EndBlockIndex; BlockIndex++) {
+ Status = NandEraseBlock(BlockIndex);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Erase block failed. Status: %x\n", Status));
+ goto exit;
+ }
+ }
+
+ // Program data
+ Status = NandWriteBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Block write fails: %x\n", Status));
+ goto exit;
+ }
+
+exit:
+ if (SpareBuffer != NULL) {
+ FreePool (SpareBuffer);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+NandFlashFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_BLOCK_IO_PROTOCOL BlockIo =
+{
+ EFI_BLOCK_IO_INTERFACE_REVISION, // Revision
+ &NandFlashMedia, // *Media
+ NandFlashReset, // Reset
+ NandFlashReadBlocks, // ReadBlocks
+ NandFlashWriteBlocks, // WriteBlocks
+ NandFlashFlushBlocks // FlushBlocks
+};
+
+EFI_STATUS
+NandFlashInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ gNandFlashInfo = (NAND_FLASH_INFO *)AllocateZeroPool(sizeof(NAND_FLASH_INFO));
+
+ //Initialize GPMC module.
+ GpmcInit();
+
+ //Reset NAND part
+ NandFlashReset(&BlockIo, FALSE);
+
+ //Detect NAND part and populate gNandFlashInfo structure
+ Status = NandDetectPart();
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "Nand part id detection failure: Status: %x\n", Status));
+ return Status;
+ }
+
+ //Count total number of 512Bytes chunk based on the page size.
+ if (gNandFlashInfo->PageSize == PAGE_SIZE_512B) {
+ gNum512BytesChunks = 1;
+ } else if (gNandFlashInfo->PageSize == PAGE_SIZE_2K) {
+ gNum512BytesChunks = 4;
+ } else if (gNandFlashInfo->PageSize == PAGE_SIZE_4K) {
+ gNum512BytesChunks = 8;
+ }
+
+ gEccCode = (UINT8 *)AllocatePool(gNum512BytesChunks * 3);
+ if (gEccCode == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //Configure ECC
+ NandConfigureEcc();
+
+ //Patch EFI_BLOCK_IO_MEDIA structure.
+ NandFlashMedia.BlockSize = gNandFlashInfo->BlockSize;
+ NandFlashMedia.LastBlock = LAST_BLOCK;
+
+ //Publish BlockIO.
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gEfiBlockIoProtocolGuid, &BlockIo,
+ &gEfiDevicePathProtocolGuid, &gDevicePath,
+ NULL
+ );
+ return Status;
+}
+
diff --git a/BeagleBoardPkg/Flash/Flash.h b/BeagleBoardPkg/Flash/Flash.h
new file mode 100644
index 0000000000..533e416c7e
--- /dev/null
+++ b/BeagleBoardPkg/Flash/Flash.h
@@ -0,0 +1,118 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef FLASH_H
+#define FLASH_H
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#define PAGE_SIZE(x) ((x) & 0x01)
+#define PAGE_SIZE_2K_VAL (0x01UL)
+
+#define SPARE_AREA_SIZE(x) (((x) >> 2) & 0x01)
+#define SPARE_AREA_SIZE_64B_VAL (0x1UL)
+
+#define BLOCK_SIZE(x) (((x) >> 4) & 0x01)
+#define BLOCK_SIZE_128K_VAL (0x01UL)
+
+#define ORGANIZATION(x) (((x) >> 6) & 0x01)
+#define ORGANIZATION_X8 (0x0UL)
+#define ORGANIZATION_X16 (0x1UL)
+
+#define PAGE_SIZE_512B (512)
+#define PAGE_SIZE_2K (2048)
+#define PAGE_SIZE_4K (4096)
+#define SPARE_AREA_SIZE_16B (16)
+#define SPARE_AREA_SIZE_64B (64)
+
+#define BLOCK_SIZE_16K (16*1024)
+#define BLOCK_SIZE_128K (128*1024)
+
+#define BLOCK_COUNT (2048)
+#define LAST_BLOCK (BLOCK_COUNT - 1)
+
+#define ECC_POSITION 2
+
+//List of commands.
+#define RESET_CMD 0xFF
+#define READ_ID_CMD 0x90
+
+#define READ_STATUS_CMD 0x70
+
+#define PAGE_READ_CMD 0x00
+#define PAGE_READ_CONFIRM_CMD 0x30
+
+#define BLOCK_ERASE_CMD 0x60
+#define BLOCK_ERASE_CONFIRM_CMD 0xD0
+
+#define PROGRAM_PAGE_CMD 0x80
+#define PROGRAM_PAGE_CONFIRM_CMD 0x10
+
+//Nand status register bit definition
+#define NAND_SUCCESS (0x0UL << 0)
+#define NAND_FAILURE (0x1UL << 0)
+
+#define NAND_BUSY (0x0UL << 6)
+#define NAND_READY (0x1UL << 6)
+
+#define NAND_RESET_STATUS (0x60UL << 0)
+
+#define MAX_RETRY_COUNT 1500
+
+EFI_BLOCK_IO_MEDIA NandFlashMedia = {
+ SIGNATURE_32('n','a','n','d'), // MediaId
+ FALSE, // RemovableMedia
+ TRUE, // MediaPresent
+ TRUE, // LogicalPartition
+ FALSE, // ReadOnly
+ FALSE, // WriteCaching
+ 0, // BlockSize
+ 2, // IoAlign
+ 0, // Pad
+ 0 // LastBlock
+};
+
+typedef struct {
+ UINT8 ManufactureId;
+ UINT8 DeviceId;
+ UINT8 BlockAddressStart; //Start of the Block address in actual NAND
+ UINT8 PageAddressStart; //Start of the Page address in actual NAND
+} NAND_PART_INFO_TABLE;
+
+typedef struct {
+ UINT8 ManufactureId;
+ UINT8 DeviceId;
+ UINT8 Organization; //x8 or x16
+ UINT32 PageSize;
+ UINT32 SparePageSize;
+ UINT32 BlockSize;
+ UINT32 NumPagesPerBlock;
+ UINT8 BlockAddressStart; //Start of the Block address in actual NAND
+ UINT8 PageAddressStart; //Start of the Page address in actual NAND
+} NAND_FLASH_INFO;
+
+#endif //FLASH_H
diff --git a/BeagleBoardPkg/Flash/Flash.inf b/BeagleBoardPkg/Flash/Flash.inf
new file mode 100644
index 0000000000..bb089850e1
--- /dev/null
+++ b/BeagleBoardPkg/Flash/Flash.inf
@@ -0,0 +1,36 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NandFlash
+ FILE_GUID = 4d00ef14-c4e0-426b-81b7-30a00a14aad6
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = NandFlashInitialize
+
+
+[Sources.common]
+ Flash.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ UefiLib
+ UefiDriverEntryPoint
+ MemoryAllocationLib
+ IoLib
+
+[Guids]
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiCpuArchProtocolGuid
+
+[Pcd]
+ gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset
+
+[depex]
+ TRUE
\ No newline at end of file
diff --git a/BeagleBoardPkg/Gpio/Gpio.c b/BeagleBoardPkg/Gpio/Gpio.c
new file mode 100644
index 0000000000..7bc5478933
--- /dev/null
+++ b/BeagleBoardPkg/Gpio/Gpio.c
@@ -0,0 +1,135 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+
+#include
+
+#include
+
+EFI_STATUS
+Get (
+ IN EMBEDDED_GPIO *This,
+ IN EMBEDDED_GPIO_PIN Gpio,
+ OUT UINTN *Value
+ )
+{
+ UINTN Port;
+ UINTN Pin;
+ UINT32 DataInRegister;
+
+ if (Value == NULL)
+ {
+ return EFI_UNSUPPORTED;
+ }
+
+ Port = GPIO_PORT(Gpio);
+ Pin = GPIO_PIN(Gpio);
+
+ DataInRegister = GpioBase(Port) + GPIO_DATAIN;
+
+ if (MmioRead32(DataInRegister) & GPIO_DATAIN_MASK(Pin)) {
+ *Value = 1;
+ } else {
+ *Value = 0;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+Set (
+ IN EMBEDDED_GPIO *This,
+ IN EMBEDDED_GPIO_PIN Gpio,
+ IN EMBEDDED_GPIO_MODE Mode
+ )
+{
+ UINTN Port;
+ UINTN Pin;
+ UINT32 OutputEnableRegister;
+ UINT32 SetDataOutRegister;
+ UINT32 ClearDataOutRegister;
+
+ Port = GPIO_PORT(Gpio);
+ Pin = GPIO_PIN(Gpio);
+
+ OutputEnableRegister = GpioBase(Port) + GPIO_OE;
+ SetDataOutRegister = GpioBase(Port) + GPIO_SETDATAOUT;
+ ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT;
+
+ switch (Mode)
+ {
+ case GPIO_MODE_INPUT:
+ MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
+ break;
+
+ case GPIO_MODE_OUTPUT_0:
+ MmioWrite32(ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
+ MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
+ break;
+
+ case GPIO_MODE_OUTPUT_1:
+ MmioWrite32(SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
+ MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetMode (
+ IN EMBEDDED_GPIO *This,
+ IN EMBEDDED_GPIO_PIN Gpio,
+ OUT EMBEDDED_GPIO_MODE *Mode
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+SetPull (
+ IN EMBEDDED_GPIO *This,
+ IN EMBEDDED_GPIO_PIN Gpio,
+ IN EMBEDDED_GPIO_PULL Direction
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EMBEDDED_GPIO Gpio = {
+ Get,
+ Set,
+ GetMode,
+ SetPull
+};
+
+EFI_STATUS
+GpioInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL);
+ return Status;
+}
diff --git a/BeagleBoardPkg/Gpio/Gpio.inf b/BeagleBoardPkg/Gpio/Gpio.inf
new file mode 100644
index 0000000000..c903ed9052
--- /dev/null
+++ b/BeagleBoardPkg/Gpio/Gpio.inf
@@ -0,0 +1,33 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Gpio
+ FILE_GUID = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = GpioInitialize
+
+
+[Sources.common]
+ Gpio.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ IoLib
+ UefiDriverEntryPoint
+ OmapLib
+
+[Guids]
+
+[Protocols]
+ gEmbeddedGpioProtocolGuid
+
+[Pcd]
+
+[depex]
+ TRUE
\ No newline at end of file
diff --git a/BeagleBoardPkg/Include/Library/BeagleBoardSystemLib.h b/BeagleBoardPkg/Include/Library/BeagleBoardSystemLib.h
new file mode 100644
index 0000000000..93a6113262
--- /dev/null
+++ b/BeagleBoardPkg/Include/Library/BeagleBoardSystemLib.h
@@ -0,0 +1,36 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BEAGLEBOARD_YSTEMLIB_H__
+#define __BEAGLEBOARD_YSTEMLIB_H__
+
+VOID
+EFIAPI
+GoLittleEndian (
+ UINTN ImageAddress
+ );
+
+VOID
+EFIAPI
+ResetSystem (
+ IN EFI_RESET_TYPE ResetType
+ );
+
+VOID
+EFIAPI
+ShutdownEfi (
+ VOID
+ );
+
+#endif // __BEAGLEBOARD_YSTEMLIB_H__
diff --git a/BeagleBoardPkg/Include/Library/OmapLib.h b/BeagleBoardPkg/Include/Library/OmapLib.h
new file mode 100644
index 0000000000..e2845ca7df
--- /dev/null
+++ b/BeagleBoardPkg/Include/Library/OmapLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAPLIB_H__
+#define __OMAPLIB_H__
+
+UINT32
+GpioBase (
+ IN UINTN Port
+ );
+
+UINT32
+TimerBase (
+ IN UINTN Timer
+ );
+
+UINTN
+InterruptVectorForTimer (
+ IN UINTN TImer
+ );
+
+UINT32
+UartBase (
+ IN UINTN Uart
+ );
+
+#endif // __OMAPLIB_H__
+
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530.h b/BeagleBoardPkg/Include/Omap3530/Omap3530.h
new file mode 100644
index 0000000000..7d3b011327
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530.h
@@ -0,0 +1,38 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530_H__
+#define __OMAP3530_H__
+
+#include "Omap3530Gpio.h"
+#include "Omap3530Interrupt.h"
+#include "Omap3530Prcm.h"
+#include "Omap3530Timer.h"
+#include "Omap3530Uart.h"
+#include "Omap3530Usb.h"
+#include "Omap3530MMCHS.h"
+#include "Omap3530I2c.h"
+#include "Omap3530PadConfiguration.h"
+#include "Omap3530Gpmc.h"
+
+//CONTROL_PBIAS_LITE
+#define CONTROL_PBIAS_LITE 0x48002520
+#define PBIASLITEVMODE0 (0x1UL << 0)
+#define PBIASLITEPWRDNZ0 (0x1UL << 1)
+#define PBIASSPEEDCTRL0 (0x1UL << 2)
+#define PBIASLITEVMODE1 (0x1UL << 8)
+#define PBIASLITEWRDNZ1 (0x1UL << 9)
+
+#endif // __OMAP3530_H__
+
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Gpio.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Gpio.h
new file mode 100644
index 0000000000..6e825a725c
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Gpio.h
@@ -0,0 +1,131 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530GPIO_H__
+#define __OMAP3530GPIO_H__
+
+#define GPIO1_BASE (0x48310000)
+#define GPIO2_BASE (0x49050000)
+#define GPIO3_BASE (0x49052000)
+#define GPIO4_BASE (0x49054000)
+#define GPIO5_BASE (0x49056000)
+#define GPIO6_BASE (0x49058000)
+
+#define GPIO_SYSCONFIG (0x0010)
+#define GPIO_SYSSTATUS (0x0014)
+#define GPIO_IRQSTATUS1 (0x0018)
+#define GPIO_IRQENABLE1 (0x001C)
+#define GPIO_WAKEUPENABLE (0x0020)
+#define GPIO_IRQSTATUS2 (0x0028)
+#define GPIO_IRQENABLE2 (0x002C)
+#define GPIO_CTRL (0x0030)
+#define GPIO_OE (0x0034)
+#define GPIO_DATAIN (0x0038)
+#define GPIO_DATAOUT (0x003C)
+#define GPIO_LEVELDETECT0 (0x0040)
+#define GPIO_LEVELDETECT1 (0x0044)
+#define GPIO_RISINGDETECT (0x0048)
+#define GPIO_FALLINGDETECT (0x004C)
+#define GPIO_DEBOUNCENABLE (0x0050)
+#define GPIO_DEBOUNCINGTIME (0x0054)
+#define GPIO_CLEARIRQENABLE1 (0x0060)
+#define GPIO_SETIRQENABLE1 (0x0064)
+#define GPIO_CLEARIRQENABLE2 (0x0070)
+#define GPIO_SETIRQENABLE2 (0x0074)
+#define GPIO_CLEARWKUENA (0x0080)
+#define GPIO_SETWKUENA (0x0084)
+#define GPIO_CLEARDATAOUT (0x0090)
+#define GPIO_SETDATAOUT (0x0094)
+
+#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
+#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
+#define GPIO_SYSCONFIG_IDLEMODE_NONE (1UL << 3)
+#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
+#define GPIO_SYSCONFIG_ENAWAKEUP_MASK (1UL << 2)
+#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
+#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
+#define GPIO_SYSCONFIG_SOFTRESET_MASK (1UL << 1)
+#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
+#define GPIO_SYSCONFIG_SOFTRESET_RESET (1UL << 1)
+#define GPIO_SYSCONFIG_AUTOIDLE_MASK (1UL << 0)
+#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
+#define GPIO_SYSCONFIG_AUTOIDLE_ON (1UL << 0)
+
+#define GPIO_SYSSTATUS_RESETDONE_MASK (1UL << 0)
+#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
+#define GPIO_SYSSTATUS_RESETDONE_COMPLETE (1UL << 0)
+
+#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
+#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
+#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
+#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
+
+#define GPIO_IRQENABLE_MASK(x) (1UL << (x))
+#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
+#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
+
+#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
+#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
+#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
+
+#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
+#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
+#define GPIO_CTRL_GATINGRATIO_DIV_2 (1UL << 1)
+#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
+#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
+#define GPIO_CTRL_DISABLEMODULE_MASK (1UL << 0)
+#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
+#define GPIO_CTRL_DISABLEMODULE_DISABLE (1UL << 0)
+
+#define GPIO_OE_MASK(x) (1UL << (x))
+#define GPIO_OE_OUTPUT(x) (0UL << (x))
+#define GPIO_OE_INPUT(x) (1UL << (x))
+
+#define GPIO_DATAIN_MASK(x) (1UL << (x))
+
+#define GPIO_DATAOUT_MASK(x) (1UL << (x))
+
+#define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
+#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
+#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
+
+#define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
+#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
+#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
+
+#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
+#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
+#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
+
+#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
+#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
+#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
+
+#define GPIO_DEBOUNCINGTIME_MASK (0xFF)
+#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
+
+#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
+
+#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
+
+#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
+
+#define GPIO_SETWKUENA_BIT(x) (1UL << (x))
+
+#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
+
+#define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
+
+#endif // __OMAP3530GPIO_H__
+
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Gpmc.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Gpmc.h
new file mode 100644
index 0000000000..907806c378
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Gpmc.h
@@ -0,0 +1,107 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530GPMC_H__
+#define __OMAP3530GPMC_H__
+
+#define GPMC_BASE (0x6E000000)
+
+//GPMC NAND definitions.
+#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
+#define SMARTIDLEMODE (0x2UL << 3)
+
+#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
+#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
+#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
+
+#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
+#define TIMEOUTENABLE (0x1UL << 0)
+#define TIMEOUTDISABLE (0x0UL << 0)
+
+#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
+#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
+
+#define GPMC_CONFIG (GPMC_BASE + 0x50)
+#define WRITEPROTECT_HIGH (0x1UL << 4)
+#define WRITEPROTECT_LOW (0x0UL << 4)
+
+#define GPMC_STATUS (GPMC_BASE + 0x54)
+
+#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
+#define DEVICETYPE_NOR (0x0UL << 10)
+#define DEVICETYPE_NAND (0x2UL << 10)
+#define DEVICESIZE_X8 (0x0UL << 12)
+#define DEVICESIZE_X16 (0x1UL << 12)
+
+#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
+#define CSONTIME (0x0UL << 0)
+#define CSRDOFFTIME (0x14UL << 8)
+#define CSWROFFTIME (0x14UL << 16)
+
+#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
+#define ADVRDOFFTIME (0x14UL << 8)
+#define ADVWROFFTIME (0x14UL << 16)
+
+#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
+#define OEONTIME (0x1UL << 0)
+#define OEOFFTIME (0xFUL << 8)
+#define WEONTIME (0x1UL << 16)
+#define WEOFFTIME (0xFUL << 24)
+
+#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
+#define RDCYCLETIME (0x14UL << 0)
+#define WRCYCLETIME (0x14UL << 8)
+#define RDACCESSTIME (0xCUL << 16)
+#define PAGEBURSTACCESSTIME (0x1UL << 24)
+
+#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
+#define CYCLE2CYCLESAMECSEN (0x1UL << 7)
+#define CYCLE2CYCLEDELAY (0xAUL << 8)
+#define WRDATAONADMUXBUS (0xFUL << 16)
+#define WRACCESSTIME (0x1FUL << 24)
+
+#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
+#define BASEADDRESS (0x30UL << 0)
+#define CSVALID (0x1UL << 6)
+#define MASKADDRESS_128MB (0x8UL << 8)
+
+#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
+#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
+#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
+
+#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
+#define ECCENABLE (0x1UL << 0)
+#define ECCDISABLE (0x0UL << 0)
+#define ECCCS_0 (0x0UL << 1)
+#define ECC16B (0x1UL << 7)
+
+#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
+#define ECCPOINTER_REG1 (0x1UL << 0)
+#define ECCCLEAR (0x1UL << 8)
+
+#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
+#define ECCSIZE0_512BYTES (0xFFUL << 12)
+#define ECCSIZE1_512BYTES (0xFFUL << 22)
+
+#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
+#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
+#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
+#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
+#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
+#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
+#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
+#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
+#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
+
+#endif //__OMAP3530GPMC_H__
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530I2c.h b/BeagleBoardPkg/Include/Omap3530/Omap3530I2c.h
new file mode 100644
index 0000000000..5477b61645
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530I2c.h
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530I2C_H__
+#define __OMAP3530I2C_H__
+
+//I2C register definitions.
+#define I2C1BASE 0x48070000
+
+#define I2C_IE (I2C1BASE + 0x4)
+#define XRDY_IE (0x1UL << 4)
+#define RRDY_IE (0x1UL << 3)
+#define ARDY_IE (0x1UL << 2)
+#define NACK_IE (0x1UL << 1)
+
+#define I2C_STAT (I2C1BASE + 0x8)
+#define BB (0x1UL << 12)
+#define XRDY (0x1UL << 4)
+#define RRDY (0x1UL << 3)
+#define ARDY (0x1UL << 2)
+#define NACK (0x1UL << 1)
+
+#define I2C_WE (I2C1BASE + 0xC)
+#define I2C_SYSS (I2C1BASE + 0x10)
+#define I2C_BUF (I2C1BASE + 0x14)
+#define I2C_CNT (I2C1BASE + 0x18)
+#define I2C_DATA (I2C1BASE + 0x1C)
+#define I2C_SYSC (I2C1BASE + 0x20)
+
+#define I2C_CON (I2C1BASE + 0x24)
+#define STT (0x1UL << 0)
+#define STP (0x1UL << 1)
+#define XSA (0x1UL << 8)
+#define TRX (0x1UL << 9)
+#define MST (0x1UL << 10)
+#define I2C_EN (0x1UL << 15)
+
+#define I2C_OA0 (I2C1BASE + 0x28)
+#define I2C_SA (I2C1BASE + 0x2C)
+#define I2C_PSC (I2C1BASE + 0x30)
+#define I2C_SCLL (I2C1BASE + 0x34)
+#define I2C_SCLH (I2C1BASE + 0x38)
+#define I2C_SYSTEST (I2C1BASE + 0x3C)
+#define I2C_BUFSTAT (I2C1BASE + 0x40)
+#define I2C_OA1 (I2C1BASE + 0x44)
+#define I2C_OA2 (I2C1BASE + 0x48)
+#define I2C_OA3 (I2C1BASE + 0x4C)
+#define I2C_ACTOA (I2C1BASE + 0x50)
+#define I2C_SBLOCK (I2C1BASE + 0x54)
+
+#endif //__OMAP3530I2C_H__
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Interrupt.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Interrupt.h
new file mode 100644
index 0000000000..129d8c0469
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Interrupt.h
@@ -0,0 +1,46 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530INTERRUPT_H__
+#define __OMAP3530INTERRUPT_H__
+
+#define INTERRUPT_BASE (0x48200000)
+
+#define INT_NROF_VECTORS (96)
+#define MAX_VECTOR (INT_NROF_VECTORS - 1)
+#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
+#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
+#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
+#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
+#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
+#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
+#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
+#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
+#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
+#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
+#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
+#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
+#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
+#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
+#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
+#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
+#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
+#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
+#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
+
+#define INTCPS_SIR_IRQ_MASK (0x7F)
+#define INTCPS_CONTROL_NEWIRQAGR (1UL << 0)
+
+#endif // __OMAP3530INTERRUPT_H__
+
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530MMCHS.h b/BeagleBoardPkg/Include/Omap3530/Omap3530MMCHS.h
new file mode 100755
index 0000000000..5ade843801
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530MMCHS.h
@@ -0,0 +1,208 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530SDIO_H__
+#define __OMAP3530SDIO_H__
+
+//MMC/SD/SDIO1 register definitions.
+#define MMCHS1BASE 0x4809C000
+#define MMC_REFERENCE_CLK (96000000)
+
+#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
+#define SOFTRESET (0x1UL << 1)
+#define ENAWAKEUP (0x1UL << 2)
+
+#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
+#define RESETDONE_MASK (0x1UL << 0)
+#define RESETDONE (0x1UL << 0)
+
+#define MMCHS_CSRE (MMCHS1BASE + 0x24)
+#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
+
+#define MMCHS_CON (MMCHS1BASE + 0x2C)
+#define OD (0x1UL << 0)
+#define NOINIT (0x0UL << 1)
+#define INIT (0x1UL << 1)
+#define HR (0x1UL << 2)
+#define STR (0x1UL << 3)
+#define MODE (0x1UL << 4)
+#define DW8_1_4_BIT (0x0UL << 5)
+#define DW8_8_BIT (0x1UL << 5)
+#define MIT (0x1UL << 6)
+#define CDP (0x1UL << 7)
+#define WPP (0x1UL << 8)
+#define CTPL (0x1UL << 11)
+#define CEATA_OFF (0x0UL << 12)
+#define CEATA_ON (0x1UL << 12)
+
+#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
+
+#define MMCHS_BLK (MMCHS1BASE + 0x104)
+#define BLEN_512BYTES (0x200UL << 0)
+
+#define MMCHS_ARG (MMCHS1BASE + 0x108)
+
+#define MMCHS_CMD (MMCHS1BASE + 0x10C)
+#define DE_ENABLE (0x1UL << 0)
+#define BCE_ENABLE (0x1UL << 1)
+#define ACEN_ENABLE (0x1UL << 2)
+#define DDIR_READ (0x1UL << 4)
+#define DDIR_WRITE (0x0UL << 4)
+#define MSBS_SGLEBLK (0x0UL << 5)
+#define MSBS_MULTBLK (0x1UL << 5)
+#define RSP_TYPE_MASK (0x3UL << 16)
+#define RSP_TYPE_136BITS (0x1UL << 16)
+#define RSP_TYPE_48BITS (0x2UL << 16)
+#define CCCE_ENABLE (0x1UL << 19)
+#define CICE_ENABLE (0x1UL << 20)
+#define DP_ENABLE (0x1UL << 21)
+#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
+
+#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
+#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
+#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
+#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
+#define MMCHS_DATA (MMCHS1BASE + 0x120)
+
+#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
+#define CMDI_MASK (0x1UL << 0)
+#define CMDI_ALLOWED (0x0UL << 0)
+#define CMDI_NOT_ALLOWED (0x1UL << 0)
+#define DATI_MASK (0x1UL << 1)
+#define DATI_ALLOWED (0x0UL << 1)
+#define DATI_NOT_ALLOWED (0x1UL << 1)
+
+#define MMCHS_HCTL (MMCHS1BASE + 0x128)
+#define DTW_1_BIT (0x0UL << 1)
+#define DTW_4_BIT (0x1UL << 1)
+#define SDBP_MASK (0x1UL << 8)
+#define SDBP_OFF (0x0UL << 8)
+#define SDBP_ON (0x1UL << 8)
+#define SDVS_1_8_V (0x5UL << 9)
+#define SDVS_3_0_V (0x6UL << 9)
+#define IWE (0x1UL << 24)
+
+#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
+#define ICE (0x1UL << 0)
+#define ICS_MASK (0x1UL << 1)
+#define ICS (0x1UL << 1)
+#define CEN (0x1UL << 2)
+#define CLKD_MASK (0x3FFUL << 6)
+#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
+#define CLKD_400KHZ (0xF0UL)
+#define DTO_MASK (0xFUL << 16)
+#define DTO_VAL (0xEUL << 16)
+#define SRA (0x1UL << 24)
+#define SRC_MASK (0x1UL << 25)
+#define SRC (0x1UL << 25)
+#define SRD (0x1UL << 26)
+
+#define MMCHS_STAT (MMCHS1BASE + 0x130)
+#define CC (0x1UL << 0)
+#define TC (0x1UL << 1)
+#define BWR (0x1UL << 4)
+#define BRR (0x1UL << 5)
+#define ERRI (0x1UL << 15)
+#define CTO (0x1UL << 16)
+#define DTO (0x1UL << 20)
+#define DCRC (0x1UL << 21)
+#define DEB (0x1UL << 22)
+
+#define MMCHS_IE (MMCHS1BASE + 0x134)
+#define CC_EN (0x1UL << 0)
+#define TC_EN (0x1UL << 1)
+#define BWR_EN (0x1UL << 4)
+#define BRR_EN (0x1UL << 5)
+#define CTO_EN (0x1UL << 16)
+#define CCRC_EN (0x1UL << 17)
+#define CEB_EN (0x1UL << 18)
+#define CIE_EN (0x1UL << 19)
+#define DTO_EN (0x1UL << 20)
+#define DCRC_EN (0x1UL << 21)
+#define DEB_EN (0x1UL << 22)
+#define CERR_EN (0x1UL << 28)
+#define BADA_EN (0x1UL << 29)
+
+#define MMCHS_ISE (MMCHS1BASE + 0x138)
+#define CC_SIGEN (0x1UL << 0)
+#define TC_SIGEN (0x1UL << 1)
+#define BWR_SIGEN (0x1UL << 4)
+#define BRR_SIGEN (0x1UL << 5)
+#define CTO_SIGEN (0x1UL << 16)
+#define CCRC_SIGEN (0x1UL << 17)
+#define CEB_SIGEN (0x1UL << 18)
+#define CIE_SIGEN (0x1UL << 19)
+#define DTO_SIGEN (0x1UL << 20)
+#define DCRC_SIGEN (0x1UL << 21)
+#define DEB_SIGEN (0x1UL << 22)
+#define CERR_SIGEN (0x1UL << 28)
+#define BADA_SIGEN (0x1UL << 29)
+
+#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
+
+#define MMCHS_CAPA (MMCHS1BASE + 0x140)
+#define VS30 (0x1UL << 25)
+#define VS18 (0x1UL << 26)
+
+#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
+#define MMCHS_REV (MMCHS1BASE + 0x1FC)
+
+#define CMD0 INDX(0)
+#define CMD0_INT_EN (CC_EN | CEB_EN)
+
+#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
+#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
+
+#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
+#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
+#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
+#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
+
+#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
+#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
+#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
+#define CMD8_ARG (0x0UL << 12 | 0x1UL << 8 | 0xCEUL << 0)
+
+#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
+#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
+#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
+#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
+
+#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
+#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
+
+#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
+#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
+#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
+
+#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
+#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
+#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
+
+#endif //__OMAP3530SDIO_H__
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530PadConfiguration.h b/BeagleBoardPkg/Include/Omap3530/Omap3530PadConfiguration.h
new file mode 100644
index 0000000000..baae8c68c8
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530PadConfiguration.h
@@ -0,0 +1,298 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530_PAD_CONFIGURATION_H__
+#define __OMAP3530_PAD_CONFIGURATION_H__
+
+#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
+
+//Pin definition
+#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
+#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
+#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
+#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
+#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
+#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
+#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
+#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
+#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
+#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
+#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
+#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
+#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
+#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
+#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
+#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
+#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
+#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
+#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
+#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
+#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
+#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
+#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
+#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
+#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
+#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
+#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
+#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
+#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
+#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
+#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
+#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
+#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
+#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
+#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
+#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
+#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
+#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
+#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
+#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
+#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
+#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
+#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
+#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
+#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
+#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
+#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
+#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
+#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
+#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
+#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
+#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
+#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
+#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
+#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
+#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
+#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
+#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
+#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
+#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
+#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
+#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
+#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
+#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
+#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
+#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
+#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
+#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
+#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
+#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
+#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
+#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
+#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
+#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
+#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
+#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
+#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
+#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
+#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
+#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
+#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
+#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
+#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
+#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
+#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
+#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
+#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
+#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
+#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
+#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
+#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
+#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
+#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
+#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
+#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
+#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
+#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
+#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
+#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
+#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
+#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
+#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
+#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
+#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
+#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
+#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
+#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
+#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
+#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
+#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
+#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
+#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
+#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
+#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
+#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
+#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
+#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
+#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
+#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
+#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
+#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
+#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
+#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
+#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
+#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
+#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
+#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
+#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
+#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
+#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
+#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
+#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
+#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
+#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
+#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
+#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
+#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
+#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
+#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
+#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
+#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
+#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
+#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
+#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
+#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
+#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
+#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
+#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
+#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
+#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
+#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
+#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
+#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
+#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
+#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
+#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
+#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
+#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
+#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
+#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
+#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
+#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
+#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
+#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
+#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
+#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
+#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
+#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
+#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
+#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
+#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
+#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
+#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
+#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
+#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
+#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
+#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
+#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
+#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
+#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
+#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
+#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
+#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
+#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
+#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
+#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
+#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
+#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
+#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
+#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
+#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
+#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
+#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
+#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
+#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
+#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
+#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
+#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
+#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
+#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
+#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
+#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
+#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
+#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
+#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
+#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
+#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
+#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
+#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
+#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
+#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
+#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
+#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
+#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
+#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
+#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
+#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
+#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
+#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
+#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
+#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
+#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
+#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
+#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
+#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
+#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
+#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
+#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
+#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
+#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
+#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
+#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
+#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
+#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
+#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
+#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
+#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
+#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
+
+//Mux modes
+#define MUXMODE0 (0x0UL)
+#define MUXMODE1 (0x1UL)
+#define MUXMODE2 (0x2UL)
+#define MUXMODE3 (0x3UL)
+#define MUXMODE4 (0x4UL)
+#define MUXMODE5 (0x5UL)
+#define MUXMODE6 (0x6UL)
+#define MUXMODE7 (0x7UL)
+
+//Pad configuration register.
+#define PAD_CONFIG_MASK (0xFFFFUL)
+#define MUXMODE_OFFSET 0
+#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
+#define PULL_CONFIG_OFFSET 3
+#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
+#define INPUTENABLE_OFFSET 8
+#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
+#define OFFMODE_VALUE_OFFSET 9
+#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
+#define WAKEUP_OFFSET 14
+#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
+
+#define PULLUDDISABLE (0x0UL << 0)
+#define PULLUDENABLE (0x1UL << 0)
+#define PULLTYPENOSELECT (0x0UL << 1)
+#define PULLTYPESELECT (0x1UL << 1)
+
+#define OUTPUT (0x0UL) //Pin is configured in output only mode.
+#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
+
+typedef struct {
+ UINTN Pin;
+ UINTN MuxMode;
+ UINTN PullConfig;
+ UINTN InputEnable;
+} PAD_CONFIGURATION;
+
+#endif //__OMAP3530_PAD_CONFIGURATION_H__
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Prcm.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Prcm.h
new file mode 100644
index 0000000000..036f8bcece
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Prcm.h
@@ -0,0 +1,164 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530PRCM_H__
+#define __OMAP3530PRCM_H__
+
+#define CM_FCLKEN1_CORE (0x48004A00)
+#define CM_FCLKEN3_CORE (0x48004A08)
+#define CM_ICLKEN1_CORE (0x48004A10)
+#define CM_ICLKEN3_CORE (0x48004A18)
+#define CM_CLKEN2_PLL (0x48004D04)
+#define CM_CLKSEL4_PLL (0x48004D4C)
+#define CM_CLKSEL5_PLL (0x48004D50)
+#define CM_FCLKEN_USBHOST (0x48005400)
+#define CM_ICLKEN_USBHOST (0x48005410)
+
+//Wakeup clock defintion
+#define CM_FCLKEN_WKUP (0x48004C00)
+#define CM_ICLKEN_WKUP (0x48004C10)
+
+//Peripheral clock definition
+#define CM_FCLKEN_PER (0x48005000)
+#define CM_ICLKEN_PER (0x48005010)
+#define CM_CLKSEL_PER (0x48005040)
+
+//Reset management definition
+#define PRM_RSTCTRL (0x48307250)
+#define PRM_RSTST (0x48307258)
+
+//CORE clock
+#define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
+#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
+#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
+
+#define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
+#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
+#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
+
+#define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
+#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
+#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
+
+#define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
+#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
+#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
+
+#define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
+#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
+#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
+
+#define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
+#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
+#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
+
+#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
+#define CM_CLKEN_ENABLE (7UL << 0)
+
+#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
+#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
+
+#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
+
+#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1)
+#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
+#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1)
+
+#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0)
+#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
+#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0)
+
+#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0)
+#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
+#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0)
+
+//Wakeup functional clock
+#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
+#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
+
+#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
+#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
+
+//Wakeup interface clock
+#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
+#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
+
+#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
+#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
+
+//Peripheral functional clock
+#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
+#define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
+
+#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
+#define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
+
+#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
+#define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11)
+
+#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
+#define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
+
+#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
+#define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
+
+#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
+#define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
+
+#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
+#define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
+
+#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
+#define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
+
+//Peripheral interface clock
+#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
+#define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
+
+#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
+#define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
+
+#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
+#define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11)
+
+#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
+#define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
+
+#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
+#define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
+
+#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
+#define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
+
+#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
+#define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
+
+#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
+#define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
+
+//Timer source clock selection
+#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
+#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1)
+
+#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
+#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2)
+
+//Reset management (Global and Cold reset)
+#define RST_GS (0x1UL << 1)
+#define RST_DPLL3 (0x1UL << 2)
+#define GLOBAL_SW_RST (0x1UL << 1)
+#define GLOBAL_COLD_RST (0x0UL << 0)
+
+#endif // __OMAP3530PRCM_H__
+
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Timer.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Timer.h
new file mode 100644
index 0000000000..1c43b3ee32
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Timer.h
@@ -0,0 +1,82 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530TIMER_H__
+#define __OMAP3530TIMER_H__
+
+#define GPTIMER1_BASE (0x48313000)
+#define GPTIMER2_BASE (0x49032000)
+#define GPTIMER3_BASE (0x49034000)
+#define GPTIMER4_BASE (0x49036000)
+#define GPTIMER5_BASE (0x49038000)
+#define GPTIMER6_BASE (0x4903A000)
+#define GPTIMER7_BASE (0x4903C000)
+#define GPTIMER8_BASE (0x4903E000)
+#define GPTIMER9_BASE (0x49040000)
+#define GPTIMER10_BASE (0x48086000)
+#define GPTIMER11_BASE (0x48088000)
+#define GPTIMER12_BASE (0x48304000)
+#define WDTIMER2_BASE (0x48314000)
+
+#define GPTIMER_TIOCP_CFG (0x0010)
+#define GPTIMER_TISTAT (0x0014)
+#define GPTIMER_TISR (0x0018)
+#define GPTIMER_TIER (0x001C)
+#define GPTIMER_TWER (0x0020)
+#define GPTIMER_TCLR (0x0024)
+#define GPTIMER_TCRR (0x0028)
+#define GPTIMER_TLDR (0x002C)
+#define GPTIMER_TTGR (0x0030)
+#define GPTIMER_TWPS (0x0034)
+#define GPTIMER_TMAR (0x0038)
+#define GPTIMER_TCAR1 (0x003C)
+#define GPTIMER_TSICR (0x0040)
+#define GPTIMER_TCAR2 (0x0044)
+#define GPTIMER_TPIR (0x0048)
+#define GPTIMER_TNIR (0x004C)
+#define GPTIMER_TCVR (0x0050)
+#define GPTIMER_TOCR (0x0054)
+#define GPTIMER_TOWR (0x0058)
+
+#define WSPR (0x048)
+
+#define TISR_TCAR_IT_FLAG_MASK (1UL << 2)
+#define TISR_OVF_IT_FLAG_MASK (1UL << 1)
+#define TISR_MAT_IT_FLAG_MASK (1UL << 0)
+#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
+
+#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
+#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1)
+#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
+#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
+
+#define TISR_TCAR_IT_FLAG_CLEAR (1UL << 2)
+#define TISR_OVF_IT_FLAG_CLEAR (1UL << 1)
+#define TISR_MAT_IT_FLAG_CLEAR (1UL << 0)
+#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
+
+#define TCLR_AR_AUTORELOAD (1UL << 1)
+#define TCLR_AR_ONESHOT (0UL << 1)
+#define TCLR_ST_ON (1UL << 0)
+#define TCLR_ST_OFF (0UL << 0)
+
+#define TIER_TCAR_IT_ENABLE (1UL << 2)
+#define TIER_TCAR_IT_DISABLE (0UL << 2)
+#define TIER_OVF_IT_ENABLE (1UL << 1)
+#define TIER_OVF_IT_DISABLE (0UL << 1)
+#define TIER_MAT_IT_ENABLE (1UL << 0)
+#define TIER_MAT_IT_DISABLE (0UL << 0)
+
+#endif // __OMAP3530TIMER_H__
+
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Uart.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Uart.h
new file mode 100644
index 0000000000..aef1c4bab9
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Uart.h
@@ -0,0 +1,53 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530UART_H__
+#define __OMAP3530UART_H__
+
+#define UART1_BASE (0x4806A000)
+#define UART2_BASE (0x4806C000)
+#define UART3_BASE (0x49020000)
+
+#define UART_DLL_REG (0x0000)
+#define UART_RBR_REG (0x0000)
+#define UART_THR_REG (0x0000)
+#define UART_DLH_REG (0x0004)
+#define UART_FCR_REG (0x0008)
+#define UART_LCR_REG (0x000C)
+#define UART_MCR_REG (0x0010)
+#define UART_LSR_REG (0x0014)
+#define UART_MDR1_REG (0x0020)
+
+#define UART_FCR_TX_FIFO_CLEAR (1UL << 3)
+#define UART_FCR_RX_FIFO_CLEAR (1UL << 3)
+#define UART_FCR_FIFO_ENABLE (1UL << 3)
+
+#define UART_LCR_DIV_EN_ENABLE (1UL << 7)
+#define UART_LCR_DIV_EN_DISABLE (0UL << 7)
+#define UART_LCR_CHAR_LENGTH_8 (3UL << 0)
+
+#define UART_MCR_RTS_FORCE_ACTIVE (1UL << 1)
+#define UART_MCR_DTR_FORCE_ACTIVE (1UL << 0)
+
+#define UART_LSR_TX_FIFO_E_MASK (1UL << 5)
+#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
+#define UART_LSR_TX_FIFO_E_EMPTY (1UL << 5)
+#define UART_LSR_RX_FIFO_E_MASK (1UL << 0)
+#define UART_LSR_RX_FIFO_E_NOT_EMPTY (1UL << 0)
+#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
+
+#define UART_MDR1_MODE_SELECT_DISABLE (7UL << 0)
+#define UART_MDR1_MODE_SELECT_UART_16X (0UL << 0)
+
+#endif // __OMAP3530UART_H__
diff --git a/BeagleBoardPkg/Include/Omap3530/Omap3530Usb.h b/BeagleBoardPkg/Include/Omap3530/Omap3530Usb.h
new file mode 100644
index 0000000000..5ffaa9d8e4
--- /dev/null
+++ b/BeagleBoardPkg/Include/Omap3530/Omap3530Usb.h
@@ -0,0 +1,42 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __OMAP3530USB_H__
+#define __OMAP3530USB_H__
+
+#define USB_BASE (0x48060000)
+
+#define UHH_SYSCONFIG (USB_BASE + 0x4010)
+#define UHH_HOSTCONFIG (USB_BASE + 0x4040)
+
+#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
+
+#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY (1UL << 12)
+#define UHH_SYSCONFIG_CLOCKACTIVITY_ON (1UL << 8)
+#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY (1UL << 3)
+#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
+#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
+
+#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
+#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
+#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
+#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
+#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4)
+#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3)
+#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2)
+#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
+#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
+
+#endif // __OMAP3530USB_H__
+
diff --git a/BeagleBoardPkg/Include/TPS65950.h b/BeagleBoardPkg/Include/TPS65950.h
new file mode 100644
index 0000000000..4b69099219
--- /dev/null
+++ b/BeagleBoardPkg/Include/TPS65950.h
@@ -0,0 +1,46 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __TPS65950_H__
+#define __TPS65950_H__
+
+#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF)
+#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF)
+#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF))
+
+//I2C Address group
+#define I2C_ADDR_GRP_ID1 0x48
+#define I2C_ADDR_GRP_ID2 0x49
+#define I2C_ADDR_GRP_ID3 0x4A
+#define I2C_ADDR_GRP_ID4 0x4B
+#define I2C_ADDR_GRP_ID5 0x12
+
+//MMC definitions.
+#define VMMC1_DEV_GRP 0x82
+#define DEV_GRP_P1 (0x01UL << 5)
+
+#define VMMC1_DEDICATED_REG 0x85
+#define VSEL_1_85V 0x0
+#define VSEL_2_85V 0x1
+#define VSEL_3_00V 0x2
+#define VSEL_3_15V 0x3
+
+//LEDEN register
+#define LEDEN 0xEE
+#define LEDAON (0x1UL << 0)
+#define LEDBON (0x1UL << 1)
+#define LEDAPWM (0x1UL << 4)
+#define LEDBPWM (0x1UL << 5)
+
+#endif //__TPS65950_H__
diff --git a/BeagleBoardPkg/InterruptDxe/HardwareInterrupt.c b/BeagleBoardPkg/InterruptDxe/HardwareInterrupt.c
new file mode 100644
index 0000000000..97361ffbc1
--- /dev/null
+++ b/BeagleBoardPkg/InterruptDxe/HardwareInterrupt.c
@@ -0,0 +1,339 @@
+/** @file
+ Template for Metronome Architecture Protocol driver of the ARM flavor
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+//
+// Notifications
+//
+VOID *CpuProtocolNotificationToken = NULL;
+EFI_EVENT CpuProtocolNotificationEvent = (EFI_EVENT)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+
+HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[INT_NROF_VECTORS];
+
+/**
+ Shutdown our hardware
+
+ DXE Core will disable interrupts and turn off the timer and disable interrupts
+ after all the event handlers have run.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ // Disable all interrupts
+ MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
+ MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
+ MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
+ MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+}
+
+/**
+ Register Handler for the specified interrupt source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param Handler Callback for interrupt. NULL to unregister
+
+ @retval EFI_SUCCESS Source was updated to support Handler.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+RegisterInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
+ )
+{
+ if (Source > MAX_VECTOR) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gRegisteredInterruptHandlers[Source] = Handler;
+
+ return This->EnableInterruptSource(This, Source);
+}
+
+
+/**
+ Enable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt enabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+EnableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ UINTN Bank;
+ UINTN Bit;
+
+ if (Source > MAX_VECTOR) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ Bank = Source / 32;
+ Bit = 1UL << (Source % 32);
+
+ MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Disable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt disabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+DisableInterruptSource(
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ UINTN Bank;
+ UINTN Bit;
+
+ if (Source > MAX_VECTOR) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ Bank = Source / 32;
+ Bit = 1UL << (Source % 32);
+
+ MmioWrite32(INTCPS_MIR_SET(Bank), Bit);
+
+ return EFI_SUCCESS;
+}
+
+
+
+/**
+ Return current state of interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.
+
+ @retval EFI_SUCCESS InterruptState is valid
+ @retval EFI_DEVICE_ERROR InterruptState is not valid
+
+**/
+EFI_STATUS
+EFIAPI
+GetInterruptSourceState (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
+ )
+{
+ UINTN Bank;
+ UINTN Bit;
+
+ if (InterruptState == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Source > MAX_VECTOR) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ Bank = Source / 32;
+ Bit = 1UL << (Source % 32);
+
+ if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
+ *InterruptState = FALSE;
+ } else {
+ *InterruptState = TRUE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+
+/**
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor.This parameter is processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+ @return None
+
+**/
+VOID
+EFIAPI
+IrqInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ UINT32 Vector;
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;
+
+ Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
+
+ InterruptHandler = gRegisteredInterruptHandlers[Vector];
+ if (InterruptHandler != NULL) {
+ // Call the registered interrupt handler.
+ InterruptHandler(Vector, SystemContext);
+ }
+
+ MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+}
+
+//
+// Making this global saves a few bytes in image size
+//
+EFI_HANDLE gHardwareInterruptHandle = NULL;
+
+//
+// The protocol instance produced by this driver
+//
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
+ RegisterInterruptSource,
+ EnableInterruptSource,
+ DisableInterruptSource,
+ GetInterruptSourceState
+};
+
+//
+// Notification routines
+//
+VOID
+CpuProtocolInstalledNotification (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+
+ //
+ // Get the cpu protocol that this driver requires.
+ //
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Unregister the default exception handler.
+ //
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Register to receive interrupts
+ //
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
+ ASSERT_EFI_ERROR(Status);
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+InterruptDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ // Make sure the Interrupt Controller Protocol is not already installed in the system.
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
+
+ // Make sure all interrupts are disabled by default.
+ MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
+ MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
+ MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
+ MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
+
+ Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
+ &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
+ NULL);
+ ASSERT_EFI_ERROR(Status);
+
+ // Set up to be notified when the Cpu protocol is installed.
+ Status = gBS->CreateEvent(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = gBS->RegisterProtocolNotify(&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);
+ ASSERT_EFI_ERROR(Status);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR(Status);
+
+ return Status;
+}
+
diff --git a/BeagleBoardPkg/InterruptDxe/InterruptDxe.inf b/BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
new file mode 100644
index 0000000000..92b8f780bf
--- /dev/null
+++ b/BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
@@ -0,0 +1,56 @@
+#%HEADER%
+#/** @file
+#
+# Interrupt DXE driver
+#
+# Copyright (c) 2009, Apple, Inc
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardInterruptDxe
+ FILE_GUID = 23eed05d-1b93-4a1a-8e1b-931d69e37952
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InterruptDxeInitialize
+
+
+[Sources.common]
+ HardwareInterrupt.c
+
+
+[Packages]
+ BeagleBoardPkg/BeagleBoardPkg.dec
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ DebugLib
+ PrintLib
+ UefiDriverEntryPoint
+ IoLib
+
+[Guids]
+
+
+[Protocols]
+ gHardwareInterruptProtocolGuid
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd.common]
+ gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress
+
+[depex]
+ TRUE
diff --git a/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.c b/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.c
new file mode 100644
index 0000000000..a03ef575fb
--- /dev/null
+++ b/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.c
@@ -0,0 +1,110 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+VOID
+ResetSystem (
+ IN EFI_RESET_TYPE ResetType
+ )
+{
+ switch (ResetType) {
+ case EfiResetWarm:
+ //Perform warm reset of the system.
+ GoLittleEndian(PcdGet32(PcdFlashFvMainBase));
+ break;
+ case EfiResetCold:
+ case EfiResetShutdown:
+ default:
+ //Perform cold reset of the system.
+ MmioOr32(PRM_RSTCTRL, RST_DPLL3);
+ while ((MmioRead32(PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
+ break;
+ }
+
+ //Should never come here.
+ ASSERT(FALSE);
+}
+
+VOID
+ShutdownEfi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN MemoryMapSize;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ UINTN MapKey;
+ UINTN DescriptorSize;
+ UINTN DescriptorVersion;
+ UINTN Pages;
+
+ MemoryMap = NULL;
+ MemoryMapSize = 0;
+ do {
+ Status = gBS->GetMemoryMap (
+ &MemoryMapSize,
+ MemoryMap,
+ &MapKey,
+ &DescriptorSize,
+ &DescriptorVersion
+ );
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+
+ Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
+ MemoryMap = AllocatePages (Pages);
+
+ //
+ // Get System MemoryMap
+ //
+ Status = gBS->GetMemoryMap (
+ &MemoryMapSize,
+ MemoryMap,
+ &MapKey,
+ &DescriptorSize,
+ &DescriptorVersion
+ );
+ // Don't do anything between the GetMemoryMap() and ExitBootServices()
+ if (!EFI_ERROR (Status)) {
+ Status = gBS->ExitBootServices (gImageHandle, MapKey);
+ if (EFI_ERROR (Status)) {
+ FreePages (MemoryMap, Pages);
+ MemoryMap = NULL;
+ MemoryMapSize = 0;
+ }
+ }
+ }
+ } while (EFI_ERROR (Status));
+
+ //Clean and invalidate caches.
+ WriteBackInvalidateDataCache();
+ InvalidateInstructionCache();
+
+ //Turning off Caches and MMU
+ ArmDisableDataCache();
+ ArmDisableInstructionCache();
+ ArmDisableMmu();
+}
+
diff --git a/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf b/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf
new file mode 100644
index 0000000000..2c23ad00e7
--- /dev/null
+++ b/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf
@@ -0,0 +1,45 @@
+#%HEADER%
+#/** @file
+# Support for Airport libraries.
+#
+# Copyright (c) 2009, Apple Inc.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardSystemLib
+ FILE_GUID = b15a2640-fef2-447c-98e1-9ce22cfa529c
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BeagleBoardSystemLib
+
+[Sources.ARM]
+ BeagleBoardSystemLib.c
+ GoLittleEndian.asm | RVCT
+ GoLittleEndian.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ CacheMaintenanceLib
+ MemoryAllocationLib
+ UefiRuntimeServicesTableLib
+ TimerLib
+ UefiLib
+
+[Pcd]
+ gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
diff --git a/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.S b/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.S
new file mode 100644
index 0000000000..a37ae7c883
--- /dev/null
+++ b/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.S
@@ -0,0 +1,27 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+.globl ASM_PFX(GoLittleEndian)
+
+// r0 is target address
+ASM_PFX(GoLittleEndian):
+
+ // Switch to SVC Mode
+ mov r2,#0xD3 // SVC mode
+ msr CPSR_c,r2 // Switch modes
+
+ bx r0
+
diff --git a/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.asm b/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.asm
new file mode 100755
index 0000000000..8daced6b8f
--- /dev/null
+++ b/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.asm
@@ -0,0 +1,27 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+ EXPORT GoLittleEndian
+ PRESERVE8
+ AREA Ebl, CODE, READONLY
+
+// r0 is target address
+GoLittleEndian
+ // Switch to SVC Mode
+ mov r2,#0xD3 // SVC mode
+ msr CPSR_c,r2 // Switch modes
+
+ bx r0
+
+ END
diff --git a/BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf b/BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
new file mode 100644
index 0000000000..5b59014585
--- /dev/null
+++ b/BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
@@ -0,0 +1,46 @@
+#%HEADER%
+#/** @file
+# Timer library implementation
+#
+# A non-functional instance of the Timer Library that can be used as a template
+# for the implementation of a functional timer library instance. This library instance can
+# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer
+# services as well as EBC modules that require timer services
+# Copyright (c) 2007, Intel Corporation.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardTimerLib
+ FILE_GUID = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+
+[Sources.common]
+ TimerLib.c
+
+[Packages]
+ BeagleBoardPkg/BeagleBoardPkg.dec
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ OmapLib
+ IoLib
+
+[Pcd]
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFreqencyInHz
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
+ gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer
+
diff --git a/BeagleBoardPkg/Library/BeagleBoardTimerLib/TimerLib.c b/BeagleBoardPkg/Library/BeagleBoardTimerLib/TimerLib.c
new file mode 100755
index 0000000000..1b9a5bac4f
--- /dev/null
+++ b/BeagleBoardPkg/Library/BeagleBoardTimerLib/TimerLib.c
@@ -0,0 +1,102 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ UINT64 NanoSeconds;
+
+ NanoSeconds = MultU64x32(MicroSeconds, 1000);
+
+ while (NanoSeconds > (UINTN)-1) {
+ NanoSecondDelay((UINTN)-1);
+ NanoSeconds -= (UINTN)-1;
+ }
+
+ NanoSecondDelay(NanoSeconds);
+
+ return MicroSeconds;
+}
+
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ UINT32 Delay;
+ UINT32 StartTime;
+ UINT32 CurrentTime;
+ UINT32 ElapsedTime;
+ UINT32 TimerCountRegister;
+
+ Delay = (NanoSeconds / PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds)) + 1;
+
+ TimerCountRegister = TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR;
+
+ StartTime = MmioRead32(TimerCountRegister);
+
+ do
+ {
+ CurrentTime = MmioRead32(TimerCountRegister);
+ ElapsedTime = CurrentTime - StartTime;
+ } while (ElapsedTime < Delay);
+
+ NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds);
+
+ return NanoSeconds;
+}
+
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR);
+}
+
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ // Timer starts with the reload value
+ *StartValue = (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TLDR);
+ }
+
+ if (EndValue != NULL) {
+ // Timer counts up to 0xFFFFFFFF
+ *EndValue = 0xFFFFFFFF;
+ }
+
+ return PcdGet64(PcdEmbeddedPerformanceCounterFreqencyInHz);
+}
diff --git a/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.c b/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.c
new file mode 100644
index 0000000000..93164d68df
--- /dev/null
+++ b/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.c
@@ -0,0 +1,42 @@
+/** @file
+ Add custom commands for BeagleBoard development.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] =
+{
+};
+
+
+VOID
+EblInitializeExternalCmd (
+ VOID
+ )
+{
+ EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE));
+ return;
+}
diff --git a/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf b/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf
new file mode 100644
index 0000000000..aa8482b79d
--- /dev/null
+++ b/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf
@@ -0,0 +1,49 @@
+#%HEADER%
+#/** @file
+# Component description file for the entry point to a EFIDXE Drivers
+#
+# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification
+# Copyright (c) 2007 - 2007, Intel Corporation
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardEblCmdLib
+ FILE_GUID = ea62bdc3-1063-425f-8851-98cb47f213a8
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources.common]
+ EblCmdLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[Protocols]
+
+[Guids]
+
+[Pcd]
diff --git a/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.c b/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.c
new file mode 100644
index 0000000000..9d5f429e2d
--- /dev/null
+++ b/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.c
@@ -0,0 +1,103 @@
+/** @file
+ Basic serial IO abstaction for GDB
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+RETURN_STATUS
+EFIAPI
+GdbSerialLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+RETURN_STATUS
+EFIAPI
+GdbSerialInit (
+ IN UINT64 BaudRate,
+ IN UINT8 Parity,
+ IN UINT8 DataBits,
+ IN UINT8 StopBits
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+BOOLEAN
+EFIAPI
+GdbIsCharAvailable (
+ VOID
+ )
+{
+ UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
+
+ if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+CHAR8
+EFIAPI
+GdbGetChar (
+ VOID
+ )
+{
+ UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
+ UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG;
+ CHAR8 Char;
+
+ while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
+ Char = MmioRead8(RBR);
+
+ return Char;
+}
+
+VOID
+EFIAPI
+GdbPutChar (
+ IN CHAR8 Char
+ )
+{
+ UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
+ UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG;
+
+ while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
+ MmioWrite8(THR, Char);
+}
+
+VOID
+GdbPutString (
+ IN CHAR8 *String
+ )
+{
+ while (*String != '\0') {
+ GdbPutChar (*String);
+ String++;
+ }
+}
+
+
+
+
diff --git a/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf b/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
new file mode 100644
index 0000000000..c8e6859023
--- /dev/null
+++ b/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
@@ -0,0 +1,29 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = GdbSerialLib
+ FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GdbSerialLib
+
+ CONSTRUCTOR = GdbSerialLibConstructor
+
+
+[Sources.common]
+ GdbSerialLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ OmapLib
+
+[FixedPcd]
+ gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart
+
diff --git a/BeagleBoardPkg/Library/OmapLib/OmapLib.c b/BeagleBoardPkg/Library/OmapLib/OmapLib.c
new file mode 100644
index 0000000000..7464b2e74a
--- /dev/null
+++ b/BeagleBoardPkg/Library/OmapLib/OmapLib.c
@@ -0,0 +1,83 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+
+UINT32
+GpioBase (
+ IN UINTN Port
+ )
+{
+ switch (Port) {
+ case 1: return GPIO1_BASE;
+ case 2: return GPIO2_BASE;
+ case 3: return GPIO3_BASE;
+ case 4: return GPIO4_BASE;
+ case 5: return GPIO5_BASE;
+ case 6: return GPIO6_BASE;
+ default: ASSERT(FALSE); return 0;
+ }
+}
+
+UINT32
+TimerBase (
+ IN UINTN Timer
+ )
+{
+ switch (Timer) {
+ case 1: return GPTIMER1_BASE;
+ case 2: return GPTIMER2_BASE;
+ case 3: return GPTIMER3_BASE;
+ case 4: return GPTIMER4_BASE;
+ case 5: return GPTIMER5_BASE;
+ case 6: return GPTIMER6_BASE;
+ case 7: return GPTIMER7_BASE;
+ case 8: return GPTIMER8_BASE;
+ case 9: return GPTIMER9_BASE;
+ case 10: return GPTIMER10_BASE;
+ case 11: return GPTIMER11_BASE;
+ case 12: return GPTIMER12_BASE;
+ default: return 0;
+ }
+}
+
+UINTN
+InterruptVectorForTimer (
+ IN UINTN Timer
+ )
+{
+ if ((Timer < 1) || (Timer > 12)) {
+ ASSERT(FALSE);
+ return 0xFFFFFFFF;
+ }
+
+ return 36 + Timer;
+}
+
+UINT32
+UartBase (
+ IN UINTN Uart
+ )
+{
+ switch (Uart) {
+ case 1: return UART1_BASE;
+ case 2: return UART2_BASE;
+ case 3: return UART3_BASE;
+ default: ASSERT(FALSE); return 0;
+ }
+}
+
diff --git a/BeagleBoardPkg/Library/OmapLib/OmapLib.inf b/BeagleBoardPkg/Library/OmapLib/OmapLib.inf
new file mode 100644
index 0000000000..8fe030cff1
--- /dev/null
+++ b/BeagleBoardPkg/Library/OmapLib/OmapLib.inf
@@ -0,0 +1,25 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = OmapLib
+ FILE_GUID = d035f5c2-1b92-4746-9f6c-5ff6202970df
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = OmapLib
+
+[Sources.common]
+ OmapLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Protocols]
+
+[Guids]
+
+[Pcd]
diff --git a/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c b/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c
new file mode 100644
index 0000000000..9c427e5c65
--- /dev/null
+++ b/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -0,0 +1,84 @@
+/** @file
+ Template library implementation to support ResetSystem Runtime call.
+
+ Fill in the templates with what ever makes you system reset.
+
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/**
+ Resets the entire platform.
+
+ @param ResetType The type of reset to perform.
+ @param ResetStatus The status code for the reset.
+ @param DataSize The size, in bytes, of WatchdogData.
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
+ EfiResetShutdown the data buffer starts with a Null-terminated
+ Unicode string, optionally followed by additional binary data.
+
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
+ )
+{
+ if (ResetData != NULL) {
+ DEBUG((EFI_D_ERROR, "%s", ResetData));
+ }
+
+ //Shutdown EFI services.
+ ShutdownEfi();
+
+ //Reset the sytem.
+ ResetSystem(ResetType);
+
+ // If the reset didn't work, return an error.
+ return EFI_DEVICE_ERROR;
+}
+
+
+
+/**
+ Initialize any infrastructure required for LibResetSystem () to function.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return EFI_SUCCESS;
+}
+
diff --git a/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf b/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644
index 0000000000..e62d94b5b4
--- /dev/null
+++ b/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -0,0 +1,41 @@
+#%HEADER%
+#/** @file
+# Reset System lib to make it easy to port new platforms
+#
+# Copyright (c) 2008, Apple Inc.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardResetSystemLib
+ FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiResetSystemLib
+
+
+[Sources.common]
+ ResetSystemLib.c
+
+[Packages]
+ BeagleBoardPkg/BeagleBoardPkg.dec
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[Pcd.common]
+ gArmTokenSpaceGuid.PcdCpuResetAddress
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
+
+[LibraryClasses]
+ DebugLib
+ BeagleBoardSystemLib
diff --git a/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.c b/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.c
new file mode 100644
index 0000000000..0509deb8ab
--- /dev/null
+++ b/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.c
@@ -0,0 +1,124 @@
+/** @file
+ Serial I/O Port library functions with no library constructor/destructor
+
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+
+ Programmed hardware of Serial port.
+
+ @return Always return EFI_UNSUPPORTED.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ // assume assembly code at reset vector has setup UART
+ return RETURN_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be writed.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes writed to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
+ UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG;
+ UINTN Count;
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
+ MmioWrite8(THR, *Buffer);
+ }
+
+ return NumberOfBytes;
+}
+
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ @param Buffer Point of data buffer which need to be writed.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Aactual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
+ UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG;
+ UINTN Count;
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
+ *Buffer = MmioRead8(RBR);
+ }
+
+ return NumberOfBytes;
+}
+
+
+/**
+ Check to see if any data is avaiable to be read from the debug device.
+
+ @retval EFI_SUCCESS At least one byte of data is avaiable to be read
+ @retval EFI_NOT_READY No data is avaiable to be read
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
+
+ if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
diff --git a/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf b/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
new file mode 100644
index 0000000000..b81bbca657
--- /dev/null
+++ b/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
@@ -0,0 +1,44 @@
+#%HEADER%
+#/** @file
+# EDK Serial port lib
+#
+# Copyright (c) 2009, Apple Inc.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardSerialPortLib
+ FILE_GUID = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources.common]
+ SerialPortLib.c
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ OmapLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[FixedPcd]
+ gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart
+
diff --git a/BeagleBoardPkg/MMCHSDxe/MMCHS.c b/BeagleBoardPkg/MMCHSDxe/MMCHS.c
new file mode 100644
index 0000000000..77c5fbdbfa
--- /dev/null
+++ b/BeagleBoardPkg/MMCHSDxe/MMCHS.c
@@ -0,0 +1,1018 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include "MMCHS.h"
+
+EFI_BLOCK_IO_MEDIA MMCHSMedia = {
+ SIGNATURE_32('s','d','i','o'), // MediaId
+ FALSE, // RemovableMedia
+ TRUE, // MediaPresent
+ TRUE, // LogicalPartition
+ FALSE, // ReadOnly
+ FALSE, // WriteCaching
+ 512, // BlockSize
+ 4, // IoAlign
+ 0, // Pad
+ 0 // LastBlock
+};
+
+typedef struct {
+ VENDOR_DEVICE_PATH Mmc;
+ EFI_DEVICE_PATH End;
+} MMCHS_DEVICE_PATH;
+
+MMCHS_DEVICE_PATH gMmcHsDevicePath =
+{
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ (UINT8)(sizeof(VENDOR_DEVICE_PATH)),
+ (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8),
+ 0xb615f1f5, 0x5088, 0x43cd, 0x80, 0x9c, 0xa1, 0x6e, 0x52, 0x48, 0x7d, 0x00
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ sizeof (EFI_DEVICE_PATH_PROTOCOL),
+ 0
+ }
+};
+
+CARD_INFO *gCardInfo;
+EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
+
+//
+// Internal Functions
+//
+
+STATIC
+VOID
+ParseCardCIDData (
+ UINT32 Response0,
+ UINT32 Response1,
+ UINT32 Response2,
+ UINT32 Response3
+ )
+{
+ gCardInfo->CIDData.MDT = ((Response0 >> 8) & 0xFFF);
+ gCardInfo->CIDData.PSN = (((Response0 >> 24) & 0xFF) | ((Response1 & 0xFFFFFF) << 8));
+ gCardInfo->CIDData.PRV = ((Response1 >> 24) & 0xFF);
+ gCardInfo->CIDData.PNM[4] = ((Response2) & 0xFF);
+ gCardInfo->CIDData.PNM[3] = ((Response2 >> 8) & 0xFF);
+ gCardInfo->CIDData.PNM[2] = ((Response2 >> 16) & 0xFF);
+ gCardInfo->CIDData.PNM[1] = ((Response2 >> 24) & 0xFF);
+ gCardInfo->CIDData.PNM[0] = ((Response3) & 0xFF);
+ gCardInfo->CIDData.OID = ((Response3 >> 8) & 0xFFFF);
+ gCardInfo->CIDData.MID = ((Response3 >> 24) & 0xFF);
+}
+
+STATIC
+VOID
+UpdateMMCHSClkFrequency (
+ UINTN NewCLKD
+ )
+{
+ //Set Clock enable to 0x0 to not provide the clock to the card
+ MmioAnd32(MMCHS_SYSCTL, ~CEN);
+
+ //Set new clock frequency.
+ MmioAndThenOr32(MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
+
+ //Poll till Internal Clock Stable
+ while ((MmioRead32(MMCHS_SYSCTL) & ICS_MASK) != ICS);
+
+ //Set Clock enable to 0x1 to provide the clock to the card
+ MmioOr32(MMCHS_SYSCTL, CEN);
+}
+
+STATIC
+EFI_STATUS
+SendCmd (
+ UINTN Cmd,
+ UINTN CmdInterruptEnableVal,
+ UINTN CmdArgument
+ )
+{
+ UINTN MmcStatus;
+ UINTN RetryCount = 0;
+
+ //Check if command line is in use or not. Poll till command line is available.
+ while ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
+
+ //Provide the block size.
+ MmioWrite32(MMCHS_BLK, BLEN_512BYTES);
+
+ //Setting Data timeout counter value to max value.
+ MmioAndThenOr32(MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
+
+ //Clear Status register.
+ MmioWrite32(MMCHS_STAT, 0xFFFFFFFF);
+
+ //Set command argument register
+ MmioWrite32(MMCHS_ARG, CmdArgument);
+
+ //Enable interrupt enable events to occur
+ MmioWrite32(MMCHS_IE, CmdInterruptEnableVal);
+
+ //Send a command
+ MmioWrite32(MMCHS_CMD, Cmd);
+
+ //Check for the command status.
+ while (RetryCount < MAX_RETRY_COUNT) {
+ do {
+ MmcStatus = MmioRead32(MMCHS_STAT);
+ } while (MmcStatus == 0);
+
+ //Read status of command response
+ if ((MmcStatus & ERRI) != 0) {
+
+ //Perform soft-reset for mmci_cmd line.
+ MmioOr32(MMCHS_SYSCTL, SRC);
+ while ((MmioRead32(MMCHS_SYSCTL) & SRC));
+
+ DEBUG ((EFI_D_INFO, "MmcStatus: %x\n", MmcStatus));
+ return EFI_DEVICE_ERROR;
+ }
+
+ //Check if command is completed.
+ if ((MmcStatus & CC) == CC) {
+ MmioWrite32(MMCHS_STAT, CC);
+ break;
+ }
+
+ RetryCount++;
+ }
+
+ if (RetryCount == MAX_RETRY_COUNT) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+VOID
+GetBlockInformation (
+ UINTN *BlockSize,
+ UINTN *NumBlocks
+ )
+{
+ CSD_SDV2 *CsdSDV2Data;
+ UINTN CardSize;
+
+ if (gCardInfo->CardType == SD_CARD_2_HIGH) {
+ CsdSDV2Data = (CSD_SDV2 *)&gCardInfo->CSDData;
+
+ //Populate BlockSize.
+ *BlockSize = (0x1UL << CsdSDV2Data->READ_BL_LEN);
+
+ //Calculate Total number of blocks.
+ CardSize = CsdSDV2Data->C_SIZELow16 | (CsdSDV2Data->C_SIZEHigh6 << 2);
+ *NumBlocks = ((CardSize + 1) * 1024);
+ } else {
+ //Populate BlockSize.
+ *BlockSize = (0x1UL << gCardInfo->CSDData.READ_BL_LEN);
+
+ //Calculate Total number of blocks.
+ CardSize = gCardInfo->CSDData.C_SIZELow2 | (gCardInfo->CSDData.C_SIZEHigh10 << 2);
+ *NumBlocks = (CardSize + 1) * (1 << (gCardInfo->CSDData.C_SIZE_MULT + 2));
+ }
+
+ //For >=2G card, BlockSize may be 1K, but the transfer size is 512 bytes.
+ if (*BlockSize > 512) {
+ *NumBlocks = MultU64x32(*NumBlocks, *BlockSize/2);
+ *BlockSize = 512;
+ }
+
+ DEBUG ((EFI_D_INFO, "Card type: %x, BlockSize: %x, NumBlocks: %x\n", gCardInfo->CardType, *BlockSize, *NumBlocks));
+}
+
+STATIC
+VOID
+CalculateCardCLKD (
+ UINTN *ClockFrequencySelect
+ )
+{
+ UINT8 MaxDataTransferRate;
+ UINTN TransferRateValue = 0;
+ UINTN TimeValue = 0 ;
+ UINTN Frequency = 0;
+
+ MaxDataTransferRate = gCardInfo->CSDData.TRAN_SPEED;
+
+ //Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED)
+ switch (MaxDataTransferRate & 0x7) {
+ case 0:
+ TransferRateValue = 100 * 1000;
+ break;
+
+ case 1:
+ TransferRateValue = 1 * 1000 * 1000;
+ break;
+
+ case 2:
+ TransferRateValue = 10 * 1000 * 1000;
+ break;
+
+ case 3:
+ TransferRateValue = 100 * 1000 * 1000;
+ break;
+
+ default:
+ DEBUG((EFI_D_ERROR, "Invalid parameter.\n"));
+ ASSERT(FALSE);
+ }
+
+ //Calculate Time value (Bits 6:3 of TRAN_SPEED)
+ switch ((MaxDataTransferRate >> 3) & 0xF) {
+ case 1:
+ TimeValue = 10;
+ break;
+
+ case 2:
+ TimeValue = 12;
+ break;
+
+ case 3:
+ TimeValue = 13;
+ break;
+
+ case 4:
+ TimeValue = 15;
+ break;
+
+ case 5:
+ TimeValue = 20;
+ break;
+
+ case 6:
+ TimeValue = 25;
+ break;
+
+ case 7:
+ TimeValue = 30;
+ break;
+
+ case 8:
+ TimeValue = 35;
+ break;
+
+ case 9:
+ TimeValue = 40;
+ break;
+
+ case 10:
+ TimeValue = 45;
+ break;
+
+ case 11:
+ TimeValue = 50;
+ break;
+
+ case 12:
+ TimeValue = 55;
+ break;
+
+ case 13:
+ TimeValue = 60;
+ break;
+
+ case 14:
+ TimeValue = 70;
+ break;
+
+ case 15:
+ TimeValue = 80;
+ break;
+
+ default:
+ DEBUG((EFI_D_ERROR, "Invalid parameter.\n"));
+ ASSERT(FALSE);
+ }
+
+ Frequency = TransferRateValue * TimeValue/10;
+
+ //Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
+ *ClockFrequencySelect = ((MMC_REFERENCE_CLK/Frequency) + 1);
+
+ DEBUG ((EFI_D_INFO, "MaxDataTransferRate: 0x%x, Frequency: %d KHz, ClockFrequencySelect: %x\n", MaxDataTransferRate, Frequency/1000, *ClockFrequencySelect));
+}
+
+STATIC
+VOID
+GetCardConfigurationData (
+ VOID
+ )
+{
+ UINTN BlockSize;
+ UINTN NumBlocks;
+ UINTN ClockFrequencySelect;
+
+ //Calculate BlockSize and Total number of blocks in the detected card.
+ GetBlockInformation(&BlockSize, &NumBlocks);
+ gCardInfo->BlockSize = BlockSize;
+ gCardInfo->NumBlocks = NumBlocks;
+
+ //Calculate Card clock divider value.
+ CalculateCardCLKD(&ClockFrequencySelect);
+ gCardInfo->ClockFrequencySelect = ClockFrequencySelect;
+}
+
+STATIC
+EFI_STATUS
+InitializeMMCHS (
+ VOID
+ )
+{
+ UINT8 Data = 0;
+ EFI_STATUS Status;
+
+ //Select Device group to belong to P1 device group in Power IC.
+ Data = DEV_GRP_P1;
+ Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEV_GRP), 1, &Data);
+ ASSERT_EFI_ERROR(Status);
+
+ //Configure voltage regulator for MMC1 in Power IC to output 3.0 voltage.
+ Data = VSEL_3_00V;
+ Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VMMC1_DEDICATED_REG), 1, &Data);
+ ASSERT_EFI_ERROR(Status);
+
+ //After ramping up voltage, set VDDS stable bit to indicate that voltage level is stable.
+ MmioOr32(CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
+
+ //Software reset of the MMCHS host controller.
+ MmioWrite32(MMCHS_SYSCONFIG, SOFTRESET);
+ gBS->Stall(1000);
+ while ((MmioRead32(MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
+
+ //Soft reset for all.
+ MmioWrite32(MMCHS_SYSCTL, SRA);
+ gBS->Stall(1000);
+ while ((MmioRead32(MMCHS_SYSCTL) & SRA) != 0x0);
+
+ //Voltage capabilities initialization. Activate VS18 and VS30.
+ MmioOr32(MMCHS_CAPA, (VS30 | VS18));
+
+ //Wakeup configuration
+ MmioOr32(MMCHS_SYSCONFIG, ENAWAKEUP);
+ MmioOr32(MMCHS_HCTL, IWE);
+
+ //MMCHS Controller default initialization
+ MmioOr32(MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
+
+ MmioWrite32(MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
+
+ //Enable internal clock
+ MmioOr32(MMCHS_SYSCTL, ICE);
+
+ //Set the clock frequency to 80KHz.
+ UpdateMMCHSClkFrequency(CLKD_80KHZ);
+
+ //Enable SD bus power.
+ MmioOr32(MMCHS_HCTL, (SDBP_ON));
+
+ //Poll till SD bus power bit is set.
+ while ((MmioRead32(MMCHS_HCTL) & SDBP_MASK) != SDBP_ON);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+PerformCardIdenfication (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN CmdArgument = 0;
+ UINTN Response = 0;
+ UINTN RetryCount = 0;
+ BOOLEAN SDCmd8Supported = FALSE;
+
+ //Enable interrupts.
+ MmioWrite32(MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
+ CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
+
+ //Controller INIT procedure start.
+ MmioOr32(MMCHS_CON, INIT);
+ MmioWrite32(MMCHS_CMD, 0x00000000);
+ while (!(MmioRead32(MMCHS_STAT) & CC));
+
+ //Wait for 1 ms
+ gBS->Stall(1000);
+
+ //Set CC bit to 0x1 to clear the flag
+ MmioOr32(MMCHS_STAT, CC);
+
+ //Retry INIT procedure.
+ MmioWrite32(MMCHS_CMD, 0x00000000);
+ while (!(MmioRead32(MMCHS_STAT) & CC));
+
+ //End initialization sequence
+ MmioAnd32(MMCHS_CON, ~INIT);
+
+ MmioOr32(MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));
+
+ //Change clock frequency to 400KHz to fit protocol
+ UpdateMMCHSClkFrequency(CLKD_400KHZ);
+
+ MmioOr32(MMCHS_CON, OD);
+
+ //Send CMD0 command.
+ Status = SendCmd(CMD0, CMD0_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Cmd0 fails.\n"));
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "CMD0 response: %x\n", MmioRead32(MMCHS_RSP10)));
+
+ //Send CMD5 command.
+ Status = SendCmd(CMD5, CMD5_INT_EN, CmdArgument);
+ if (Status == EFI_SUCCESS) {
+ DEBUG ((EFI_D_ERROR, "CMD5 Success. SDIO card. Follow SDIO card specification.\n"));
+ DEBUG ((EFI_D_INFO, "CMD5 response: %x\n", MmioRead32(MMCHS_RSP10)));
+ //NOTE: Returning unsupported error for now. Need to implement SDIO specification.
+ return EFI_UNSUPPORTED;
+ } else {
+ DEBUG ((EFI_D_INFO, "CMD5 fails. Not an SDIO card.\n"));
+ }
+
+ MmioOr32(MMCHS_SYSCTL, SRC);
+ gBS->Stall(1000);
+ while ((MmioRead32(MMCHS_SYSCTL) & SRC));
+
+ //Send CMD8 command. (New v2.00 command for Voltage check)
+ //Only 2.7V - 3.6V is supported for SD2.0, only SD 2.0 card can pass.
+ //MMC & SD1.1 card will fail this command.
+ CmdArgument = CMD8_ARG;
+ Status = SendCmd(CMD8, CMD8_INT_EN, CmdArgument);
+ if (Status == EFI_SUCCESS) {
+ Response = MmioRead32(MMCHS_RSP10);
+ DEBUG ((EFI_D_INFO, "CMD8 success. CMD8 response: %x\n", Response));
+ if (Response != CmdArgument) {
+ return EFI_DEVICE_ERROR;
+ }
+ DEBUG ((EFI_D_INFO, "Card is SD2.0\n"));
+ SDCmd8Supported = TRUE; //Supports high capacity.
+ } else {
+ DEBUG ((EFI_D_INFO, "CMD8 fails. Not an SD2.0 card.\n"));
+ }
+
+ MmioOr32(MMCHS_SYSCTL, SRC);
+ gBS->Stall(1000);
+ while ((MmioRead32(MMCHS_SYSCTL) & SRC));
+
+ //Poll till card is busy
+ while (RetryCount < MAX_RETRY_COUNT) {
+ //Send CMD55 command.
+ CmdArgument = 0;
+ Status = SendCmd(CMD55, CMD55_INT_EN, CmdArgument);
+ if (Status == EFI_SUCCESS) {
+ DEBUG ((EFI_D_INFO, "CMD55 success. CMD55 response: %x\n", MmioRead32(MMCHS_RSP10)));
+ gCardInfo->CardType = SD_CARD;
+ } else {
+ DEBUG ((EFI_D_INFO, "CMD55 fails.\n"));
+ gCardInfo->CardType = MMC_CARD;
+ }
+
+ //Send appropriate command for the card type which got detected.
+ if (gCardInfo->CardType == SD_CARD) {
+ CmdArgument = ((UINTN *) &(gCardInfo->OCRData))[0];
+
+ //Set HCS bit.
+ if (SDCmd8Supported) {
+ CmdArgument |= HCS;
+ }
+
+ Status = SendCmd(ACMD41, ACMD41_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_INFO, "ACMD41 fails.\n"));
+ return Status;
+ }
+ ((UINT32 *) &(gCardInfo->OCRData))[0] = MmioRead32(MMCHS_RSP10);
+ DEBUG ((EFI_D_INFO, "SD card detected. ACMD41 OCR: %x\n", ((UINT32 *) &(gCardInfo->OCRData))[0]));
+ } else if (gCardInfo->CardType == MMC_CARD) {
+ CmdArgument = 0;
+ Status = SendCmd(CMD1, CMD1_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_INFO, "CMD1 fails.\n"));
+ return Status;
+ }
+ Response = MmioRead32(MMCHS_RSP10);
+ DEBUG ((EFI_D_INFO, "MMC card detected.. CMD1 response: %x\n", Response));
+
+ //NOTE: For now, I am skipping this since I only have an SD card.
+ //Compare card OCR and host OCR (Section 22.6.1.3.2.4)
+ return EFI_UNSUPPORTED; //For now, MMC is not supported.
+ }
+
+ //Poll the card until it is out of its power-up sequence.
+ if (gCardInfo->OCRData.Busy == 1) {
+
+ if (SDCmd8Supported) {
+ gCardInfo->CardType = SD_CARD_2;
+ }
+
+ //Card is ready. Check CCS (Card capacity status) bit (bit#30).
+ //SD 2.0 standard card will response with CCS 0, SD high capacity card will respond with CCS 1.
+ if (gCardInfo->OCRData.AccessMode & BIT1) {
+ gCardInfo->CardType = SD_CARD_2_HIGH;
+ DEBUG ((EFI_D_INFO, "High capacity card.\n"));
+ } else {
+ DEBUG ((EFI_D_INFO, "Standard capacity card.\n"));
+ }
+
+ break;
+ }
+
+ gBS->Stall(1000);
+ RetryCount++;
+ }
+
+ if (RetryCount == MAX_RETRY_COUNT) {
+ DEBUG ((EFI_D_ERROR, "Timeout error. RetryCount: %d\n", RetryCount));
+ return EFI_TIMEOUT;
+ }
+
+ //Read CID data.
+ CmdArgument = 0;
+ Status = SendCmd(CMD2, CMD2_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "CMD2 fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "CMD2 response: %x %x %x %x\n", MmioRead32(MMCHS_RSP10), MmioRead32(MMCHS_RSP32), MmioRead32(MMCHS_RSP54), MmioRead32(MMCHS_RSP76)));
+
+ //Parse CID register data.
+ ParseCardCIDData(MmioRead32(MMCHS_RSP10), MmioRead32(MMCHS_RSP32), MmioRead32(MMCHS_RSP54), MmioRead32(MMCHS_RSP76));
+
+ //Read RCA
+ CmdArgument = 0;
+ Status = SendCmd(CMD3, CMD3_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "CMD3 fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ //Set RCA for the detected card. RCA is CMD3 response.
+ gCardInfo->RCA = (MmioRead32(MMCHS_RSP10) >> 16);
+ DEBUG ((EFI_D_INFO, "CMD3 response: RCA %x\n", gCardInfo->RCA));
+
+ //MMC Bus setting change after card identification.
+ MmioAnd32(MMCHS_CON, ~OD);
+ MmioOr32(MMCHS_HCTL, SDVS_3_0_V);
+ UpdateMMCHSClkFrequency(CLKD_400KHZ); //Set the clock frequency to 400KHz.
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+GetCardSpecificData (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN CmdArgument;
+
+ //Send CMD9 to retrieve CSD.
+ CmdArgument = gCardInfo->RCA << 16;
+ Status = SendCmd(CMD9, CMD9_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "CMD9 fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ //Populate 128-bit CSD register data.
+ ((UINT32 *)&(gCardInfo->CSDData))[0] = MmioRead32(MMCHS_RSP10);
+ ((UINT32 *)&(gCardInfo->CSDData))[1] = MmioRead32(MMCHS_RSP32);
+ ((UINT32 *)&(gCardInfo->CSDData))[2] = MmioRead32(MMCHS_RSP54);
+ ((UINT32 *)&(gCardInfo->CSDData))[3] = MmioRead32(MMCHS_RSP76);
+
+ DEBUG ((EFI_D_INFO, "CMD9 response: %x %x %x %x\n", MmioRead32(MMCHS_RSP10), MmioRead32(MMCHS_RSP32), MmioRead32(MMCHS_RSP54), MmioRead32(MMCHS_RSP76)));
+
+ //Calculate total number of blocks and max. data transfer rate supported by the detected card.
+ GetCardConfigurationData();
+
+ //Change MMCHS clock frequency to what detected card can support.
+ UpdateMMCHSClkFrequency(gCardInfo->ClockFrequencySelect);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+PerformCardConfiguration (
+ VOID
+ )
+{
+ UINTN CmdArgument = 0;
+ EFI_STATUS Status;
+
+ //Send CMD7
+ CmdArgument = gCardInfo->RCA << 16;
+ Status = SendCmd(CMD7, CMD7_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "CMD7 fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ //Send CMD16 to set the block length
+ CmdArgument = gCardInfo->BlockSize;
+ Status = SendCmd(CMD16, CMD16_INT_EN, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "CMD16 fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+ReadBlockData(
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ OUT VOID *Buffer
+ )
+{
+ UINTN MmcStatus;
+ UINTN *DataBuffer = Buffer;
+ UINTN DataSize = This->Media->BlockSize/4;
+ UINTN Count;
+ UINTN RetryCount = 0;
+
+ //Check controller status to make sure there is no error.
+ while (RetryCount < MAX_RETRY_COUNT) {
+ do {
+ //Read Status.
+ MmcStatus = MmioRead32(MMCHS_STAT);
+ } while(MmcStatus == 0);
+
+ //Check if Buffer read ready (BRR) bit is set?
+ if (MmcStatus & BRR) {
+
+ //Clear BRR bit
+ MmioOr32(MMCHS_STAT, BRR);
+
+ //Read block worth of data.
+ for (Count = 0; Count < DataSize; Count++) {
+ *DataBuffer++ = MmioRead32(MMCHS_DATA);
+ }
+ break;
+ }
+ RetryCount++;
+ }
+
+ if (RetryCount == MAX_RETRY_COUNT) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+WriteBlockData(
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ OUT VOID *Buffer
+ )
+{
+ UINTN MmcStatus;
+ UINTN *DataBuffer = Buffer;
+ UINTN DataSize = This->Media->BlockSize/4;
+ UINTN Count;
+ UINTN RetryCount = 0;
+
+ //Check controller status to make sure there is no error.
+ while (RetryCount < MAX_RETRY_COUNT) {
+ do {
+ //Read Status.
+ MmcStatus = MmioRead32(MMCHS_STAT);
+ } while(MmcStatus == 0);
+
+ //Check if Buffer write ready (BWR) bit is set?
+ if (MmcStatus & BWR) {
+
+ //Clear BWR bit
+ MmioOr32(MMCHS_STAT, BWR);
+
+ //Write block worth of data.
+ for (Count = 0; Count < DataSize; Count++) {
+ MmioWrite32(MMCHS_DATA, *DataBuffer++);
+ }
+
+ break;
+ }
+ RetryCount++;
+ }
+
+ if (RetryCount == MAX_RETRY_COUNT) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+TransferBlockData(
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ OUT VOID *Buffer,
+ IN OPERATION_TYPE OperationType
+ )
+{
+ EFI_STATUS Status;
+ UINTN MmcStatus;
+ UINTN RetryCount = 0;
+
+ //Read or Write data.
+ if (OperationType == READ) {
+ Status = ReadBlockData(This, Buffer);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "ReadBlockData fails.\n"));
+ return Status;
+ }
+ } else if (OperationType == WRITE) {
+ Status = WriteBlockData(This, Buffer);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "WriteBlockData fails.\n"));
+ return Status;
+ }
+ }
+
+ //Check for the Transfer completion.
+ while (RetryCount < MAX_RETRY_COUNT) {
+ //Read Status
+ do {
+ MmcStatus = MmioRead32(MMCHS_STAT);
+ } while (MmcStatus == 0);
+
+ //Check if Transfer complete (TC) bit is set?
+ if (MmcStatus & TC) {
+ break;
+ } else {
+ DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
+ //Check if DEB, DCRC or DTO interrupt occured.
+ if ((MmcStatus & DEB) | (MmcStatus & DCRC) | (MmcStatus & DTO)) {
+ //There was an error during the data transfer.
+
+ //Set SRD bit to 1 and wait until it return to 0x0.
+ MmioOr32(MMCHS_SYSCTL, SRD);
+ while((MmioRead32(MMCHS_SYSCTL) & SRD) != 0x0);
+
+ return EFI_DEVICE_ERROR;
+ }
+ }
+ RetryCount++;
+ }
+
+ if (RetryCount == MAX_RETRY_COUNT) {
+ DEBUG ((EFI_D_ERROR, "TransferBlockData timed out.\n"));
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+SdReadWrite (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINTN Lba,
+ OUT VOID *Buffer,
+ IN UINTN BufferSize,
+ IN OPERATION_TYPE OperationType
+ )
+{
+ EFI_STATUS Status;
+ UINTN RetryCount = 0;
+ UINTN NumBlocks;
+ UINTN Cmd = 0;
+ UINTN CmdInterruptEnable = 0;
+ UINTN CmdArgument = 0;
+
+ //Check if the data lines are not in use.
+ while ((RetryCount++ < MAX_RETRY_COUNT) && ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) != DATI_ALLOWED));
+ if (RetryCount == MAX_RETRY_COUNT) {
+ return EFI_TIMEOUT;
+ }
+
+ //Populate the command information based on the operation type.
+ if (OperationType == READ) {
+ Cmd = CMD17; //Single block read
+ CmdInterruptEnable = CMD17_INT_EN;
+ } else if (OperationType == WRITE) {
+ Cmd = CMD24; //Single block write
+ CmdInterruptEnable = CMD24_INT_EN;
+ }
+
+ //Calculate total number of blocks its going to read.
+ NumBlocks = (BufferSize + (This->Media->BlockSize - 1))/This->Media->BlockSize;
+
+ //Set command argument based on the card access mode (Byte mode or Block mode)
+ if (gCardInfo->OCRData.AccessMode & BIT1) {
+ CmdArgument = (UINTN)Lba;
+ } else {
+ CmdArgument = (UINTN)Lba * This->Media->BlockSize;
+ }
+
+ while(NumBlocks) {
+ //Send Command.
+ Status = SendCmd(Cmd, CmdInterruptEnable, CmdArgument);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "CMD fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ //Transfer a block worth of data.
+ Status = TransferBlockData(This, Buffer, OperationType);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "TransferBlockData fails. %x\n", Status));
+ return Status;
+ }
+
+ //Adjust command argument.
+ if (gCardInfo->OCRData.AccessMode & BIT1) {
+ CmdArgument++; //Increase BlockIndex by one.
+ } else {
+ CmdArgument += This->Media->BlockSize; //Increase BlockIndex by BlockSize
+ }
+
+ //Adjust Buffer.
+ Buffer = (UINT8 *)Buffer + This->Media->BlockSize;
+ NumBlocks--;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MMCHSReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+MMCHSReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ if (Buffer == NULL)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Lba > This->Media->LastBlock)
+ {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((BufferSize % This->Media->BlockSize) != 0)
+ {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ //Perform Read operation.
+ Status = SdReadWrite(This, (UINTN)Lba, Buffer, BufferSize, READ);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Read operation fails.\n"));
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MMCHSWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Lba > This->Media->LastBlock) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((BufferSize % This->Media->BlockSize) != 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ if (This->Media->ReadOnly) {
+ return EFI_WRITE_PROTECTED;
+ }
+
+ //Perform write operation.
+ Status = SdReadWrite(This, (UINTN)Lba, Buffer, BufferSize, WRITE);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Write operation fails.\n"));
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MMCHSFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_BLOCK_IO_PROTOCOL BlockIo =
+{
+ EFI_BLOCK_IO_INTERFACE_REVISION, // Revision
+ &MMCHSMedia, // *Media
+ MMCHSReset, // Reset
+ MMCHSReadBlocks, // ReadBlocks
+ MMCHSWriteBlocks, // WriteBlocks
+ MMCHSFlushBlocks // FlushBlocks
+};
+
+EFI_STATUS
+MMCHSInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
+ ASSERT_EFI_ERROR(Status);
+
+ gCardInfo = (CARD_INFO *)AllocateZeroPool(sizeof(CARD_INFO));
+ if (gCardInfo == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //Initialize MMC host controller.
+ Status = InitializeMMCHS();
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Initialize MMC host controller fails. Status: %x\n", Status));
+ return Status;
+ }
+
+ //Card idenfication
+ Status = PerformCardIdenfication();
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "No MMC/SD card detected.\n"));
+ return EFI_SUCCESS; //NOTE: Check if this is correct..
+ }
+
+ //Get CSD (Card specific data) for the detected card.
+ Status = GetCardSpecificData();
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //Configure the card in data transfer mode.
+ Status = PerformCardConfiguration();
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //Patch the Media structure.
+ MMCHSMedia.LastBlock = (gCardInfo->NumBlocks - 1);
+ MMCHSMedia.BlockSize = gCardInfo->BlockSize;
+
+ //Publish BlockIO.
+ Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle,
+ &gEfiBlockIoProtocolGuid, &BlockIo,
+ &gEfiDevicePathProtocolGuid, &gMmcHsDevicePath,
+ NULL);
+ return Status;
+}
diff --git a/BeagleBoardPkg/MMCHSDxe/MMCHS.h b/BeagleBoardPkg/MMCHSDxe/MMCHS.h
new file mode 100755
index 0000000000..9baac74931
--- /dev/null
+++ b/BeagleBoardPkg/MMCHSDxe/MMCHS.h
@@ -0,0 +1,158 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MMCHS_H_
+#define _MMCHS_H_
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define MAX_RETRY_COUNT 100
+
+#define HCS (0x1UL << 30) //Host capacity support/1 = Supporting high capacity
+#define CCS (0x1UL << 30) //Card capacity status/1 = High capacity card
+typedef struct {
+ UINT32 Reserved0: 7; // 0
+ UINT32 V170_V195: 1; // 1.70V - 1.95V
+ UINT32 V200_V260: 7; // 2.00V - 2.60V
+ UINT32 V270_V360: 9; // 2.70V - 3.60V
+ UINT32 RESERVED_1: 5; // Reserved
+ UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
+ UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
+}OCR;
+
+typedef struct {
+ UINT32 NOT_USED; // 1 [0:0]
+ UINT32 CRC; // CRC7 checksum [7:1]
+ UINT32 MDT; // Manufacturing date [19:8]
+ UINT32 RESERVED_1; // Reserved [23:20]
+ UINT32 PSN; // Product serial number [55:24]
+ UINT8 PRV; // Product revision [63:56]
+ UINT8 PNM[5]; // Product name [64:103]
+ UINT16 OID; // OEM/Application ID [119:104]
+ UINT8 MID; // Manufacturer ID [127:120]
+}CID;
+
+typedef struct {
+ UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
+ UINT8 CRC: 7; // CRC [7:1]
+ UINT8 RESERVED_1: 2; // Reserved [9:8]
+ UINT8 FILE_FORMAT: 2; // File format [11:10]
+ UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
+ UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
+ UINT8 COPY: 1; // Copy flag (OTP) [14:14]
+ UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
+ UINT16 RESERVED_2: 5; // Reserved [20:16]
+ UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
+ UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
+ UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
+ UINT16 RESERVED_3: 2; // Reserved [30:29]
+ UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
+ UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
+ UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
+ UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
+ UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
+ UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
+ UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
+ UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
+ UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
+ UINT32 C_SIZELow2: 2; // Device size [73:62]
+ UINT32 C_SIZEHigh10: 10;// Device size [73:62]
+ UINT32 RESERVED_4: 2; // Reserved [75:74]
+ UINT32 DSR_IMP: 1; // DSR implemented [76:76]
+ UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
+ UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
+ UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
+ UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
+ UINT32 CCC: 12;// Card command classes [95:84]
+ UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
+ UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+ UINT8 TAAC ; // Data read access-time 1 [119:112]
+ UINT8 RESERVED_5: 6; // Reserved [125:120]
+ UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
+}CSD;
+
+typedef struct {
+ UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
+ UINT8 CRC: 7; // CRC [7:1]
+ UINT8 RESERVED_1: 2; // Reserved [9:8]
+ UINT8 FILE_FORMAT: 2; // File format [11:10]
+ UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
+ UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
+ UINT8 COPY: 1; // Copy flag (OTP) [14:14]
+ UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
+ UINT16 RESERVED_2: 5; // Reserved [20:16]
+ UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
+ UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
+ UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
+ UINT16 RESERVED_3: 2; // Reserved [30:29]
+ UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
+ UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
+ UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
+ UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
+ UINT16 RESERVED_4: 1; // Reserved [47:47]
+ UINT32 C_SIZELow16: 16;// Device size [69:48]
+ UINT32 C_SIZEHigh6: 6; // Device size [69:48]
+ UINT32 RESERVED_5: 6; // Reserved [75:70]
+ UINT32 DSR_IMP: 1; // DSR implemented [76:76]
+ UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
+ UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
+ UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
+ UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
+ UINT16 CCC: 12;// Card command classes [95:84]
+ UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
+ UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
+ UINT8 TAAC ; // Data read access-time 1 [119:112]
+ UINT8 RESERVED_6: 6; // 0 [125:120]
+ UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
+}CSD_SDV2;
+
+typedef enum {
+ UNKNOWN_CARD,
+ MMC_CARD, //MMC card
+ SD_CARD, //SD 1.1 card
+ SD_CARD_2, //SD 2.0 or above standard card
+ SD_CARD_2_HIGH //SD 2.0 or above high capacity card
+} CARD_TYPE;
+
+typedef enum {
+ READ,
+ WRITE
+} OPERATION_TYPE;
+
+typedef struct
+{
+ UINT16 RCA;
+ UINTN BlockSize;
+ UINTN NumBlocks;
+ UINTN ClockFrequencySelect;
+ CARD_TYPE CardType;
+ OCR OCRData;
+ CID CIDData;
+ CSD CSDData;
+} CARD_INFO;
+
+#endif
diff --git a/BeagleBoardPkg/MMCHSDxe/MMCHS.inf b/BeagleBoardPkg/MMCHSDxe/MMCHS.inf
new file mode 100644
index 0000000000..3636f35583
--- /dev/null
+++ b/BeagleBoardPkg/MMCHSDxe/MMCHS.inf
@@ -0,0 +1,39 @@
+#%HEADER%
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MMCHS
+ FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = MMCHSInitialize
+
+
+[Sources.common]
+ MMCHS.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ UefiLib
+ UefiDriverEntryPoint
+ MemoryAllocationLib
+ IoLib
+
+[Guids]
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiCpuArchProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEmbeddedExternalDeviceProtocolGuid
+
+[Pcd]
+ gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base
+
+[depex]
+ gEmbeddedExternalDeviceProtocolGuid
diff --git a/BeagleBoardPkg/PciEmulation/PciEmulation.c b/BeagleBoardPkg/PciEmulation/PciEmulation.c
new file mode 100644
index 0000000000..dee0541971
--- /dev/null
+++ b/BeagleBoardPkg/PciEmulation/PciEmulation.c
@@ -0,0 +1,584 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+#include
+
+EFI_CPU_ARCH_PROTOCOL *gCpu;
+EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
+
+#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ PCI_DEVICE_PATH PciDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_IO_DEVICE_PATH;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_PCI_IO_DEVICE_PATH DevicePath;
+ EFI_PCI_IO_PROTOCOL PciIoProtocol;
+ PCI_TYPE00 *ConfigSpace;
+ PCI_ROOT_BRIDGE RootBridge;
+ UINTN Segment;
+} EFI_PCI_IO_PRIVATE_DATA;
+
+#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
+#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
+
+EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
+{
+ {
+ { ACPI_DEVICE_PATH, ACPI_DP, sizeof (ACPI_HID_DEVICE_PATH), 0},
+ EISA_PNP_ID(0x0A03), // HID
+ 0 // UID
+ },
+ {
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, sizeof (PCI_DEVICE_PATH), 0},
+ 0,
+ 0
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
+};
+
+STATIC
+VOID
+ConfigureUSBHost (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Data = 0;
+
+ // Take USB host out of force-standby mode
+ MmioWrite32(UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
+ | UHH_SYSCONFIG_CLOCKACTIVITY_ON
+ | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
+ | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
+ | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
+ MmioWrite32(UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
+ | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
+ | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
+ | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
+ | UHH_HOSTCONFIG_ENA_INCR16_ENABLE
+ | UHH_HOSTCONFIG_ENA_INCR8_ENABLE
+ | UHH_HOSTCONFIG_ENA_INCR4_ENABLE
+ | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
+ | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
+
+ // USB reset (GPIO 147 - Port 5 pin 19) output high
+ MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
+ MmioWrite32(GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
+
+ // Get the Power IC protocol.
+ Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
+ ASSERT_EFI_ERROR(Status);
+
+ //Enable power to the USB host.
+ Status = gTPS65950->Read(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
+ ASSERT_EFI_ERROR(Status);
+
+ //LEDAON & LEDAPWM control the power to the USB host so enable those bits.
+ Data |= (LEDAON | LEDAPWM);
+
+ Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
+ ASSERT_EFI_ERROR(Status);
+}
+
+EFI_STATUS
+PciIoPollMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoPollIo (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMemRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoMemWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoIoRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoIoWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoPciRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Count,
+ TRUE,
+ (PTR)(UINTN)Buffer,
+ TRUE,
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)
+ );
+}
+
+EFI_STATUS
+PciIoPciWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Count,
+ TRUE,
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
+ TRUE,
+ (PTR)(UINTN)Buffer
+ );
+}
+
+EFI_STATUS
+PciIoCopyMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ MAP_INFO_INSTANCE *Map;
+ EFI_STATUS Status;
+
+ if ( HostAddress == NULL || NumberOfBytes == NULL ||
+ DeviceAddress == NULL || Mapping == NULL ) {
+
+ return EFI_INVALID_PARAMETER;
+ }
+
+
+ if (Operation >= EfiPciOperationMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *DeviceAddress = ConvertToPhysicalAddress (HostAddress);
+
+ // Data cache flush (HostAddress, NumberOfBytes);
+
+ // Remember range so we can flush on the other side
+ Status = gBS->AllocatePool (EfiBootServicesData, sizeof (PCI_DMA_MAP), (VOID **) &Map);
+ if (EFI_ERROR(Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ *Mapping = Map;
+
+ Map->HostAddress = (UINTN)HostAddress;
+ Map->DeviceAddress = *DeviceAddress;
+ Map->NumberOfBytes = *NumberOfBytes;
+ Map->Operation = Operation;
+
+ // EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
+ gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoUnmap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ )
+{
+ PCI_DMA_MAP *Map;
+
+ if (Mapping == NULL) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Map = (PCI_DMA_MAP *)Mapping;
+ if (Map->Operation == EfiPciOperationBusMasterWrite) {
+ //
+ // Make sure we read buffer from uncached memory and not the cache
+ //
+ gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
+ } else if (Map->Operation == EfiPciOperationBusMasterCommonBuffer) {
+ //
+ // CPU was using uncached address, so anything in the cached range is bogus
+ //
+ gCpu->FlushDataCache (gCpu, Map->DeviceAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
+ }
+
+ FreePool (Map);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoAllocateBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ )
+{
+ if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (HostAddress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
+ //
+ // We used uncached memory to keep coherency
+ //
+ if (MemoryType == EfiBootServicesData) {
+ *HostAddress = UncachedAllocatePages (Pages);
+ } else if (MemoryType != EfiRuntimeServicesData) {
+ *HostAddress = UncachedAllocateRuntimePages (Pages);
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoFreeBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
+ )
+{
+ if (HostAddress == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ UncachedFreePages (HostAddress, Pages);
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+PciIoFlush (
+ IN EFI_PCI_IO_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetLocation (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ OUT UINTN *SegmentNumber,
+ OUT UINTN *BusNumber,
+ OUT UINTN *DeviceNumber,
+ OUT UINTN *FunctionNumber
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
+
+ if (SegmentNumber != NULL) {
+ *SegmentNumber = Private->Segment;
+ }
+
+ if (BusNumber != NULL) {
+ *BusNumber = 0xff;
+ }
+
+ if (DeviceNumber != NULL) {
+ *DeviceNumber = 0;
+ }
+
+ if (FunctionNumber != NULL) {
+ *FunctionNumber = 0;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
+ IN UINT64 Attributes,
+ OUT UINT64 *Result OPTIONAL
+ )
+{
+ switch (Operation) {
+ case EfiPciIoAttributeOperationGet:
+ case EfiPciIoAttributeOperationSupported:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ // We are not a real PCI device so just say things we kind of do
+ *Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
+ break;
+
+ case EfiPciIoAttributeOperationSet:
+ case EfiPciIoAttributeOperationEnable:
+ case EfiPciIoAttributeOperationDisable:
+ // Since we are not a real PCI device no enable/set or disable operations exist.
+ return EFI_SUCCESS;
+ break;
+
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ };
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports, OPTIONAL
+ OUT VOID **Resources OPTIONAL
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoSetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_PCI_IO_PROTOCOL PciIoTemplate =
+{
+ PciIoPollMem,
+ PciIoPollIo,
+ PciIoMemRead,
+ PciIoMemWrite,
+ PciIoIoRead,
+ PciIoIoWrite,
+ PciIoPciRead,
+ PciIoPciWrite,
+ PciIoCopyMem,
+ PciIoMap,
+ PciIoUnmap,
+ PciIoAllocateBuffer,
+ PciIoFreeBuffer,
+ PciIoFlush,
+ PciIoGetLocation,
+ PciIoAttributes,
+ PciIoGetBarAttributes,
+ PciIoSetBarAttributes,
+ 0,
+ 0
+};
+
+EFI_STATUS
+EFIAPI
+PciEmulationEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+ UINT8 CapabilityLength;
+ UINT8 PhysicalPorts;
+ UINTN Count;
+
+ // Get the Cpu protocol for later use
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
+ ASSERT_EFI_ERROR(Status);
+
+ //Configure USB host for OMAP3530.
+ ConfigureUSBHost();
+
+ // Create a private structure
+ Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));
+ if (Private == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
+ Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
+ Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base
+ Private->Segment = 0; // Default to segment zero
+
+ // Find out the capability register length and number of physical ports.
+ CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
+ PhysicalPorts = (MmioRead32(Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
+
+ // Calculate the total size of the USB registers.
+ Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
+
+ // Enable Port Power bit in Port status and control registers in EHCI register space.
+ // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
+ // host controller implementation includes port power control.
+ for (Count = 0; Count < PhysicalPorts; Count++) {
+ MmioOr32((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
+ }
+
+ // Create fake PCI config space.
+ Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));
+ if (Private->ConfigSpace == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ FreePool(Private);
+ return Status;
+ }
+
+ // Configure PCI config space
+ Private->ConfigSpace->Hdr.VendorId = 0x3530;
+ Private->ConfigSpace->Hdr.DeviceId = 0x3530;
+ Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;
+ Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;
+ Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;
+ Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;
+
+ Handle = NULL;
+
+ // Unique device path.
+ CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
+ Private->DevicePath.AcpiDevicePath.UID = 0;
+
+ // Copy protocol structure
+ CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));
+
+ Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
+ &gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
+ &gEfiDevicePathProtocolGuid, &Private->DevicePath,
+ NULL);
+ if (EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));
+ }
+
+ return Status;
+}
+
diff --git a/BeagleBoardPkg/PciEmulation/PciEmulation.h b/BeagleBoardPkg/PciEmulation/PciEmulation.h
new file mode 100644
index 0000000000..c19cd8c551
--- /dev/null
+++ b/BeagleBoardPkg/PciEmulation/PciEmulation.h
@@ -0,0 +1,305 @@
+/** @file
+
+ Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_ROOT_BRIDGE_H_
+#define _PCI_ROOT_BRIDGE_H_
+
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+extern EFI_CPU_ARCH_PROTOCOL *gCpu;
+
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
+
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+
+#define ACPI_CONFIG_IO 0
+#define ACPI_CONFIG_MMIO 1
+#define ACPI_CONFIG_BUS 2
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
+} ACPI_CONFIG_INFO;
+
+
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
+
+ UINT8 StartBus;
+ UINT8 EndBus;
+ UINT16 Type;
+ UINT32 MemoryStart;
+ UINT32 MemorySize;
+ UINTN IoOffset;
+ UINT32 IoStart;
+ UINT32 IoSize;
+ UINT64 PciAttributes;
+
+ ACPI_CONFIG_INFO *Config;
+
+} PCI_ROOT_BRIDGE;
+
+
+#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+
+typedef union {
+ UINT8 volatile *buf;
+ UINT8 volatile *ui8;
+ UINT16 volatile *ui16;
+ UINT32 volatile *ui32;
+ UINT64 volatile *ui64;
+ UINTN volatile ui;
+} PTR;
+
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS DeviceAddress;
+ UINTN NumberOfBytes;
+ EFI_PCI_IO_PROTOCOL_OPERATION Operation;
+
+} MAP_INFO_INSTANCE;
+
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS HostAddress;
+ EFI_PHYSICAL_ADDRESS DeviceAddress;
+ UINTN NumberOfBytes;
+ EFI_PCI_IO_PROTOCOL_OPERATION Operation;
+} PCI_DMA_MAP;
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollIo (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoCopyMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoUnmap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoAllocateBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFreeBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ OUT VOID *HostAddress
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFlush (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoGetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT UINT64 *Supported,
+ OUT UINT64 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoSetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN OUT UINT64 *ResourceBase,
+ IN OUT UINT64 *ResourceLength
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoConfiguration (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
+ );
+
+//
+// Private Function Prototypes
+//
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN BOOLEAN InStrideFlag,
+ IN PTR In,
+ IN BOOLEAN OutStrideFlag,
+ OUT PTR Out
+ );
+
+BOOLEAN
+PciIoMemAddressValid (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Address
+ );
+
+EFI_STATUS
+EmulatePciIoForEhci (
+ INTN MvPciIfMaxIf
+ );
+
+#endif
+
diff --git a/BeagleBoardPkg/PciEmulation/PciEmulation.inf b/BeagleBoardPkg/PciEmulation/PciEmulation.inf
new file mode 100644
index 0000000000..a6958b197b
--- /dev/null
+++ b/BeagleBoardPkg/PciEmulation/PciEmulation.inf
@@ -0,0 +1,58 @@
+#%HEADER%
+/** @file
+
+ Copyright (c) 2009 Apple, Inc. All rights reserved.
+
+ This document is the property of Apple, Inc.
+ It is considered confidential and proprietary.
+
+ This document may not be reproduced or transmitted in any form,
+ in whole or in part, without the express written permission of
+ Apple, Inc.
+
+**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BeagleBoardPciEmulation
+ FILE_GUID = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = PciEmulationEntryPoint
+
+[Sources.common]
+ PciRootBridgeIo.c
+ PciEmulation.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ BeagleBoardPkg/BeagleBoardPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DxeServicesTableLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UncachedMemoryAllocationLib
+ IoLib
+
+[Protocols]
+ gEfiPciRootBridgeIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiPciHostBridgeResourceAllocationProtocolGuid
+ gEfiCpuArchProtocolGuid
+ gEfiPciIoProtocolGuid
+ gEmbeddedExternalDeviceProtocolGuid
+
+[Depex]
+ gEfiMetronomeArchProtocolGuid AND
+ gEfiCpuArchProtocolGuid AND
+ gEmbeddedExternalDeviceProtocolGuid
+
\ No newline at end of file
diff --git a/BeagleBoardPkg/PciEmulation/PciRootBridgeIo.c b/BeagleBoardPkg/PciEmulation/PciRootBridgeIo.c
new file mode 100644
index 0000000000..d06a56ce57
--- /dev/null
+++ b/BeagleBoardPkg/PciEmulation/PciRootBridgeIo.c
@@ -0,0 +1,306 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+
+BOOLEAN
+PciRootBridgeMemAddressValid (
+ IN PCI_ROOT_BRIDGE *Private,
+ IN UINT64 Address
+ )
+{
+ if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+EFI_STATUS
+PciRootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN BOOLEAN InStrideFlag,
+ IN PTR In,
+ IN BOOLEAN OutStrideFlag,
+ OUT PTR Out
+ )
+{
+ UINTN Stride;
+ UINTN InStride;
+ UINTN OutStride;
+
+
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Stride = (UINTN)1 << Width;
+ InStride = InStrideFlag ? Stride : 0;
+ OutStride = OutStrideFlag ? Stride : 0;
+
+ //
+ // Loop for each iteration and move the data
+ //
+ switch (Width) {
+ case EfiPciWidthUint8:
+ for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
+ *In.ui8 = *Out.ui8;
+ }
+ break;
+ case EfiPciWidthUint16:
+ for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
+ *In.ui16 = *Out.ui16;
+ }
+ break;
+ case EfiPciWidthUint32:
+ for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
+ *In.ui32 = *Out.ui32;
+ }
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciRootBridgeIoPciRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+ UINTN AlignMask;
+ PTR In;
+ PTR Out;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AlignMask = (1 << (Width & 0x03)) - 1;
+ if (Address & AlignMask) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ In.buf = Buffer;
+ Out.buf = (VOID *)(UINTN) Address;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ case EfiPciWidthUint16:
+ case EfiPciWidthUint32:
+ case EfiPciWidthUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
+
+ case EfiPciWidthFifoUint8:
+ case EfiPciWidthFifoUint16:
+ case EfiPciWidthFifoUint32:
+ case EfiPciWidthFifoUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
+
+ case EfiPciWidthFillUint8:
+ case EfiPciWidthFillUint16:
+ case EfiPciWidthFillUint32:
+ case EfiPciWidthFillUint64:
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
+
+ default:
+ break;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+ UINTN AlignMask;
+ PTR In;
+ PTR Out;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AlignMask = (1 << (Width & 0x03)) - 1;
+ if (Address & AlignMask) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ In.buf = (VOID *)(UINTN) Address;
+ Out.buf = Buffer;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ case EfiPciWidthUint16:
+ case EfiPciWidthUint32:
+ case EfiPciWidthUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
+
+ case EfiPciWidthFifoUint8:
+ case EfiPciWidthFifoUint16:
+ case EfiPciWidthFifoUint32:
+ case EfiPciWidthFifoUint64:
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
+
+ case EfiPciWidthFillUint8:
+ case EfiPciWidthFillUint16:
+ case EfiPciWidthFillUint32:
+ case EfiPciWidthFillUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
+
+ default:
+ break;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
+}
+
+
diff --git a/BeagleBoardPkg/Sec/Arm/Macro.inc b/BeagleBoardPkg/Sec/Arm/Macro.inc
new file mode 100755
index 0000000000..cacfef976a
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Arm/Macro.inc
@@ -0,0 +1,67 @@
+//%HEADER%
+ MACRO
+ MmioWrite32Macro $Address, $Data
+ ldr r1, = ($Address)
+ ldr r0, = ($Data)
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioOr32Macro $Address, $OrData
+ ldr r1, =($Address)
+ ldr r2, =($OrData)
+ ldr r0, [r1]
+ orr r0, r0, r2
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioAnd32Macro $Address, $AndData
+ ldr r1, =($Address)
+ ldr r2, =($AndData)
+ ldr r0, [r1]
+ and r0, r0, r2
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioAndThenOr32Macro $Address, $AndData, $OrData
+ ldr r1, =($Address)
+ ldr r0, [r1]
+ ldr r2, =($AndData)
+ and r0, r0, r2
+ ldr r2, =($OrData)
+ orr r0, r0, r2
+ str r0, [r1]
+ MEND
+
+ MACRO
+ MmioWriteFromReg32Macro $Address, $Reg
+ ldr r1, =($Address)
+ str $Reg, [r1]
+ MEND
+
+ MACRO
+ MmioRead32Macro $Address
+ ldr r1, =($Address)
+ ldr r0, [r1]
+ MEND
+
+ MACRO
+ MmioReadToReg32Macro $Address, $Reg
+ ldr r1, =($Address)
+ ldr $Reg, [r1]
+ MEND
+
+ MACRO
+ LoadConstantMacro $Data
+ ldr r0, =($Data)
+ MEND
+
+ MACRO
+ LoadConstantToRegMacro $Data, $Reg
+ ldr $Reg, =($Data)
+ MEND
+
+ END
+
\ No newline at end of file
diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S
new file mode 100755
index 0000000000..0ae8da6a24
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S
@@ -0,0 +1,93 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#include
+#include
+
+.text
+.align 3
+
+.globl ASM_PFX(CEntryPoint)
+.globl ASM_PFX(_ModuleEntryPoint)
+
+ASM_PFX(_ModuleEntryPoint):
+
+ //Disable L2 cache
+ mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
+ bic r0, r0, #0x00000002 // disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
+
+ //Enable Strict alignment checking & Instruction cache
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
+ orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
+ orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+ // Set CPU vectors to start of DRAM
+ mov r0, #0x80000000
+ mcr p15, 0, r0, c12, c0, 0
+
+ /* before we call C code, lets setup the stack pointer */
+stack_pointer_setup:
+
+ //
+ // Set stack based on PCD values. Need to do it this way to make C code work
+ // when it runs from FLASH.
+ //
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */
+ add r4, r2, r3
+
+ //Enter IRQ mode and set up IRQ stack pointer
+ mov r0,#0x12|0x80|0x40
+ msr CPSR_c,r0
+ mov r13,r4
+
+ //Enter Abort mode and set up Abort stack pointer
+ mov r0,#0x17|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ //Enter Undefined mode and set up Undefined stack pointer
+ mov r0,#0x1b|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ //Enter SVC mode and set up SVC stack pointer
+ mov r0,#0x13|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ //Enter System mode and set up System stack pointer
+ mov r0,#0x1f|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ // Call C entry point
+ mov r0, #0x80000000 /* memory base arg0 */
+ mov r1, #0x10000000 /* memory size arg1 */
+
+ bl ASM_PFX(CEntryPoint) /* Assume C code is ARM */
+
+ShouldNeverGetHere:
+ /* _CEntryPoint should never return */
+ b ShouldNeverGetHere
+
+
diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm
new file mode 100755
index 0000000000..fb30e4dd59
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm
@@ -0,0 +1,95 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+#include
+#include
+#include
+ INCLUDE AsmMacroIoLib.inc
+
+ IMPORT CEntryPoint
+ EXPORT _ModuleEntryPoint
+
+ PRESERVE8
+ AREA ModuleEntryPoint, CODE, READONLY
+
+
+_ModuleEntryPoint
+
+ //Disable L2 cache
+ mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
+ bic r0, r0, #0x00000002 // disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
+
+ //Enable Strict alignment checking & Instruction cache
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
+ orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
+ orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+ // Set CPU vectors to start of DRAM
+ mov r0, #0x80000000
+ mcr p15, 0, r0, c12, c0, 0
+ /* before we call C code, lets setup the stack pointer in internal RAM*/
+stack_pointer_setup
+
+ //
+ // Set stack based on PCD values. Need to do it this way to make C code work
+ // when it runs from FLASH.
+ //
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */
+ LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */
+ add r4, r2, r3
+
+ //Enter IRQ mode and set up IRQ stack pointer
+ mov r0,#0x12|0x80|0x40
+ msr CPSR_c,r0
+ mov r13,r4
+
+ //Enter Abort mode and set up Abort stack pointer
+ mov r0,#0x17|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ //Enter Undefined mode and set up Undefined stack pointer
+ mov r0,#0x1b|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ //Enter SVC mode and set up SVC stack pointer
+ mov r0,#0x13|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ //Enter System mode and set up System stack pointer
+ mov r0,#0x1f|0x80|0x40
+ msr CPSR_c,r0
+ sub r4, r4, #0x400
+ mov r13,r4
+
+ // Call C entry point
+ mov r0, #0x80000000 /* memory base arg0 */
+ mov r1, #0x08000000 /* memory size arg1 */
+ blx CEntryPoint /* Assume C code is thumb */
+
+ShouldNeverGetHere
+ /* _CEntryPoint should never return */
+ b ShouldNeverGetHere
+
+ END
+
diff --git a/BeagleBoardPkg/Sec/Cache.c b/BeagleBoardPkg/Sec/Cache.c
new file mode 100755
index 0000000000..12bf990812
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Cache.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+// SoC registers. L3 interconnects
+#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000
+#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000
+#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+
+// SoC registers. L4 interconnects
+#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000
+#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000
+#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+
+VOID
+InitCache (
+ IN UINT32 MemoryBase,
+ IN UINT32 MemoryLength
+ )
+{
+ UINTN UncachedMemoryMask;
+ UINT32 CacheAttributes;
+ ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5];
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+
+ UncachedMemoryMask = PcdGet64(PcdArmUncachedMemoryMask);
+
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+
+ // DDR
+ MemoryTable[0].PhysicalBase = MemoryBase;
+ MemoryTable[0].VirtualBase = MemoryBase;
+ MemoryTable[0].Length = MemoryLength;
+ MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
+
+ // Uncached DDR Mirror
+ MemoryTable[1].PhysicalBase = MemoryBase;
+ MemoryTable[1].VirtualBase = MemoryBase | UncachedMemoryMask;
+ MemoryTable[1].Length = MemoryLength;
+ MemoryTable[1].Attributes = DDR_ATTRIBUTES_UNCACHED;
+
+ // SOC Registers. L3 interconnects
+ MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
+ MemoryTable[2].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
+ MemoryTable[2].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
+ MemoryTable[2].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
+
+ // SOC Registers. L4 interconnects
+ MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
+ MemoryTable[3].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
+ MemoryTable[3].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
+ MemoryTable[3].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
+
+ // End of Table
+ MemoryTable[4].PhysicalBase = 0;
+ MemoryTable[4].VirtualBase = 0;
+ MemoryTable[4].Length = 0;
+ MemoryTable[4].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ArmConfigureMmu(MemoryTable, &TranslationTableBase, &TranslationTableSize);
+
+ BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
+}
diff --git a/BeagleBoardPkg/Sec/Clock.c b/BeagleBoardPkg/Sec/Clock.c
new file mode 100644
index 0000000000..2d814e49e9
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Clock.c
@@ -0,0 +1,70 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+
+#include
+
+VOID
+ClockInit (
+ VOID
+ )
+{
+ //DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
+
+ // Enable PLL5 and set to 120 MHz as a reference clock.
+ MmioWrite32(CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
+ MmioWrite32(CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
+ MmioWrite32(CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
+
+ // Turn on functional & interface clocks to the USBHOST power domain
+ MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
+ | CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);
+ MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);
+
+ // Turn on functional & interface clocks to the USBTLL block.
+ MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);
+ MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);
+
+ // Turn on functional & interface clocks to MMC1 and I2C1 modules.
+ MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE
+ | CM_FCLKEN1_CORE_EN_I2C1_ENABLE);
+ MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE
+ | CM_ICLKEN1_CORE_EN_I2C1_ENABLE);
+
+ // Turn on functional & interface clocks to various Peripherals.
+ MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE
+ | CM_FCLKEN_PER_EN_GPT3_ENABLE
+ | CM_FCLKEN_PER_EN_GPT4_ENABLE
+ | CM_FCLKEN_PER_EN_GPIO2_ENABLE
+ | CM_FCLKEN_PER_EN_GPIO3_ENABLE
+ | CM_FCLKEN_PER_EN_GPIO4_ENABLE
+ | CM_FCLKEN_PER_EN_GPIO5_ENABLE
+ | CM_FCLKEN_PER_EN_GPIO6_ENABLE);
+ MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE
+ | CM_ICLKEN_PER_EN_GPT3_ENABLE
+ | CM_ICLKEN_PER_EN_GPT4_ENABLE
+ | CM_ICLKEN_PER_EN_GPIO2_ENABLE
+ | CM_ICLKEN_PER_EN_GPIO3_ENABLE
+ | CM_ICLKEN_PER_EN_GPIO4_ENABLE
+ | CM_ICLKEN_PER_EN_GPIO5_ENABLE
+ | CM_ICLKEN_PER_EN_GPIO6_ENABLE);
+
+ // Turn on functional & inteface clocks to various wakeup modules.
+ MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE
+ | CM_FCLKEN_WKUP_EN_WDT2_ENABLE);
+ MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE
+ | CM_ICLKEN_WKUP_EN_WDT2_ENABLE);
+}
diff --git a/BeagleBoardPkg/Sec/PadConfiguration.c b/BeagleBoardPkg/Sec/PadConfiguration.c
new file mode 100644
index 0000000000..b478cdfd92
--- /dev/null
+++ b/BeagleBoardPkg/Sec/PadConfiguration.c
@@ -0,0 +1,282 @@
+/** @file
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+
+#define NUM_PINS 238
+
+PAD_CONFIGURATION PadConfigurationTable[NUM_PINS] = {
+ //Pin, MuxMode, PullConfig, InputEnable
+ { SDRC_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D12, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D13, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D14, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D15, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D16, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D17, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D18, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D19, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D20, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D21, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D22, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D23, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D24, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D25, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D26, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D27, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D28, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D29, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D30, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_D31, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_CLK, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_DQS0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_CKE0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { SDRC_CKE1, MUXMODE7, PULLTYPENOSELECT, INPUT },
+ { SDRC_DQS1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_DQS2, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { SDRC_DQS3, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_A1, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A2, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A3, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A4, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A6, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A7, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A8, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A9, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_A10, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D12, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D13, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D14, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_D15, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_NCS0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_NCS1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { GPMC_NCS2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { GPMC_NCS3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { GPMC_NCS4, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { GPMC_NCS5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_NCS6, MUXMODE1, PULLTYPENOSELECT, INPUT },
+ { GPMC_NCS7, MUXMODE1, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { GPMC_CLK, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_NADV_ALE, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_NOE, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_NWE, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_NBE0_CLE, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { GPMC_NBE1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_NWP, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { GPMC_WAIT0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { GPMC_WAIT1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { GPMC_WAIT2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { GPMC_WAIT3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { DSS_PCLK, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_HSYNC, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_PSYNC, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_ACBIAS, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA0, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA1, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA2, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA3, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA4, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA6, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA7, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA8, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA9, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA10, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA11, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA12, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA13, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA14, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA15, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA16, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA17, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA18, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA19, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA20, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA21, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA22, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { DSS_DATA23, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { CAM_HS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { CAM_VS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { CAM_XCLKA, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { CAM_PCLK, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { CAM_FLD, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { CAM_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CAM_XCLKB, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { CAM_WEN, MUXMODE4, PULLTYPENOSELECT, INPUT },
+ { CAM_STROBE, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { CSI2_DX0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CSI2_DY0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CSI2_DX1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { CSI2_DY1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { MCBSP2_FSX, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { MCBSP2_CLKX, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { MCBSP2_DR, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { MCBSP2_DX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { MMC1_CLK, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { MMC1_CMD, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT4, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT5, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT6, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC1_DAT7, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_CLK, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_CMD, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT0, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT1, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT2, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT3, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT4, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT5, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT6, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MMC2_DAT7, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MCBSP3_DX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP3_DR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP3_CLKX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP3_FSX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { UART2_CTS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { UART2_RTS, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { UART2_TX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { UART2_RX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { UART1_TX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { UART1_RTS, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { UART1_CTS, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { UART1_RX, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { MCBSP4_CLKX, MUXMODE1, PULLTYPENOSELECT, INPUT },
+ { MCBSP4_DR, MUXMODE1, PULLTYPENOSELECT, INPUT },
+ { MCBSP4_DX, MUXMODE1, PULLTYPENOSELECT, INPUT },
+ { MCBSP4_FSX, MUXMODE1, PULLTYPENOSELECT, INPUT },
+ { MCBSP1_CLKR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP1_FSR, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { MCBSP1_DX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP1_DR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP1_CLKS, MUXMODE0, PULLTYPESELECT, INPUT },
+ { MCBSP1_FSX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCBSP1_CLKX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { UART3_CTS_RCTX,MUXMODE0, PULLUDENABLE, INPUT },
+ { UART3_RTS_SD, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { UART3_RX_IRRX, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { UART3_TX_IRTX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
+ { HSUSB0_CLK, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_STP, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { HSUSB0_DIR, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_NXT, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA0, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA1, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA2, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA3, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA4, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA5, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA6, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { HSUSB0_DATA7, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { I2C1_SCL, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { I2C1_SDA, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { I2C2_SCL, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { I2C2_SDA, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { I2C3_SCL, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { I2C3_SDA, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { HDQ_SIO, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { MCSPI1_CLK, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MCSPI1_SIMO, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { MCSPI1_SOMI, MUXMODE0, PULLTYPENOSELECT, INPUT },
+ { MCSPI1_CS0, MUXMODE0, PULLUDENABLE, INPUT },
+ { MCSPI1_CS1, MUXMODE0, PULLUDENABLE, OUTPUT },
+ { MCSPI1_CS2, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
+ { MCSPI1_CS3, MUXMODE3, PULLTYPESELECT, INPUT },
+ { MCSPI2_CLK, MUXMODE3, PULLTYPESELECT, INPUT },
+ { MCSPI2_SIMO, MUXMODE3, PULLTYPESELECT, INPUT },
+ { MCSPI2_SOMI, MUXMODE3, PULLTYPESELECT, INPUT },
+ { MCSPI2_CS0, MUXMODE3, PULLTYPESELECT, INPUT },
+ { MCSPI2_CS1, MUXMODE3, PULLTYPESELECT, INPUT },
+ { SYS_NIRQ, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { SYS_CLKOUT2, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
+ { ETK_CLK, MUXMODE3, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
+ { ETK_CTL, MUXMODE3, PULLTYPESELECT, OUTPUT },
+ { ETK_D0, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D1, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D2, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D3, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D4, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D5, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D6, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D7, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D8, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D9, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D10, MUXMODE3, PULLTYPESELECT, OUTPUT },
+ { ETK_D11, MUXMODE3, PULLTYPESELECT, OUTPUT },
+ { ETK_D12, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D13, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D14, MUXMODE3, PULLTYPESELECT, INPUT },
+ { ETK_D15, MUXMODE3, PULLTYPESELECT, INPUT }
+};
+
+VOID
+PadConfiguration (
+ VOID
+ )
+{
+ UINTN Index;
+ UINT16 PadConfiguration;
+ UINTN NumPinsToConfigure = sizeof(PadConfigurationTable)/sizeof(PAD_CONFIGURATION);
+
+ for (Index = 0; Index < NumPinsToConfigure; Index++) {
+ //Set up Pad configuration for particular pin.
+ PadConfiguration = (PadConfigurationTable[Index].MuxMode << MUXMODE_OFFSET);
+ PadConfiguration |= (PadConfigurationTable[Index].PullConfig << PULL_CONFIG_OFFSET);
+ PadConfiguration |= (PadConfigurationTable[Index].InputEnable << INPUTENABLE_OFFSET);
+
+ //Configure the pin with specific Pad configuration.
+ MmioWrite16(PadConfigurationTable[Index].Pin, PadConfiguration);
+ }
+}
diff --git a/BeagleBoardPkg/Sec/Sec.c b/BeagleBoardPkg/Sec/Sec.c
new file mode 100755
index 0000000000..321b35940c
--- /dev/null
+++ b/BeagleBoardPkg/Sec/Sec.c
@@ -0,0 +1,165 @@
+/** @file
+ C Entry point for the SEC. First C code after the reset vector.
+
+ Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include