mirror of https://github.com/acidanthera/audk.git
ArmPkg: Fix Ecc error 8005/8007 in ArmDisassemblerLib
This patch fixes the following Ecc reported error: 8005: Variable name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters 4. Global variable name must start with a 'g' 8007: There should be no use of short (single character) variable names Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
This commit is contained in:
Pierre Gondois
mergify[bot]
parent
60e49aac4e
commit
2f2c0a8b9f
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@ -71,7 +71,7 @@ CHAR8 *gLdmStack[] = {
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#define SIGN(_U) ((_U) ? "" : "-")
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#define WRITE(_W) ((_W) ? "!" : "")
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#define WRITE(_Write) ((_Write) ? "!" : "")
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#define BYTE(_B) ((_B) ? "B":"")
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#define USER(_B) ((_B) ? "^" : "")
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@ -159,23 +159,24 @@ DisassembleArmInstruction (
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)
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{
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UINT32 OpCode;
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CHAR8 *Type, *Root;
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BOOLEAN I, P, U, B, W, L, S, H;
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CHAR8 *Type;
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CHAR8 *Root;
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BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
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UINT32 Rn, Rd, Rm;
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UINT32 imode, offset_8, offset_12;
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UINT32 IMod, Offset8, Offset12;
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UINT32 Index;
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UINT32 shift_imm, shift;
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UINT32 ShiftImm, Shift;
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OpCode = **OpCodePtr;
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I = (OpCode & BIT25) == BIT25;
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P = (OpCode & BIT24) == BIT24;
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U = (OpCode & BIT23) == BIT23;
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B = (OpCode & BIT22) == BIT22; // Also called S
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W = (OpCode & BIT21) == BIT21;
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L = (OpCode & BIT20) == BIT20;
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S = (OpCode & BIT6) == BIT6;
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H = (OpCode & BIT5) == BIT5;
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Imm = (OpCode & BIT25) == BIT25; // I
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Pre = (OpCode & BIT24) == BIT24; // P
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Up = (OpCode & BIT23) == BIT23; // U
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WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
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Write = (OpCode & BIT21) == BIT21; // W
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Load = (OpCode & BIT20) == BIT20; // L
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Sign = (OpCode & BIT6) == BIT6; // S
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Half = (OpCode & BIT5) == BIT5; // H
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Rn = (OpCode >> 16) & 0xf;
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Rd = (OpCode >> 12) & 0xf;
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Rm = (OpCode & 0xf);
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@ -189,7 +190,7 @@ DisassembleArmInstruction (
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// LDREX, STREX
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if ((OpCode & 0x0fe000f0) == 0x01800090) {
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if (L) {
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if (Load) {
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// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
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AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
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} else {
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@ -201,89 +202,89 @@ DisassembleArmInstruction (
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// LDM/STM
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if ((OpCode & 0x0e000000) == 0x08000000) {
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if (L) {
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if (Load) {
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// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
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// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
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// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
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AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
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AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
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} else {
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// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
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// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
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AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
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AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
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}
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return;
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}
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// LDR/STR Address Mode 2
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if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
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offset_12 = OpCode & 0xfff;
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Offset12 = OpCode & 0xfff;
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if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
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Index = AsciiSPrint (Buf, Size, "PLD");
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} else {
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Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
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Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
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}
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if (P) {
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if (!I) {
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if (Pre) {
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if (!Imm) {
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// A5.2.2 [<Rn>, #+/-<offset_12>]
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// A5.2.5 [<Rn>, #+/-<offset_12>]
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));
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} else if ((OpCode & 0x03000ff0) == 0x03000000) {
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// A5.2.3 [<Rn>, +/-<Rm>]
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// A5.2.6 [<Rn>, +/-<Rm>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));
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} else {
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// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
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// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
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shift_imm = (OpCode >> 7) & 0x1f;
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shift = (OpCode >> 5) & 0x3;
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if (shift == 0x0) {
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ShiftImm = (OpCode >> 7) & 0x1f;
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Shift = (OpCode >> 5) & 0x3;
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if (Shift == 0x0) {
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Type = "LSL";
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} else if (shift == 0x1) {
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} else if (Shift == 0x1) {
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Type = "LSR";
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if (shift_imm == 0) {
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shift_imm = 32;
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if (ShiftImm == 0) {
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ShiftImm = 32;
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}
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} else if (shift == 0x2) {
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} else if (Shift == 0x2) {
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Type = "ASR";
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} else if (shift_imm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
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} else if (ShiftImm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
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return;
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} else {
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Type = "ROR";
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}
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
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}
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} else { // !P
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if (!I) {
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} else { // !Pre
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if (!Imm) {
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// A5.2.8 [<Rn>], #+/-<offset_12>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
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} else if ((OpCode & 0x03000ff0) == 0x03000000) {
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// A5.2.9 [<Rn>], +/-<Rm>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
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} else {
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// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
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shift_imm = (OpCode >> 7) & 0x1f;
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shift = (OpCode >> 5) & 0x3;
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ShiftImm = (OpCode >> 7) & 0x1f;
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Shift = (OpCode >> 5) & 0x3;
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if (shift == 0x0) {
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if (Shift == 0x0) {
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Type = "LSL";
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} else if (shift == 0x1) {
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} else if (Shift == 0x1) {
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Type = "LSR";
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if (shift_imm == 0) {
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shift_imm = 32;
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if (ShiftImm == 0) {
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ShiftImm = 32;
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}
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} else if (shift == 0x2) {
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} else if (Shift == 0x2) {
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Type = "ASR";
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} else if (shift_imm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
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} else if (ShiftImm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);
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// FIx me
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return;
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} else {
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Type = "ROR";
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}
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
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}
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}
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return;
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@ -292,18 +293,18 @@ DisassembleArmInstruction (
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if ((OpCode & 0x0e000000) == 0x00000000) {
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// LDR/STR address mode 3
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// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
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if (L) {
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if (!S) {
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if (Load) {
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if (!Sign) {
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Root = "LDR%aH %a, ";
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} else if (!H) {
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} else if (!Half) {
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Root = "LDR%aSB %a, ";
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} else {
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Root = "LDR%aSH %a, ";
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}
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} else {
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if (!S) {
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if (!Sign) {
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Root = "STR%aH %a ";
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} else if (!H) {
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} else if (!Half) {
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Root = "LDR%aD %a ";
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} else {
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Root = "STR%aD %a ";
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@ -312,28 +313,28 @@ DisassembleArmInstruction (
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Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
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S = (OpCode & BIT6) == BIT6;
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H = (OpCode & BIT5) == BIT5;
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offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
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if (P & !W) {
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Sign = (OpCode & BIT6) == BIT6;
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Half = (OpCode & BIT5) == BIT5;
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Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
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if (Pre & !Write) {
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// Immediate offset/index
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if (B) {
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if (WriteBack) {
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// A5.3.2 [<Rn>, #+/-<offset_8>]
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// A5.3.4 [<Rn>, #+/-<offset_8>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
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} else {
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// A5.3.3 [<Rn>, +/-<Rm>]
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// A5.3.5 [<Rn>, +/-<Rm>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
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}
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} else {
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// Register offset/index
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if (B) {
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if (WriteBack) {
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// A5.3.6 [<Rn>], #+/-<offset_8>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
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} else {
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// A5.3.7 [<Rn>], +/-<Rm>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
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}
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}
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return;
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@ -342,19 +343,19 @@ DisassembleArmInstruction (
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if ((OpCode & 0x0fb000f0) == 0x01000050) {
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// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
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// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
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AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
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AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);
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return;
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}
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if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
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// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
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AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
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AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));
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return;
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}
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if ((OpCode & 0xfe500f00) == 0xf8100500) {
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// A4.1.59 RFE<addressing_mode> <Rn>{!}
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AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
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AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));
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return;
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}
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@ -369,9 +370,9 @@ DisassembleArmInstruction (
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if (((OpCode >> 6) & 0x7) == 0) {
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AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
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} else {
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imode = (OpCode >> 18) & 0x3;
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IMod = (OpCode >> 18) & 0x3;
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Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
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(imode == 3) ? "ID":"IE",
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(IMod == 3) ? "ID":"IE",
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((OpCode & BIT8) != 0) ? "A":"",
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((OpCode & BIT7) != 0) ? "I":"",
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((OpCode & BIT6) != 0) ? "F":"");
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@ -390,19 +391,19 @@ DisassembleArmInstruction (
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if ((OpCode & 0x0fb00000) == 0x01000000) {
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// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
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AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
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AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");
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return;
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}
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if ((OpCode & 0x0db00000) == 0x01200000) {
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// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
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if (I) {
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if (Imm) {
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// MSR{<cond>} CPSR_<fields>, #<immediate>
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AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
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AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
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} else {
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// MSR{<cond>} CPSR_<fields>, <Rm>
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AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
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AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
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}
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return;
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}
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@ -416,35 +417,35 @@ DisassembleArmInstruction (
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if ((OpCode & 0x0e000000) == 0x0c000000) {
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// A4.1.19 LDC and A4.1.96 SDC
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if ((OpCode & 0xf0000000) == 0xf0000000) {
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Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
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Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
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} else {
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Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
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Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
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}
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|
||||
if (!P) {
|
||||
if (!W) {
|
||||
if (!Pre) {
|
||||
if (!Write) {
|
||||
// A5.5.5.5 [<Rn>], <option>
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
|
||||
} else {
|
||||
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
|
||||
}
|
||||
} else {
|
||||
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
|
||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0f000010) == 0x0e000010) {
|
||||
// A4.1.32 MRC2, MCR2
|
||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
|
||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((OpCode & 0x0ff00000) == 0x0c400000) {
|
||||
// A4.1.33 MRRC2, MCRR2
|
||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
|
||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
try to reuse existing case entries if possible.
|
||||
|
||||
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
|
|
@ -451,7 +452,7 @@ SignExtend32 (
|
|||
// in the instruction address and you get back the aligned answer
|
||||
//
|
||||
UINT32
|
||||
PCAlign4 (
|
||||
PcAlign4 (
|
||||
IN UINT32 Data
|
||||
)
|
||||
{
|
||||
|
|
@ -486,12 +487,19 @@ DisassembleThumbInstruction (
|
|||
UINT32 Index;
|
||||
UINT32 Offset;
|
||||
UINT16 Rd, Rn, Rm, Rt, Rt2;
|
||||
BOOLEAN H1, H2, imod;
|
||||
BOOLEAN H1Bit; // H1
|
||||
BOOLEAN H2Bit; // H2
|
||||
BOOLEAN IMod; // imod
|
||||
//BOOLEAN ItFlag;
|
||||
UINT32 PC, Target, msbit, lsbit;
|
||||
UINT32 Pc, Target, MsBit, LsBit;
|
||||
CHAR8 *Cond;
|
||||
BOOLEAN S, J1, J2, P, U, W;
|
||||
UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
|
||||
BOOLEAN Sign; // S
|
||||
BOOLEAN J1Bit; // J1
|
||||
BOOLEAN J2Bit; // J2
|
||||
BOOLEAN Pre; // P
|
||||
BOOLEAN UAdd; // U
|
||||
BOOLEAN WriteBack; // W
|
||||
UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
|
||||
UINT32 Mask;
|
||||
|
||||
OpCodePtr = *OpCodePtrPtr;
|
||||
|
|
@ -504,10 +512,10 @@ DisassembleThumbInstruction (
|
|||
Rd = OpCode & 0x7;
|
||||
Rn = (OpCode >> 3) & 0x7;
|
||||
Rm = (OpCode >> 6) & 0x7;
|
||||
H1 = (OpCode & BIT7) != 0;
|
||||
H2 = (OpCode & BIT6) != 0;
|
||||
imod = (OpCode & BIT4) != 0;
|
||||
PC = (UINT32)(UINTN)OpCodePtr;
|
||||
H1Bit = (OpCode & BIT7) != 0;
|
||||
H2Bit = (OpCode & BIT6) != 0;
|
||||
IMod = (OpCode & BIT4) != 0;
|
||||
Pc = (UINT32)(UINTN)OpCodePtr;
|
||||
|
||||
// Increment by the minimum instruction size, Thumb2 could be bigger
|
||||
*OpCodePtrPtr += 1;
|
||||
|
|
@ -548,7 +556,7 @@ DisassembleThumbInstruction (
|
|||
case LOAD_STORE_FORMAT3:
|
||||
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
|
||||
Target = (OpCode & 0xff) << 2;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
|
||||
return;
|
||||
case LOAD_STORE_FORMAT4:
|
||||
// Rt, [SP, #imm8]
|
||||
|
|
@ -583,16 +591,16 @@ DisassembleThumbInstruction (
|
|||
Cond = gCondition[(OpCode >> 8) & 0xf];
|
||||
Buf[Offset-5] = *Cond++;
|
||||
Buf[Offset-4] = *Cond;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
|
||||
return;
|
||||
case UNCONDITIONAL_BRANCH_SHORT:
|
||||
// A6.3.2 B <target_address>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
|
||||
return;
|
||||
|
||||
case BRANCH_EXCHANGE:
|
||||
// A6.3.3 BX|BLX <Rm>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
|
||||
return;
|
||||
|
||||
case DATA_FORMAT1:
|
||||
|
|
@ -629,12 +637,12 @@ DisassembleThumbInstruction (
|
|||
return;
|
||||
case DATA_FORMAT8:
|
||||
// A6.4.3 <Rd>|<Rn>, <Rm>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
|
||||
return;
|
||||
|
||||
case CPS_FORMAT:
|
||||
// A7.1.24
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
||||
return;
|
||||
|
||||
case ENDIAN_FORMAT:
|
||||
|
|
@ -645,13 +653,13 @@ DisassembleThumbInstruction (
|
|||
case DATA_CBZ:
|
||||
// CB{N}Z <Rn>, <Lable>
|
||||
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
|
||||
return;
|
||||
|
||||
case ADR_FORMAT:
|
||||
// ADR <Rd>, <Label>
|
||||
Target = (OpCode & 0xff) << 2;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
|
||||
return;
|
||||
|
||||
case IT_BLOCK:
|
||||
|
|
@ -708,32 +716,32 @@ DisassembleThumbInstruction (
|
|||
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
|
||||
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
|
||||
Target = SignExtend32 (Target, BIT20);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
|
||||
return;
|
||||
case B_T4:
|
||||
// S:I1:I2:imm10:imm11:0
|
||||
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
|
||||
S = (OpCode32 & BIT26) == BIT26;
|
||||
J1 = (OpCode32 & BIT13) == BIT13;
|
||||
J2 = (OpCode32 & BIT11) == BIT11;
|
||||
Target |= (!(J2 ^ S) ? BIT22 : 0); // I2
|
||||
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1
|
||||
Target |= (S ? BIT24 : 0); // S
|
||||
Sign = (OpCode32 & BIT26) == BIT26;
|
||||
J1Bit = (OpCode32 & BIT13) == BIT13;
|
||||
J2Bit = (OpCode32 & BIT11) == BIT11;
|
||||
Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
|
||||
Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
|
||||
Target |= (Sign ? BIT24 : 0); // S
|
||||
Target = SignExtend32 (Target, BIT24);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
|
||||
return;
|
||||
|
||||
case BL_T2:
|
||||
// BLX S:I1:I2:imm10:imm11:0
|
||||
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
|
||||
S = (OpCode32 & BIT26) == BIT26;
|
||||
J1 = (OpCode32 & BIT13) == BIT13;
|
||||
J2 = (OpCode32 & BIT11) == BIT11;
|
||||
Target |= (!(J2 ^ S) ? BIT23 : 0); // I2
|
||||
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
|
||||
Target |= (S ? BIT25 : 0); // S
|
||||
Sign = (OpCode32 & BIT26) == BIT26;
|
||||
J1Bit = (OpCode32 & BIT13) == BIT13;
|
||||
J2Bit = (OpCode32 & BIT11) == BIT11;
|
||||
Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
|
||||
Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
|
||||
Target |= (Sign ? BIT25 : 0); // S
|
||||
Target = SignExtend32 (Target, BIT25);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
|
||||
return;
|
||||
|
||||
case POP_T2:
|
||||
|
|
@ -748,8 +756,8 @@ DisassembleThumbInstruction (
|
|||
|
||||
case STM_FORMAT:
|
||||
// <Rn>{!}, <registers>
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
|
||||
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
|
||||
return;
|
||||
|
||||
case LDM_REG_IMM12_SIGNED:
|
||||
|
|
@ -759,7 +767,7 @@ DisassembleThumbInstruction (
|
|||
// U == 0 means subtrack, U == 1 means add
|
||||
Target = -Target;
|
||||
}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
|
||||
return;
|
||||
|
||||
case LDM_REG_INDIRECT_LSL:
|
||||
|
|
@ -784,36 +792,36 @@ DisassembleThumbInstruction (
|
|||
|
||||
case LDM_REG_IMM8:
|
||||
// <rt>, [<rn>, {, #<imm8>}]{!}
|
||||
W = (OpCode32 & BIT8) == BIT8;
|
||||
U = (OpCode32 & BIT9) == BIT9;
|
||||
P = (OpCode32 & BIT10) == BIT10;
|
||||
WriteBack = (OpCode32 & BIT8) == BIT8;
|
||||
UAdd = (OpCode32 & BIT9) == BIT9;
|
||||
Pre = (OpCode32 & BIT10) == BIT10;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
|
||||
if (P) {
|
||||
if (Pre) {
|
||||
if ((OpCode32 & 0xff) == 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
|
||||
} else {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
|
||||
}
|
||||
} else {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
|
||||
}
|
||||
return;
|
||||
|
||||
case LDRD_REG_IMM8_SIGNED:
|
||||
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
|
||||
P = (OpCode32 & BIT24) == BIT24; // index = P
|
||||
U = (OpCode32 & BIT23) == BIT23;
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
Pre = (OpCode32 & BIT24) == BIT24; // index = P
|
||||
UAdd = (OpCode32 & BIT23) == BIT23;
|
||||
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
|
||||
if (P) {
|
||||
if (Pre) {
|
||||
if ((OpCode32 & 0xff) == 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, "]");
|
||||
} else {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
|
||||
}
|
||||
} else {
|
||||
if ((OpCode32 & 0xff) != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
|
@ -825,7 +833,7 @@ DisassembleThumbInstruction (
|
|||
// U == 0 means subtrack, U == 1 means add
|
||||
Target = -Target;
|
||||
}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
|
||||
return;
|
||||
|
||||
case LDREXB:
|
||||
|
|
@ -840,14 +848,14 @@ DisassembleThumbInstruction (
|
|||
|
||||
case SRS_FORMAT:
|
||||
// SP{!}, #<mode>
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);
|
||||
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
|
||||
return;
|
||||
|
||||
case RFE_FORMAT:
|
||||
// <Rn>{!}
|
||||
W = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
|
||||
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
|
||||
return;
|
||||
|
||||
case ADD_IMM12:
|
||||
|
|
@ -917,9 +925,9 @@ DisassembleThumbInstruction (
|
|||
// ADDR <Rd>, <label>
|
||||
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
||||
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
|
||||
Target = PCAlign4 (PC) - Target;
|
||||
Target = PcAlign4 (Pc) - Target;
|
||||
} else {
|
||||
Target = PCAlign4 (PC) + Target;
|
||||
Target = PcAlign4 (Pc) + Target;
|
||||
}
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
|
||||
return;
|
||||
|
|
@ -932,52 +940,52 @@ DisassembleThumbInstruction (
|
|||
|
||||
case BFC_THUMB2:
|
||||
// BFI <Rd>, <Rn>, #<lsb>, #<width>
|
||||
msbit = OpCode32 & 0x1f;
|
||||
lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
|
||||
MsBit = OpCode32 & 0x1f;
|
||||
LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
|
||||
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
|
||||
// BFC <Rd>, #<lsb>, #<width>
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
|
||||
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
|
||||
} else {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
|
||||
}
|
||||
return;
|
||||
|
||||
case CPD_THUMB2:
|
||||
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
|
||||
coproc = (OpCode32 >> 8) & 0xf;
|
||||
opc1 = (OpCode32 >> 20) & 0xf;
|
||||
opc2 = (OpCode32 >> 5) & 0x7;
|
||||
Coproc = (OpCode32 >> 8) & 0xf;
|
||||
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||
Opc2 = (OpCode32 >> 5) & 0x7;
|
||||
CRd = (OpCode32 >> 12) & 0xf;
|
||||
CRn = (OpCode32 >> 16) & 0xf;
|
||||
CRm = OpCode32 & 0xf;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);
|
||||
if (opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
|
||||
if (Opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
|
||||
}
|
||||
return;
|
||||
|
||||
case MRC_THUMB2:
|
||||
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
|
||||
coproc = (OpCode32 >> 8) & 0xf;
|
||||
opc1 = (OpCode32 >> 20) & 0xf;
|
||||
opc2 = (OpCode32 >> 5) & 0x7;
|
||||
Coproc = (OpCode32 >> 8) & 0xf;
|
||||
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||
Opc2 = (OpCode32 >> 5) & 0x7;
|
||||
CRn = (OpCode32 >> 16) & 0xf;
|
||||
CRm = OpCode32 & 0xf;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);
|
||||
if (opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
|
||||
if (Opc2 != 0) {
|
||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
|
||||
}
|
||||
return;
|
||||
|
||||
case MRRC_THUMB2:
|
||||
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
|
||||
coproc = (OpCode32 >> 8) & 0xf;
|
||||
opc1 = (OpCode32 >> 20) & 0xf;
|
||||
Coproc = (OpCode32 >> 8) & 0xf;
|
||||
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||
CRn = (OpCode32 >> 16) & 0xf;
|
||||
CRm = OpCode32 & 0xf;
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
|
||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
|
||||
return;
|
||||
|
||||
case THUMB2_2REGS:
|
||||
|
|
|
|||
Loading…
Reference in New Issue