mirror of https://github.com/acidanthera/audk.git
MdeModulePkg Xhci: Correct description of Timeout param in XhciReg.h
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=653 Correct description of Timeout param in XhciReg.h to be matched with XhciReg.c. Cc: Alexei Fedorov <Alexei.Fedorov@arm.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This commit is contained in:
parent
0e6be43fd3
commit
2f6ef874ac
|
@ -2,7 +2,7 @@
|
|||
|
||||
This file contains the register definition of XHCI host controller.
|
||||
|
||||
Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
@ -399,7 +399,7 @@ XhcClearOpRegBit (
|
|||
@param Offset The offset of the operational register.
|
||||
@param Bit The bit of the register to wait for.
|
||||
@param WaitToSet Wait the bit to set or clear.
|
||||
@param Timeout The time to wait before abort (in microsecond, us).
|
||||
@param Timeout The time to wait before abort (in millisecond, ms).
|
||||
|
||||
@retval EFI_SUCCESS The bit successfully changed by host controller.
|
||||
@retval EFI_TIMEOUT The time out occurred.
|
||||
|
@ -521,7 +521,7 @@ XhcIsSysError (
|
|||
Reset the XHCI host controller.
|
||||
|
||||
@param Xhc The XHCI Instance.
|
||||
@param Timeout Time to wait before abort (in microsecond, us).
|
||||
@param Timeout Time to wait before abort (in millisecond, ms).
|
||||
|
||||
@retval EFI_SUCCESS The XHCI host controller is reset.
|
||||
@return Others Failed to reset the XHCI before Timeout.
|
||||
|
@ -537,7 +537,7 @@ XhcResetHC (
|
|||
Halt the XHCI host controller.
|
||||
|
||||
@param Xhc The XHCI Instance.
|
||||
@param Timeout Time to wait before abort (in microsecond, us).
|
||||
@param Timeout Time to wait before abort (in millisecond, ms).
|
||||
|
||||
@return EFI_SUCCESS The XHCI host controller is halt.
|
||||
@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
|
||||
|
@ -553,7 +553,7 @@ XhcHaltHC (
|
|||
Set the XHCI host controller to run.
|
||||
|
||||
@param Xhc The XHCI Instance.
|
||||
@param Timeout Time to wait before abort (in microsecond, us).
|
||||
@param Timeout Time to wait before abort (in millisecond, ms).
|
||||
|
||||
@return EFI_SUCCESS The XHCI host controller is running.
|
||||
@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
Private Header file for Usb Host Controller PEIM
|
||||
|
||||
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions
|
||||
|
@ -287,7 +287,7 @@ XhcPeiClearOpRegBit (
|
|||
@param Offset The offset of the operational register.
|
||||
@param Bit The bit of the register to wait for.
|
||||
@param WaitToSet Wait the bit to set or clear.
|
||||
@param Timeout The time to wait before abort (in microsecond, us).
|
||||
@param Timeout The time to wait before abort (in millisecond, ms).
|
||||
|
||||
@retval EFI_SUCCESS The bit successfully changed by host controller.
|
||||
@retval EFI_TIMEOUT The time out occurred.
|
||||
|
|
Loading…
Reference in New Issue