mirror of https://github.com/acidanthera/audk.git
ArmPkg: Add support for GICv4
Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This commit is contained in:
Sami Mujawar
Ard Biesheuvel
parent
bbce001515
commit
301402fa47
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2017, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -19,6 +19,16 @@
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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// In GICv3, there are 2 x 64KB frames:
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// Redistributor control frame + SGI Control & Generation frame
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#define GIC_V3_REDISTRIBUTOR_GRANULARITY (ARM_GICR_CTLR_FRAME_SIZE \
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+ ARM_GICR_SGI_PPI_FRAME_SIZE)
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// In GICv4, there are 2 additional 64KB frames:
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// VLPI frame + Reserved page frame
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#define GIC_V4_REDISTRIBUTOR_GRANULARITY (GIC_V3_REDISTRIBUTOR_GRANULARITY \
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+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
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+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
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#define ISENABLER_ADDRESS(base,offset) ((base) + \
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))
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@ -54,12 +64,11 @@ GicGetCpuRedistributorBase (
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IN ARM_GIC_ARCH_REVISION Revision
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)
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{
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UINTN Index;
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UINTN MpId;
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UINTN CpuAffinity;
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UINTN Affinity;
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UINTN GicRedistributorGranularity;
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UINTN GicCpuRedistributorBase;
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UINT64 TypeRegister;
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MpId = ArmReadMpidr ();
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// Define CPU affinity as:
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@ -68,27 +77,30 @@ GicGetCpuRedistributorBase (
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CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
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((MpId & ARM_CORE_AFF3) >> 8);
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if (Revision == ARM_GIC_ARCH_REVISION_3) {
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// 2 x 64KB frame:
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// Redistributor control frame + SGI Control & Generation frame
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GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE
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+ ARM_GICR_SGI_PPI_FRAME_SIZE;
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} else {
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if (Revision < ARM_GIC_ARCH_REVISION_3) {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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return 0;
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}
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GicCpuRedistributorBase = GicRedistributorBase;
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for (Index = 0; Index < PcdGet32 (PcdCoreCount); Index++) {
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Affinity = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER) >> 32;
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do {
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TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
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Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
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if (Affinity == CpuAffinity) {
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return GicCpuRedistributorBase;
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}
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// Move to the next GIC Redistributor frame
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GicCpuRedistributorBase += GicRedistributorGranularity;
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}
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// Move to the next GIC Redistributor frame.
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// The GIC specification does not forbid a mixture of redistributors
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// with or without support for virtual LPIs, so we test Virtual LPIs
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// Support (VLPIS) bit for each frame to decide the granularity.
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// Note: The assumption here is that the redistributors are adjacent
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// for all CPUs. However this may not be the case for NUMA systems.
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GicCpuRedistributorBase += (((ARM_GICR_TYPER_VLPIS & TypeRegister) != 0)
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? GIC_V4_REDISTRIBUTOR_GRANULARITY
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: GIC_V3_REDISTRIBUTOR_GRANULARITY);
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} while ((TypeRegister & ARM_GICR_TYPER_LAST) == 0);
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// The Redistributor has not been found for the current CPU
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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@ -1,5 +1,5 @@
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#/* @file
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# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2018, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -44,8 +44,5 @@
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ArmPlatformPkg/ArmPlatformPkg.dec
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MdePkg/MdePkg.dec
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[Pcd]
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gArmPlatformTokenSpaceGuid.PcdCoreCount
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[FeaturePcd]
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gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2017, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -62,10 +62,26 @@
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// GIC Redistributor
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#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
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// GIC Redistributor Control frame
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#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
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// GIC Redistributor TYPER bit assignments
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#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
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#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
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#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
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#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
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#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
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// Selection Support
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#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
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#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
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#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
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#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
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ARM_GICR_TYPER_AFFINITY) >> 32)
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// GIC SGI & PPI Redistributor frame
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#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
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#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
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