tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear" 

This reverts commit 39b9a5ffe6.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
This commit is contained in:
Laszlo Ersek 2019-05-29 11:49:07 +02:00
parent f03859ea6c
commit 305cd4f783
3 changed files with 6 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
OvmfPkg/PlatformPei/MemDetect.c
View File

@ -42,8 +42,6 @@ STATIC UINT32 mS3AcpiReservedMemorySize;
STATIC UINT16 mQ35TsegMbytes;
UINT32 mQemuUc32Base;
VOID
Q35TsegMbytesInitialization (
VOID
@ -665,8 +663,6 @@ QemuInitializeRam (
// cover it exactly.
//
if (IsMtrrSupported ()) {
UINT32 Uc32Size;
MtrrGetAllMtrrs (&MtrrSettings);
//
@ -693,24 +689,11 @@ QemuInitializeRam (
//
// Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as
// uncacheable. Make sure one variable MTRR suffices by truncating the size
// to a whole power of two. This will round the base *up*, and a gap (not
// used for either RAM or MMIO) may stay in the middle, marked as
// cacheable-by-default.
// uncacheable
//
Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);
if (mQemuUc32Base != LowerMemorySize) {
DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "
"an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize,
mQemuUc32Base, Uc32Size));
}
Status = MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size,
CacheUncacheable);
Status = MtrrSetMemoryAttribute (LowerMemorySize,
SIZE_4GB - LowerMemorySize, CacheUncacheable);
ASSERT_EFI_ERROR (Status);
} else {
mQemuUc32Base = (UINT32)LowerMemorySize;
}
}

4
OvmfPkg/PlatformPei/Platform.c
View File

@ -174,12 +174,14 @@ MemMapInitialization (
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
if (!mXen) {
UINT32 TopOfLowRam;
UINT64 PciExBarBase;
UINT32 PciBase;
UINT32 PciSize;
TopOfLowRam = GetSystemMemorySizeBelow4gb ();
PciExBarBase = 0;
PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;
PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// The 32-bit PCI host aperture is expected to fall between the top of

2
OvmfPkg/PlatformPei/Platform.h
View File

@ -114,6 +114,4 @@ extern UINT32 mMaxCpuCount;
extern UINT16 mHostBridgeDevId;
extern UINT32 mQemuUc32Base;
#endif // _PLATFORM_PEI_H_INCLUDED_