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UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 

Needn't to copy register table if AllocatedSize is 0.

v4:
  Fix potential uninitialized variable issue.

v5:
  Set DestinationRegisterTableList[Index].RegisterTableEntry before
  RegisterTableEntry is updated.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Jeff Fan 2017-03-07 20:01:51 +08:00
parent 8b371e93f2
commit 30d995ee08
1 changed files with 17 additions and 13 deletions
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30
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
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@ -826,21 +826,25 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
ASSERT (RegisterTableEntry != NULL);
CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
//
// Go though all MSRs in register table to initialize MSR spin lock
//
for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
//
// Initialize MSR spin lock only for those MSRs need bit field writing
//
InitMsrSpinLockByIndex (RegisterTableEntry->Index);
if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
RegisterTableEntry = AllocateCopyPool (
DestinationRegisterTableList[Index].AllocatedSize,
(VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
);
ASSERT (RegisterTableEntry != NULL);
DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
//
// Go though all MSRs in register table to initialize MSR spin lock
//
for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
//
// Initialize MSR spin lock only for those MSRs need bit field writing
//
InitMsrSpinLockByIndex (RegisterTableEntry->Index);
}
}
}
DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
}
}