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MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()

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To enable AARCH64 native instruction support for Openssl,
some interfaces must be implemented. OPENSSL_cpuid_setup()
allows to probe the supported features of the platform.

Add ArmReadIdAA64Isar0Reg() to read the AA64Isar0, containing
Arm64 instruction capabilities.
A similar ArmReadIdAA64Isar0() function is available in the ArmPkg,
but the CryptoPkg where OPENSSL_cpuid_setup will reside cannot rely
on the ArmPkg.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
This commit is contained in:
Pierre Gondois 2023-10-04 14:26:05 +02:00 committed by mergify[bot]
parent a72d93e163
commit 30e53f8b5e
4 changed files with 134 additions and 0 deletions
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72
MdePkg/Include/Library/BaseLib.h
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@ -141,6 +141,78 @@ ArmReadCntPctReg (
VOID
);
//
// Bit shifts for the ID_AA64ISAR0_EL1 register.
//
#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)
#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)
#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)
#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)
#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)
#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)
#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)
#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)
#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)
#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)
#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)
#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)
#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)
#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)
//
// Bit masks for the ID_AA64ISAR0_EL1 fields.
//
#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)
#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)
//
// Bit masks for the ID_AA64ISAR0_EL1 field values.
//
#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)
#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)
#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)
#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)
#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)
#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)
#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)
/**
Reads the current value of ID_AA64ISAR0_EL1 register.
Reads and returns the current value of ID_AA64ISAR0_EL1.
This function is only available on AARCH64.
@return The current value of ID_AA64ISAR0_EL1
**/
UINT64
EFIAPI
ArmReadIdAA64Isar0Reg (
VOID
);
#endif // defined (MDE_CPU_AARCH64)
#if defined (MDE_CPU_RISCV64)

30
MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S Normal file
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@ -0,0 +1,30 @@
#------------------------------------------------------------------------------
#
# ArmReadIdAA64Isar0Reg() for AArch64
#
# Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#------------------------------------------------------------------------------
.text
.p2align 2
GCC_ASM_EXPORT(ArmReadIdAA64Isar0Reg)
#/**
# Reads the ID_AA64ISAR0 Register.
#
# @return The contents of the ID_AA64ISAR0 register.
#
#**/
#UINT64
#EFIAPI
#ArmReadIdAA64Isar0Reg (
# VOID
# );
#
ASM_PFX(ArmReadIdAA64Isar0Reg):
AARCH64_BTI(c)
mrs x0, id_aa64isar0_el1
ret

30
MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm Normal file
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@ -0,0 +1,30 @@
;------------------------------------------------------------------------------
;
; ArmReadIdAA64Isar0Reg() for AArch64
;
; Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
;
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
EXPORT ArmReadIdAA64Isar0Reg
AREA BaseLib_LowLevel, CODE, READONLY
;/**
; Reads the ID_AA64ISAR0 Register.
;
; @return The contents of the ID_AA64ISAR0 register.
;
;**/
;UINT64
;EFIAPI
;ArmReadIdAA64Isar0Reg (
; VOID
; );
;
ArmReadIdAA64Isar0Reg
mrs x0, id_aa64isar0_el1
ret
END

2
MdePkg/Library/BaseLib/BaseLib.inf
View File

@ -379,6 +379,7 @@
AArch64/CpuBreakpoint.S | GCC
AArch64/SpeculationBarrier.S | GCC
AArch64/ArmReadCntPctReg.S | GCC
AArch64/ArmReadIdAA64Isar0Reg.S | GCC
AArch64/MemoryFence.asm | MSFT
AArch64/SwitchStack.asm | MSFT
@ -389,6 +390,7 @@
AArch64/CpuBreakpoint.asm | MSFT
AArch64/SpeculationBarrier.asm | MSFT
AArch64/ArmReadCntPctReg.asm | MSFT
AArch64/ArmReadIdAA64Isar0Reg.asm | MSFT
[Sources.RISCV64]
Math64.c