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MdePkg: Rename Cache Management Function To Clarify Fence Based Op
There are different ways to manage cache on RISC-V Processors. One way is to use fence instruction. Another way is to use CPU specific cache management operation instructions ratified as per RISC-V ISA specifications to be introduced in future patches. Current method is fence instruction based, rename the function accordingly to add that clarity. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
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**/
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**/
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VOID
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VOID
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EFIAPI
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EFIAPI
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RiscVInvalidateInstCacheAsm (
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RiscVInvalidateInstCacheFenceAsm (
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VOID
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VOID
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);
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);
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@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
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**/
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**/
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VOID
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VOID
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EFIAPI
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EFIAPI
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RiscVInvalidateDataCacheAsm (
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RiscVInvalidateDataCacheFenceAsm (
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VOID
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VOID
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);
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);
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@ -21,7 +21,7 @@ InvalidateInstructionCache (
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VOID
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VOID
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)
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)
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{
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{
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RiscVInvalidateInstCacheAsm ();
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RiscVInvalidateInstCacheFenceAsm ();
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}
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}
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/**
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/**
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@ -193,7 +193,7 @@ InvalidateDataCache (
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VOID
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VOID
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)
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)
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{
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{
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RiscVInvalidateDataCacheAsm ();
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RiscVInvalidateDataCacheFenceAsm ();
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}
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}
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/**
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/**
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@ -9,13 +9,13 @@
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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.align 3
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.align 3
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ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
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ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
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ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
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ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)
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ASM_PFX(RiscVInvalidateInstCacheAsm):
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ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
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fence.i
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fence.i
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ret
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ret
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ASM_PFX(RiscVInvalidateDataCacheAsm):
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ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
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fence
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fence
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ret
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ret
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