MdePkg: Rename Cache Management Function To Clarify Fence Based Op

There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Pedro Falcato <pedro.falcato@gmail.com>

Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Dhaval 2023-12-13 20:29:28 +05:30 committed by mergify[bot]
parent 286b30f517
commit 30faafd024
3 changed files with 8 additions and 8 deletions

View File

@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
**/
VOID
EFIAPI
RiscVInvalidateInstCacheAsm (
RiscVInvalidateInstCacheFenceAsm (
VOID
);
@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
**/
VOID
EFIAPI
RiscVInvalidateDataCacheAsm (
RiscVInvalidateDataCacheFenceAsm (
VOID
);

View File

@ -21,7 +21,7 @@ InvalidateInstructionCache (
VOID
)
{
RiscVInvalidateInstCacheAsm ();
RiscVInvalidateInstCacheFenceAsm ();
}
/**
@ -193,7 +193,7 @@ InvalidateDataCache (
VOID
)
{
RiscVInvalidateDataCacheAsm ();
RiscVInvalidateDataCacheFenceAsm ();
}
/**

View File

@ -9,13 +9,13 @@
//------------------------------------------------------------------------------
.align 3
ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)
ASM_PFX(RiscVInvalidateInstCacheAsm):
ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
fence.i
ret
ASM_PFX(RiscVInvalidateDataCacheAsm):
ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
fence
ret