mirror of https://github.com/acidanthera/audk.git
MdeModulePkg: BaseSerialPortLib16550 library to support PCI UART device.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> Reviewed-by: Kinney, Michael D <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15783 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Gao, Liming
lgao4
parent
883e23d0d3
commit
31122d8c9a
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@ -13,10 +13,18 @@
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**/
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#include <Base.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/SerialPortLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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#include <Library/PlatformHookLib.h>
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#include <Library/BaseLib.h>
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//
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// PCI Defintions.
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//
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#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
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//
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// 16550 UART register offsets and bitfields
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@ -40,6 +48,15 @@
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#define B_UART_MSR_CTS BIT4
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#define B_UART_MSR_DSR BIT5
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//
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// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
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//
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typedef struct {
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UINT8 Device;
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UINT8 Function;
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UINT16 PowerManagementStatusAndControlRegister;
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} PCI_UART_DEVICE_INFO;
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/**
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Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
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MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
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@ -53,13 +70,14 @@
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**/
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UINT8
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SerialPortReadRegister (
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UINTN Base,
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UINTN Offset
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)
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{
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if (PcdGetBool (PcdSerialUseMmio)) {
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return MmioRead8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset);
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return MmioRead8 (Base + Offset);
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} else {
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return IoRead8 ((UINT16)PcdGet64 (PcdSerialRegisterBase) + Offset);
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return IoRead8 (Base + Offset);
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}
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}
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@ -77,17 +95,319 @@ SerialPortReadRegister (
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**/
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UINT8
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SerialPortWriteRegister (
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UINTN Base,
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UINTN Offset,
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UINT8 Value
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)
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{
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if (PcdGetBool (PcdSerialUseMmio)) {
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return MmioWrite8 ((UINTN)PcdGet64 (PcdSerialRegisterBase) + Offset, Value);
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return MmioWrite8 (Base + Offset, Value);
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} else {
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return IoWrite8 ((UINT16)PcdGet64 (PcdSerialRegisterBase) + Offset, Value);
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return IoWrite8 (Base + Offset, Value);
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}
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}
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/**
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Update the value of an 16-bit PCI configuration register in a PCI device. If the
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PCI Configuration register specified by PciAddress is already programmed with a
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non-zero value, then return the current value. Otherwise update the PCI configuration
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register specified by PciAddress with the value specified by Value and return the
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value programmed into the PCI configuration register. All values must be masked
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using the bitmask specified by Mask.
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@param PciAddress PCI Library address of the PCI Configuration register to update.
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@param Value The value to program into the PCI Configuration Register.
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@param Mask Bitmask of the bits to check and update in the PCI configuration register.
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**/
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UINT16
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SerialPortLibUpdatePciRegister16 (
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UINTN PciAddress,
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UINT16 Value,
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UINT16 Mask
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)
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{
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UINT16 CurrentValue;
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CurrentValue = PciRead16 (PciAddress) & Mask;
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if (CurrentValue != 0) {
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return CurrentValue;
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}
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return PciWrite16 (PciAddress, Value & Mask);
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}
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/**
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Update the value of an 32-bit PCI configuration register in a PCI device. If the
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PCI Configuration register specified by PciAddress is already programmed with a
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non-zero value, then return the current value. Otherwise update the PCI configuration
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register specified by PciAddress with the value specified by Value and return the
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value programmed into the PCI configuration register. All values must be masked
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using the bitmask specified by Mask.
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@param PciAddress PCI Library address of the PCI Configuration register to update.
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@param Value The value to program into the PCI Configuration Register.
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@param Mask Bitmask of the bits to check and update in the PCI configuration register.
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@return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
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**/
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UINT32
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SerialPortLibUpdatePciRegister32 (
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UINTN PciAddress,
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UINT32 Value,
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UINT32 Mask
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)
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{
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UINT32 CurrentValue;
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CurrentValue = PciRead32 (PciAddress) & Mask;
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if (CurrentValue != 0) {
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return CurrentValue;
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}
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return PciWrite32 (PciAddress, Value & Mask);
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}
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/**
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Retrieve the I/O or MMIO base address register for the PCI UART device.
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This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
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Device if they are not already enabled.
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@return The base address register of the PCI UART device.
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**/
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UINTN
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GetSerialRegisterBase (
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VOID
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)
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{
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UINTN PciLibAddress;
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UINTN PrimaryBusNumber;
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UINTN BusNumber;
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UINTN SubordinateBusNumber;
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UINT32 ParentIoBase;
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UINT32 ParentIoLimit;
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UINT16 ParentMemoryBase;
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UINT16 ParentMemoryLimit;
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UINT32 IoBase;
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UINT32 IoLimit;
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UINT16 MemoryBase;
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UINT16 MemoryLimit;
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UINTN SerialRegisterBase;
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UINTN BarIndex;
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UINT32 RegisterBaseMask;
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PCI_UART_DEVICE_INFO *DeviceInfo;
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//
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// Get PCI Device Info
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//
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DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
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//
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// If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
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//
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if (DeviceInfo->Device == 0xff) {
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return (UINTN)PcdGet64 (PcdSerialRegisterBase);
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}
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//
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// Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
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//
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ParentMemoryBase = 0 >> 16;
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ParentMemoryLimit = 0xfff00000 >> 16;
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ParentIoBase = 0 >> 12;
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ParentIoLimit = 0xf000 >> 12;
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//
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// Enable I/O and MMIO in PCI Bridge
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// Assume Root Bus Numer is Zero.
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//
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for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
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//
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// Compute PCI Lib Address to PCI to PCI Bridge
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Retrieve and verify the bus numbers in the PCI to PCI Bridge
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//
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PrimaryBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
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BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
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if (BusNumber == 0 || BusNumber > SubordinateBusNumber) {
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return 0;
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}
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//
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// Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
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//
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if (PcdGetBool (PcdSerialUseMmio)) {
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MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryLimit)) & 0xfff0;
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MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryBase)) & 0xfff0;
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//
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// If PCI Bridge MMIO window is disabled, then return 0
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//
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if (MemoryLimit < MemoryBase) {
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return 0;
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}
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//
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// If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
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//
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if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) {
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return 0;
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}
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ParentMemoryBase = MemoryBase;
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ParentMemoryLimit = MemoryLimit;
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} else {
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IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimit));
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if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
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IoLimit = IoLimit >> 4;
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} else {
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IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimitUpper16)) << 4) | (IoLimit >> 4);
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}
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IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBase));
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if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
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IoBase = IoBase >> 4;
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} else {
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IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBaseUpper16)) << 4) | (IoBase >> 4);
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}
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//
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// If PCI Bridge I/O window is disabled, then return 0
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//
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if (IoLimit < IoBase) {
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return 0;
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}
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//
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// If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
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//
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if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {
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return 0;
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}
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ParentIoBase = IoBase;
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ParentIoLimit = IoLimit;
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}
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}
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//
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// Compute PCI Lib Address to PCI UART
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Find the first IO or MMIO BAR
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//
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RegisterBaseMask = 0xFFFFFFF0;
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for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) {
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SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);
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if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {
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//
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// MMIO BAR is found
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//
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RegisterBaseMask = 0xFFFFFFF0;
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break;
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}
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if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {
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//
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// IO BAR is found
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//
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RegisterBaseMask = 0xFFFFFFF8;
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break;
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}
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}
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//
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// MMIO or IO BAR is not found.
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//
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if (BarIndex == PCI_MAX_BAR) {
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return 0;
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}
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//
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// Program UART BAR
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//
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SerialRegisterBase = SerialPortLibUpdatePciRegister32 (
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PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,
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(UINT32)PcdGet64 (PcdSerialRegisterBase),
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RegisterBaseMask
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);
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//
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// Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
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//
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if (PcdGetBool (PcdSerialUseMmio)) {
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if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) {
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return 0;
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}
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} else {
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if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) {
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return 0;
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}
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}
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//
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// Enable I/O and MMIO in PCI UART Device if they are not already enabled
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//
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PciOr16 (
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PciLibAddress + PCI_COMMAND_OFFSET,
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PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
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);
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//
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// Force D0 state if a Power Management and Status Register is specified
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//
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if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
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if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
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PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
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//
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// If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
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//
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SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
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}
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}
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//
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// Get PCI Device Info
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//
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DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
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//
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// Enable I/O or MMIO in PCI Bridge
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// Assume Root Bus Numer is Zero.
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//
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for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
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//
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// Compute PCI Lib Address to PCI to PCI Bridge
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//
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PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
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//
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// Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
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//
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PciOr16 (
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PciLibAddress + PCI_COMMAND_OFFSET,
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PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
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);
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//
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// Force D0 state if a Power Management and Status Register is specified
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//
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if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
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if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
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PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
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}
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}
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BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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}
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return SerialRegisterBase;
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}
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/**
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Return whether the hardware flow control signal allows writing.
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@ -96,7 +416,7 @@ SerialPortWriteRegister (
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**/
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BOOLEAN
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SerialPortWritable (
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VOID
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UINTN SerialRegisterBase
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)
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{
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if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
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@ -113,7 +433,7 @@ SerialPortWritable (
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// 1 0 Cable connected, but not clear to send. Wait
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// 1 1 Cable connected, and clear to send. Transmit
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//
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return (BOOLEAN) ((SerialPortReadRegister (R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
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return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
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} else {
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//
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// Wait for both DSR and CTS to be set OR for DSR to be clear.
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@ -127,7 +447,7 @@ SerialPortWritable (
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// 1 0 Cable connected, but not clear to send. Wait
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// 1 1 Cable connected, and clar to send. Transmit
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//
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return (BOOLEAN) ((SerialPortReadRegister (R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
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return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
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}
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}
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@ -152,7 +472,9 @@ SerialPortInitialize (
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)
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{
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RETURN_STATUS Status;
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UINTN Divisor;
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UINTN SerialRegisterBase;
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UINT32 Divisor;
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UINT32 CurrentDivisor;
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BOOLEAN Initialized;
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//
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@ -164,59 +486,78 @@ SerialPortInitialize (
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return Status;
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}
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//
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// Calculate divisor for baud generator
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// Ref_Clk_Rate / Baud_Rate / 16
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//
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Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);
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if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
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Divisor++;
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}
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//
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// Get the base address of the serial port in either I/O or MMIO space
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//
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SerialRegisterBase = GetSerialRegisterBase ();
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if (SerialRegisterBase ==0) {
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return RETURN_DEVICE_ERROR;
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}
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//
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// See if the serial port is already initialized
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//
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Initialized = TRUE;
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if ((SerialPortReadRegister (R_UART_FCR) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)) !=
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(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)) ) {
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if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
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Initialized = FALSE;
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}
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if ((SerialPortReadRegister (R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
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Initialized = FALSE;
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}
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SerialPortWriteRegister (R_UART_LCR, (UINT8)(SerialPortReadRegister (R_UART_LCR) | B_UART_LCR_DLAB));
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Divisor = SerialPortReadRegister (R_UART_BAUD_HIGH) << 8;
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Divisor |= (UINTN)SerialPortReadRegister (R_UART_BAUD_LOW);
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SerialPortWriteRegister (R_UART_LCR, (UINT8)(SerialPortReadRegister (R_UART_LCR) & ~B_UART_LCR_DLAB));
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if (Divisor != 115200 / PcdGet32 (PcdSerialBaudRate)) {
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
|
||||
CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
|
||||
CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
|
||||
if (CurrentDivisor != Divisor) {
|
||||
Initialized = FALSE;
|
||||
}
|
||||
if (Initialized) {
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
//
|
||||
// Wait for the serial port to be ready.
|
||||
// Verify that both the transmit FIFO and the shift register are empty.
|
||||
//
|
||||
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
|
||||
|
||||
//
|
||||
// Configure baud rate
|
||||
//
|
||||
Divisor = 115200 / PcdGet32 (PcdSerialBaudRate);
|
||||
SerialPortWriteRegister (R_UART_LCR, B_UART_LCR_DLAB);
|
||||
SerialPortWriteRegister (R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
|
||||
SerialPortWriteRegister (R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
|
||||
|
||||
//
|
||||
// Clear DLAB and configure Data Bits, Parity, and Stop Bits.
|
||||
// Strip reserved bits from PcdSerialLineControl
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
|
||||
|
||||
//
|
||||
// Enable and reset FIFOs
|
||||
// Strip reserved bits from PcdSerialFifoControl
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & 0x27));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
|
||||
|
||||
//
|
||||
// Put Modem Control Register(MCR) into its reset state of 0x00.
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_MCR, 0x00);
|
||||
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Write data from buffer to serial device.
|
||||
|
||||
|
||||
Writes NumberOfBytes data bytes from Buffer to the serial device.
|
||||
The number of bytes actually written to the serial device is returned.
|
||||
If the return value is less than NumberOfBytes, then the write operation failed.
|
||||
|
|
@ -238,16 +579,22 @@ EFIAPI
|
|||
SerialPortWrite (
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
)
|
||||
{
|
||||
UINTN Result;
|
||||
UINTN Index;
|
||||
UINTN FifoSize;
|
||||
UINTN SerialRegisterBase;
|
||||
UINTN Result;
|
||||
UINTN Index;
|
||||
UINTN FifoSize;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
SerialRegisterBase = GetSerialRegisterBase ();
|
||||
if (SerialRegisterBase ==0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (NumberOfBytes == 0) {
|
||||
//
|
||||
// Flush the hardware
|
||||
|
|
@ -256,12 +603,12 @@ SerialPortWrite (
|
|||
//
|
||||
// Wait for both the transmit FIFO and shift register empty.
|
||||
//
|
||||
while ((SerialPortReadRegister (R_UART_LSR) & B_UART_LSR_TEMT) == 0);
|
||||
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
|
||||
|
||||
//
|
||||
// Wait for the hardware flow control signal
|
||||
//
|
||||
while (!SerialPortWritable ());
|
||||
while (!SerialPortWritable (SerialRegisterBase));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -273,7 +620,7 @@ SerialPortWrite (
|
|||
if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
|
||||
FifoSize = 16;
|
||||
} else {
|
||||
FifoSize = 64;
|
||||
FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -283,7 +630,7 @@ SerialPortWrite (
|
|||
// Wait for the serial port to be ready, to make sure both the transmit FIFO
|
||||
// and shift register empty.
|
||||
//
|
||||
while ((SerialPortReadRegister (R_UART_LSR) & B_UART_LSR_TEMT) == 0);
|
||||
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
|
||||
|
||||
//
|
||||
// Fill then entire Tx FIFO
|
||||
|
|
@ -292,12 +639,12 @@ SerialPortWrite (
|
|||
//
|
||||
// Wait for the hardware flow control signal
|
||||
//
|
||||
while (!SerialPortWritable ());
|
||||
while (!SerialPortWritable (SerialRegisterBase));
|
||||
|
||||
//
|
||||
// Write byte to the transmit buffer.
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_TXBUF, *Buffer);
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
|
||||
}
|
||||
}
|
||||
return Result;
|
||||
|
|
@ -319,8 +666,9 @@ EFIAPI
|
|||
SerialPortRead (
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
)
|
||||
{
|
||||
UINTN SerialRegisterBase;
|
||||
UINTN Result;
|
||||
UINT8 Mcr;
|
||||
|
||||
|
|
@ -328,36 +676,42 @@ SerialPortRead (
|
|||
return 0;
|
||||
}
|
||||
|
||||
Mcr = (UINT8)(SerialPortReadRegister (R_UART_MCR) & ~B_UART_MCR_RTS);
|
||||
SerialRegisterBase = GetSerialRegisterBase ();
|
||||
if (SerialRegisterBase ==0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
|
||||
|
||||
for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
|
||||
//
|
||||
// Wait for the serial port to have some data.
|
||||
//
|
||||
while ((SerialPortReadRegister (R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
|
||||
while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
|
||||
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||||
//
|
||||
// Set RTS to let the peer send some data
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
|
||||
}
|
||||
}
|
||||
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||||
//
|
||||
// Clear RTS to prevent peer from sending data
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_MCR, Mcr);
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
|
||||
}
|
||||
|
||||
//
|
||||
// Read byte from the receive buffer.
|
||||
//
|
||||
*Buffer = SerialPortReadRegister (R_UART_RXBUF);
|
||||
*Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
|
||||
}
|
||||
|
||||
return Result;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Polls a serial device to see if there is any data waiting to be read.
|
||||
|
||||
|
|
@ -375,15 +729,22 @@ SerialPortPoll (
|
|||
VOID
|
||||
)
|
||||
{
|
||||
UINTN SerialRegisterBase;
|
||||
|
||||
SerialRegisterBase = GetSerialRegisterBase ();
|
||||
if (SerialRegisterBase ==0) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
//
|
||||
// Read the serial port status
|
||||
//
|
||||
if ((SerialPortReadRegister (R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
|
||||
if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
|
||||
if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
|
||||
//
|
||||
// Clear RTS to prevent peer from sending data
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_MCR, (UINT8)(SerialPortReadRegister (R_UART_MCR) & ~B_UART_MCR_RTS));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
|
@ -392,7 +753,7 @@ SerialPortPoll (
|
|||
//
|
||||
// Set RTS to let the peer send some data
|
||||
//
|
||||
SerialPortWriteRegister (R_UART_MCR, (UINT8)(SerialPortReadRegister (R_UART_MCR) | B_UART_MCR_RTS));
|
||||
SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
## @file
|
||||
# SerialPortLib instance for 16550 UART
|
||||
# SerialPortLib instance for 16550 UART.
|
||||
#
|
||||
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -15,6 +15,7 @@
|
|||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BaseSerialPortLib16550
|
||||
MODULE_UNI_FILE = BaseSerialPortLib16550.uni
|
||||
FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
|
|
@ -28,15 +29,19 @@
|
|||
PcdLib
|
||||
IoLib
|
||||
PlatformHookLib
|
||||
PciLib
|
||||
|
||||
[Sources]
|
||||
BaseSerialPortLib16550.c
|
||||
|
||||
[Pcd]
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMETIMES_CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo ## CONSUMES
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSUMES
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -695,6 +695,26 @@
|
|||
## Default Creator Revision for ACPI table creation.
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038
|
||||
|
||||
## UART clock frequency is for the baud rate configuration.
|
||||
# @Prompt Serial Port Clock Rate
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|1843200|UINT32|0x00010066
|
||||
|
||||
## PCI Serial Device Info. It is an array of Device, Function, and Power Management
|
||||
# information that describes the path that contains zero or more PCI to PCI briges
|
||||
# followed by a PCI serial device. Each array entry is 4-bytes in length. The
|
||||
# first byte is the PCI Device Number, then second byte is the PCI Function Number,
|
||||
# and the last two bytes are the offset to the PCI power management capabilities
|
||||
# register used to manage the D0-D3 states. If a PCI power management capabilities
|
||||
# register is not present, then the last two bytes in the offset is set to 0. The
|
||||
# array is terminated by an array entry with a PCI Device Number of 0xFF. For a
|
||||
# non-PCI fixed address serial device, such as an ISA serial device, the value is 0xFF.
|
||||
# @Prompt Pci Serial Device Info
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xFF}|VOID*|0x00010067
|
||||
|
||||
## Serial Port Extended Transmit FIFO Size. The default is 64 bytes.
|
||||
# @Prompt Pci Port Extended Transmit FIFO Size in Bytes
|
||||
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|64|UINT32|0x00010068
|
||||
|
||||
[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
|
||||
## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
|
||||
# This PCD could be set to 0 then console output could be at max column and max row.
|
||||
|
|
|
|||
Loading…
Reference in New Issue