mirror of https://github.com/acidanthera/audk.git
IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Kuo, Ted
mergify[bot]
parent
c8fb724046
commit
3182843f3b
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@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi):
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SAVE_EAX
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SAVE_EDX
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CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
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SAVE_ECX ; save UPD param to slot 3 in xmm6
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;
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; Sec Platform Init
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;
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CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
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CALL_MMX ASM_PFX(SecPlatformInit)
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cmp eax, 0
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jnz TempRamInitExit
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; Load microcode
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LOAD_ESP
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CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
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LOAD_ECX
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CALL_MMX ASM_PFX(LoadMicrocodeDefault)
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SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.
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SAVE_UCODE_STATUS ; Save microcode return status in slot 1 in xmm5.
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;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
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; Call Sec CAR Init
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LOAD_ESP
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CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
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LOAD_ECX
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CALL_MMX ASM_PFX(SecCarInit)
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cmp eax, 0
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jnz TempRamInitExit
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LOAD_ESP
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CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
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mov edi, ecx ; Save UPD param to EDI for later code use
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LOAD_ECX
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mov edi, ecx ; Save UPD param to EDI for later code use
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CALL_MMX ASM_PFX(EstablishStackFsp)
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cmp eax, 0
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jnz TempRamInitExit
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LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
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SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.
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LOAD_UCODE_STATUS ; Restore microcode status if no CAR init error from slot 1 in xmm5.
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TempRamInitExit:
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mov bl, al ; save al data in bl
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@ -7,6 +7,8 @@
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SECTION .text
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FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
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global ASM_PFX(FspInfoHeaderRelativeOff)
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ASM_PFX(FspInfoHeaderRelativeOff):
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DD 0x12345678 ; This value must be patched by the build script
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@ -14,7 +16,7 @@ ASM_PFX(FspInfoHeaderRelativeOff):
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global ASM_PFX(AsmGetFspBaseAddress)
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ASM_PFX(AsmGetFspBaseAddress):
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call ASM_PFX(AsmGetFspInfoHeader)
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add eax, 0x1C
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add eax, FSP_HEADER_IMGBASE_OFFSET
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mov eax, dword [eax]
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ret
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@ -1,6 +1,6 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Abstract:
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@ -16,21 +16,21 @@
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;
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; Define SSE macros using SSE 4.1 instructions
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; args 1:XMM, 2:IDX, 3:REG
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%macro SXMMN 3
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%macro SXMMN 3
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pinsrd %1, %3, (%2 & 3)
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%endmacro
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;
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;args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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%macro LXMMN 3
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pextrd %2, %1, (%3 & 3)
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%endmacro
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%else
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;
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; Define SSE macros using SSE 2 instructions
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; args 1:XMM, 2:IDX, 3:REG
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%macro SXMMN 3
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%macro SXMMN 3
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pinsrw %1, %3, (%2 & 3) * 2
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ror %3, 16
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pinsrw %1, %3, (%2 & 3) * 2 + 1
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@ -38,19 +38,19 @@
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%endmacro
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;
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;args 1:XMM, 2:REG, 3:IDX
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;args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)
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pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh)
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movd %2, %1
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pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
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pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh)
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%endmacro
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%endif
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;
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; XMM7 to save/restore EBP, EBX, ESI, EDI
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; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slot 3
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;
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%macro SAVE_REGS 0
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%macro SAVE_REGS 0
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SXMMN xmm7, 0, ebp
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SXMMN xmm7, 1, ebx
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SXMMN xmm7, 2, esi
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@ -67,63 +67,67 @@
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%endmacro
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;
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; XMM6 to save/restore EAX, EDX, ECX, ESP
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; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slot 3
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;
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%macro LOAD_EAX 0
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LXMMN xmm6, eax, 1
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%macro LOAD_ESP 0
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movd esp, xmm6
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%endmacro
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%macro SAVE_EAX 0
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SXMMN xmm6, 1, eax
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%endmacro
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%macro LOAD_EDX 0
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LXMMN xmm6, edx, 2
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%endmacro
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%macro SAVE_EDX 0
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SXMMN xmm6, 2, edx
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%endmacro
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%macro SAVE_ECX 0
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SXMMN xmm6, 3, ecx
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%endmacro
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%macro LOAD_ECX 0
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LXMMN xmm6, ecx, 3
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%endmacro
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%macro SAVE_ESP 0
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%macro SAVE_ESP 0
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SXMMN xmm6, 0, esp
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%endmacro
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%macro LOAD_ESP 0
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movd esp, xmm6
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%macro LOAD_EAX 0
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LXMMN xmm6, eax, 1
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%endmacro
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%macro SAVE_EAX 0
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SXMMN xmm6, 1, eax
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%endmacro
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%macro LOAD_EDX 0
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LXMMN xmm6, edx, 2
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%endmacro
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%macro SAVE_EDX 0
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SXMMN xmm6, 2, edx
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%endmacro
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%macro LOAD_ECX 0
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LXMMN xmm6, ecx, 3
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%endmacro
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%macro SAVE_ECX 0
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SXMMN xmm6, 3, ecx
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%endmacro
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;
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; XMM5 for calling stack
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; XMM5 slot 0 for calling stack
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; arg 1:Entry
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%macro CALL_XMM 1
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mov esi, %%ReturnAddress
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pslldq xmm5, 4
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%ifdef USE_SSE41_FLAG
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pinsrd xmm5, esi, 0
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%else
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pinsrw xmm5, esi, 0
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ror esi, 16
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pinsrw xmm5, esi, 1
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%endif
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SXMMN xmm5, 0, esi
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mov esi, %1
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jmp esi
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%%ReturnAddress:
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%endmacro
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%macro RET_XMM 0
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movd esi, xmm5
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psrldq xmm5, 4
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LXMMN xmm5, esi, 0
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jmp esi
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%endmacro
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;
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; XMM5 slot 1 for uCode status
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;
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%macro LOAD_UCODE_STATUS 0
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LXMMN xmm5, eax, 1
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%endmacro
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%macro SAVE_UCODE_STATUS 0
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SXMMN xmm5, 1, eax
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%endmacro
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%macro ENABLE_SSE 0
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;
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; Initialize floating point units
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@ -79,7 +79,7 @@ AsmGetFspBaseAddress (
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/**
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This interface gets FspInfoHeader pointer
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@return FSP binary base address.
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@return FSP info header.
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**/
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UINTN
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@ -7,10 +7,12 @@
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DEFAULT REL
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SECTION .text
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FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
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global ASM_PFX(AsmGetFspBaseAddress)
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ASM_PFX(AsmGetFspBaseAddress):
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call ASM_PFX(AsmGetFspInfoHeader)
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add rax, 0x1C
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add rax, FSP_HEADER_IMGBASE_OFFSET
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mov eax, [rax]
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ret
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